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`Symmetric multiprocessing - Wikipedia
`
`Symmetric multiprocessing
`
`Symmetric multiprocessing (SMP)
`involves a multiprocessor computer
`hardware and
`software architecture
`where two or more identical processors
`are connected to a single, shared main
`memory, have full access to all input and
`output devices, and are controlled by a
`single operating system instance that
`treats all processors equally, reserving
`none
`for
`special purposes. Most
`multiprocessor systems today use an
`SMP architecture. In the case of multi-
`core processors, the SMP architecture
`applies to the cores, treating them as
`separate processors.
`
`Diagram of a symmetric multiprocessing system
`
`Professor John D. Kubiatowicz considers
`traditionally SMP systems to contain processors without caches.[1] Culler and Pal-Singh in their 1998 book "Parallel
`Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of
`confusion. [...] The more precise description of what is intended by SMP is a shared memory multiprocessor where the
`cost of accessing a memory location is the same for all processors; that is, it has uniform access costs when the access
`actually is to memory. If the location is cached, the access will be faster, but cache access times and memory access times
`are the same on all processors."[2]
`
`SMP systems are tightly coupled multiprocessor systems with a pool of homogeneous processors running independently
`of each other. Each processor, executing different programs and working on different sets of data, has the capability of
`sharing common resources (memory, I/O device, interrupt system and so on) that are connected using a system bus or a
`crossbar.
`
`Contents
`Design
`History
`Uses
`Advantages/Disadvantages
`Programming
`Performance
`Alternatives
`Variable SMP
`See also
`References
`https://en.wikipedia.org/wiki/Symmetric_multiprocessing
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`External links
`
`Design
`
`Symmetric multiprocessing - Wikipedia
`
`SMP systems have centralized shared memory called main memory (MM) operating under a single operating system with
`two or more homogeneous processors. Usually each processor has an associated private high-speed memory known as
`cache memory (or cache) to speed up the main memory data access and to reduce the system bus traffic.
`
`Processors may be interconnected using buses, crossbar switches or on-chip mesh networks. The bottleneck in the
`scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among
`the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly
`linear scalability to much higher processor counts at the sacrifice of programmability:
`
`Serious programming challenges remain with this kind of architecture because it requires two distinct
`modes of programming; one for the CPUs themselves and one for the interconnect between the CPUs. A
`single programming language would have to be able to not only partition the workload, but also comprehend
`the memory locality, which is severe in a mesh-based architecture.[3]
`
`SMP systems allow any processor to work on any task no matter where the data for that task is located in memory,
`provided that each task in the system is not in execution on two or more processors at the same time. With proper
`operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently.
`
`History
`
`The earliest production system with multiple identical processors was the Burroughs B5000, which was functional around
`1961. However at run-time this was asymmetric, with one processor restricted to application programs while the other
`processor mainly handled the operating system and hardware interrupts. The Burroughs D825 first implemented SMP in
`1962.[4][5]
`
`IBM offered dual-processor computer systems based on its System/360 model 65 and the closely related model 67[6] and
`67-2.[7] The operating systems that ran on these machines were OS/360 M65MP[8] and TSS/360. Other software
`developed at universities, notably the Michigan Terminal System (MTS), used both CPUs. Both processors could access
`data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the
`operating system kernel ran on both processors (though with a "big lock" around the I/O handler).[9] The MTS supervisor
`(UMMPS) has the ability to run on both CPUs of the IBM System/360 model 67-2. Supervisor locks were small and used
`to protect individual common data structures that might be accessed simultaneously from either CPU.[10]
`
`Other mainframes that supported SMP included the UNIVAC 1108 II, released in 1965, which supported up to three CPUs,
`and the GE-635 and GE-645,[11][12] although GECOS on multiprocessor GE-635 systems ran in a master-slave asymmetric
`fashion, unlike Multics on multiprocessor GE-645 systems, which ran in a symmetric fashion.[13]
`
`Starting with its version 7.0 (1972), Digital Equipment Corporation's operating system TOPS-10 implemented the SMP
`feature, the earliest system running SMP was the DECSystem 1077 dual KI10 processor system.[14] Later KL10 system
`could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processor VAX system, the VAX-11/782, was
`asymmetric,[15] but later VAX multiprocessor systems were SMP.[16]
`
`https://en.wikipedia.org/wiki/Symmetric_multiprocessing
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`Early commercial Unix SMP implementations included the Sequent Computer Systems Balance 8000 (released in 1984)
`and Balance 21000 (released in 1986).[17] Both models were based on 10 MHz National Semiconductor NS32032
`processors, each with a small write-through cache connected to a common memory to form a shared memory system.
`Another early commercial Unix SMP implementation was the NUMA based Honeywell Information Systems Italy XPS-
`100 designed by Dan Gielan of VAST Corporation in 1985. Its design supported up to 14 processors, but due to electrical
`limitations, the largest marketed version was a dual processor system. The operating system was derived and ported by
`VAST Corporation from AT&T 3B20 Unix SysVr3 code used internally within AT&T.
`
`Earlier non-commercial multiprocessing UNIX ports existed, including a port named MUNIX created at the Naval
`Postgraduate School by 1975[18].
`
`Uses
`
`Time-sharing and server systems can often use SMP without changes to applications, as they may have multiple processes
`running in parallel, and a system with more than one process running can run different processes on different processors.
`
`On personal computers, SMP is less useful for applications that have not been modified. If the system rarely runs more
`than one process at a time, SMP is useful only for applications that have been modified for multithreaded (multitasked)
`processing. Custom-programmed software can be written or modified to use multiple threads, so that it can make use of
`multiple processors.
`
`Multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them
`to make more use of multiple processors.
`
`Advantages/Disadvantages
`
`In SMP, all of the processors are tightly coupled inside the same box with a bus or switch. Some of the components that
`are shared are global memory, disks, and I/O devices. Only one copy of an OS runs on all the processors, and the OS must
`be designed to take advantage of this architecture. Some of the basic advantages involves cost-effective ways to increase
`throughput. To solve different problems and tasks, SMP applies multiple processors to that one problem, known as
`parallel programming.
`
`However, there are a few limits on the scalability of SMP due to cache coherence and shared objects.
`
`Programming
`
`Uniprocessor and SMP systems require different programming methods to achieve maximum performance. Programs
`running on SMP systems may experience an increase in performance even when they have been written for uniprocessor
`systems. This is because hardware interrupts usually suspends program execution while the kernel that handles them can
`execute on an idle processor instead. The effect in most applications (e.g. games) is not so much a performance increase as
`the appearance that the program is running much more smoothly. Some applications, particularly building software and
`some distributed computing projects, run faster by a factor of (nearly) the number of additional processors. (Compilers by
`themselves are single threaded, but, when building a software project with multiple compilation units, if each compilation
`unit is handled independently, this creates an embarrassingly parallel situation across the entire multi-compilation-unit
`project, allowing near linear scaling of compilation time. Distributed computing projects are inherently parallel by design.)
`
`Systems programmers must build support for SMP into the operating system, otherwise, the additional processors remain
`idle and the system functions as a uniprocessor system.
`
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`SMP systems can also lead to more complexity regarding instruction sets. A homogeneous processor system typically
`requires extra registers for "special instructions" such as SIMD (MMX, SSE, etc.), while a heterogeneous system can
`implement different types of hardware for different instructions/uses.
`
`Performance
`
`When more than one program executes at the same time, an SMP system has considerably better performance than a uni-
`processor, because different programs can run on different CPUs simultaneously. Similarly, Asymmetric multiprocessing
`(AMP) usually allows only one processor to run a program or task at a time. For example, AMP can be used in assigning
`specific tasks to CPU based to priority and importance of task completion. AMP was created well before SMP in terms of
`handling multiple CPUs, which explains the lack of performance based on the example provided.
`
`In cases where an SMP environment processes many jobs, administrators often experience a loss of hardware efficiency.
`Software programs have been developed to schedule jobs and other functions of the computer so that the processor
`utilization reaches its maximum potential. Good software packages can achieve this maximum potential by scheduling
`each CPU separately, as well as being able to integrate multiple SMP machines and clusters.
`
`Access to RAM is serialized; this and cache coherency issues causes performance to lag slightly behind the number of
`additional processors in the system.
`
`Alternatives
`
`SMP uses a single shared system bus that represents one
`of
`the earliest styles of multiprocessor machine
`architectures,
`typically used
`for building smaller
`computers with up to 8 processors.
`
`Larger computer systems might use newer architectures
`such as NUMA (Non-Uniform Memory Access), which
`dedicates different memory banks
`to different
`processors. In a NUMA architecture, processors may
`access local memory quickly and remote memory more
`slowly. This can dramatically
`improve memory
`throughput as long as the data are localized to specific
`processes (and thus processors). On the downside,
`NUMA makes the cost of moving data from one processor to another, as in workload balancing, more expensive. The
`benefits of NUMA are limited to particular workloads, notably on servers where the data are often associated strongly with
`certain tasks or users.
`
`Diagram of a typical SMP system. Three processors are
`connected to the same memory module through a system
`bus or crossbar switch
`
`Finally, there is computer clustered multiprocessing (such as Beowulf), in which not all memory is available to all
`processors. Clustering techniques are used fairly extensively to build very large supercomputers.
`
`Variable SMP
`
`Variable Symmetric Multiprocessing (vSMP) is a specific mobile use case technology initiated by NVIDIA. This technology
`includes an extra fifth core in a quad-core device, called the Companion core, built specifically for executing tasks at a
`lower frequency during mobile active standby mode, video playback, and music playback.
`
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`Project Kal-El (Tegra 3),[19] patented by NVIDIA, was the first SoC (System on Chip) to implement this new vSMP
`technology. This technology not only reduces mobile power consumption during active standby state, but also maximizes
`quad core performance during active usage for intensive mobile applications. Overall this technology addresses the need
`for increase in battery life performance during active and standby usage by reducing the power consumption in mobile
`processors.
`
`Unlike current SMP architectures, the vSMP Companion core is OS transparent meaning that the operating system and
`the running applications are totally unaware of this extra core but are still able to take advantage of it. Some of the
`advantages of the vSMP architecture includes cache coherency, OS efficiency, and power optimization. The advantages for
`this architecture are explained below:
`
`Cache Coherency: There are no consequences for synchronizing caches between cores running at different
`frequencies since vSMP does not allow the Companion core and the main cores to run simultaneously.
`OS Efficiency: It is inefficient when multiple CPU cores are run at different asynchronous frequencies because this
`could lead to possible scheduling issues. With vSMP, the active CPU cores will run at similar frequencies to optimize
`OS scheduling.
`Power Optimization: In asynchronous clocking based architecture, each core is on a different power plane to handle
`voltage adjustments for different operating frequencies. The result of this could impact performance. vSMP
`technology is able to dynamically enable and disable certain cores for active and standby usage, reducing overall
`power consumption.
`These advantages lead the vSMP architecture to considerably benefit over other architectures using asynchronous clocking
`technologies.
`
`See also
`
`Binary Modular Dataflow Machine
`Locale (computer hardware)
`Massively parallel
`Partitioned global address space
`Simultaneous multithreading – where functional elements of a CPU core are allocated across multiple threads of
`execution
`Software lockout
`Xeon Phi
`References
`
`1. John Kubiatowicz. Introduction to Parallel Architectures and Pthreads (https://parlab.eecs.berkeley.edu/2013bootcam
`pagenda). 2013 Short Course on Parallel Programming.
`2. David Culler; Jaswinder Pal Singh; Anoop Gupta (1999). Parallel Computer Architecture: A Hardware/Software
`Approach (https://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA32). Morgan Kaufmann. p. 47. ISBN 978-
`1558603431.
`3. Lina J. Karam, Ismail AlKamal, Alan Gatherer, Gene A. Frantz, David V. Anderson, Brian L. Evans (2009). "Trends in
`Multi-core DSP Platforms" (http://users.ece.utexas.edu/~bevans/papers/2009/multicore/MulticoreDSPsForIEEESPMF
`inal.pdf) (PDF). IEEE Signal Processing Magazine, Special Issue on Signal Processing on Platforms with Multiple
`Cores.
`4. Gregory V. Wilson (October 1994). "The History of the Development of Parallel Computing" (http://ei.cs.vt.edu/~histor
`y/Parallel.html).
`5. Martin H. Weik (January 1964). "A Fourth Survey of Domestic Electronic Digital Computing Systems" (http://ed-thele
`n.org/comp-hist/BRL64-b.html#BURROUGHS-D825). Ballistic Research Laboratories, Aberdeen Proving Grounds.
`Burroughs D825.
`
`https://en.wikipedia.org/wiki/Symmetric_multiprocessing
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`6. IBM System/360 Model 65 Functional Characteristics (http://www.bitsavers.org/pdf/ibm/360/funcChar/A22-6884-3_36
`0-65_funcChar.pdf) (PDF). Fourth Edition. IBM. September 1968. A22-6884-3.
`7. IBM System/360 Model 67 Functional Characteristics (http://www.bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_3
`60-67_funcChar.pdf) (PDF). Third Edition. IBM. February 1972. GA27-2719-2.
`8. M65MP: An Experiment in OS/360 multiprocessing (http://doi.acm.org/10.1145/800186.810634)
`9. Program Logic Manual, OS I/O Supervisor Logic, Release 21 (R21.7) (http://bitsavers.org/pdf/ibm/360/os/R21.7_Apr7
`3/plm/GY28-6616-9_OS_IO_Superv_PLM_R21.7_Apr73.pdf) (PDF) (Tenth ed.). IBM. April 1973. GY28-6616-9.
`10. Time Sharing Supervisor Programs (https://1a9f2076-a-62cb3a1a-s-sites.googlegroups.com/site/michiganterminalsys
`tem/documentation/documents/timeSharingSupervisorPrograms-1971.pdf?attachauth=ANoY7crPBadRVtxTmN8sqSj
`Fc3xC84Q_pDpvpRo7VRWz0_Ql-UKQ2SVe6hJ7lVOjGZbLkOSXco8c9_ZI6TmQZS8EpBTMlByIPM4iByyUXlXE__Yf
`WN0jqwIQglhyvR0oSxl0I_C0JenDItLzN4btLtkug9HSHRX1s-WtlkSQ-pzJLpczJYsuzTvZVIggSTW0arjTnQsls6xcrCsM
`cyl58Y98Q0Sw2yecmFLiTcYjnYrgAhLGSu9b2s28oV04R6_6p6fD8UUjvnRawHn7N6qFgRIEuGj4QuZlkthZM5_fZwaP
`yXvLxccgLCk%3D&attredirects=0) by Mike Alexander (May 1971) has information on MTS, TSS, CP/67, and Multics
`11. GE-635 System Manual (http://www.bitsavers.org/pdf/ge/GE-6xx/CPB-371A_GE-635_System_Man_Jul64.pdf) (PDF).
`General Electric. July 1964.
`12. GE-645 System Manual (http://www.bitsavers.org/pdf/ge/GE-645/GE-645_SystemMan_Jan68.pdf) (PDF). General
`Electric. January 1968.
`13. Richard Shetron (May 5, 1998). "Fear of Multiprocessing?" (https://groups.google.com/d/msg/alt.folklore.computers/v-
`hkdKaPTXc/MX7UI3DgOokJ). Newsgroup: alt.folklore.computers (news:alt.folklore.computers).
`Usenet: 354e95a9.0@news.wizvax.net (news:354e95a9.0@news.wizvax.net).
`14. DEC 1077 and SMP (http://www.ultimate.com/phil/pdp10/10periphs)
`15. VAX Product Sales Guide, pages 1-23 and 1-24 (http://www.bitsavers.org/pdf/dec/vax/EG-21731-18_VAX_Product_S
`ales_Guide_Apr82.pdf): the VAX-11/782 is described as an asymmetric multiprocessing system in 1982
`16. VAX 8820/8830/8840 System Hardware User's Guide (http://www.bitsavers.org/pdf/dec/vax/8800/EK-8840H-UG-001_
`88xx_System_Hardware_Users_Guide_Mar88.pdf): by 1988 the VAX operating system was SMP
`17. Hockney, R.W.; Jesshope, C.R. (1988). Parallel Computers 2: Architecture, Programming and Algorithms. Taylor &
`Francis. p. 46. ISBN 0-85274-811-6.
`18. Hawley, John Alfred (June 1975). "MUNIX, A Multiprocessing Version Of UNIX" (https://core.ac.uk/download/pdf/3671
`4194.pdf) (PDF). core.ac.uk. Retrieved 11 November 2018.
`19. Variable SMP – A Multi-Core CPU Architecture for Low Power and High Performance. NVIDIA. 2011. (http://www.nvid
`ia.com/content/pdf/tegra_white_papers/tegra-whitepaper-0911b.pdf)
`
`External links
`
`History of Multi-Processing (http://ei.cs.vt.edu/~history/Parallel.html)
`Linux and Multiprocessing (http://www.ibm.com/developerworks/library/l-linux-smp/)
`AMD (https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118,00.html)
`
`Retrieved from "https://en.wikipedia.org/w/index.php?title=Symmetric_multiprocessing&oldid=895110125"
`
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