UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`MICROSOFT CORPORATION,
`Petitioner,
`v.
`DIRECTSTREAM, LLC,
`Patent Owner.
`_______________________
`
`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01602 (Patent 7,225,324 B2)
`IPR2018-01603 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
`IPR2018-01606 (Patent 7,620,800 B2)
`IPR2018-01607 (Patent 7,620,800 B2)
`__________________________
`
`DECLARATION OF DR. HOUMAN HOMAYOUN
`
`1
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 1
`
`

`

`TABLE OF CONTENTS
`
`I. PURPOSE OF DECLARATION ............................................................................ 1 
`II. MATERIALS REVIEWED AND CONSIDERED ............................................... 2 
`III. EXPERIENCE AND QUALIFICATIONS .......................................................... 3 
`IV. PRIOR TESTIMONY .......................................................................................... 5 
`V. LEGAL STANDARDS PROVIDED ..................................................................... 6 
`VI. OVERVIEW OF HIGH-PERFORMANCE RECONFIGURABLE
`COMPUTING AND THE PRIOR ART SYSTEMS ..................................... 10 
`A. Background ....................................................................................................... 10 
`B. High Performance Computing (“HPC”) – Definition and Evaluation Metrics ... 19 
`C. System Architecture – It’s Impact on HPC ........................................................ 22 
`D. History of HPC ................................................................................................. 23 
`E. Overview of Cost/Benefit Decision Making for HPC Architects ........................ 27 
`F. Memory – A Hurdle to Enhance HPC Architectures ......................................... 29 
`G. HPC Techniques for Optimization of Single-Processor Systems ........................ 32 
`H. Multi-Processor Systems ................................................................................... 35 
`I. Reconfigurable Computing and FPGAs ............................................................. 50 
`J. FPGAs and HPC Systems .................................................................................. 55 
`K. Web Server State of the Art ............................................................................... 58 
`VII. THE PATENTS-IN-SUIT ................................................................................. 59 
`A. The ’324 Patent ................................................................................................. 59 
`B. The ’800 Patent ................................................................................................. 60 
`VIII. LEVEL OF ORDINARY SKILL IN THE ART .............................................. 64 
`A. My POSITA Definition ..................................................................................... 64 
`
`i
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`
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 2
`
`

`

`B. My Understanding and Disagreement of Microsoft’s POSITA Definition that
`Uses Hindsight Bias .......................................................................................... 68 
`IX. KEY TERMS FROM THE PATENTS-IN-SUIT ............................................... 72 
`A. The Board’s Claim Constructions ...................................................................... 72 
`1. ’324 Patent .................................................................................................. 72 
`2. ’800 Patent .................................................................................................. 72 
`B. My Opinions on Claim Construction ................................................................. 73 
`1. Stream communication connection .............................................................. 73 
`2. “Pass computed data seamlessly between said computational loops” ........... 76 
`3. The terms seamless, systolic, and data driven have distinct meanings. .......... 79 
`X. ANALYSIS OF MICROSOFT’S PRIOR ART REFERENCES .......................... 80 
`A. Teachings of Splash2 ......................................................................................... 80 
`1. Splash2 does not teach a “stream communication connection.” ................... 80 
`2. Splash2 does not teach computational loops. ............................................... 84 
`3. Splash2 requires memory between the PEs. ................................................. 87 
`B. Chunky SLD does not teach computational loops. ............................................ 91 
`C. Jeong does not teach computational loops. ........................................................ 92 
`D. Roccatano does not teach computational loops. ................................................ 93 
`E. RaPid does not teach computational loops. ....................................................... 93 
`XI. DR. STONE FAILS TO APPLY HIS OWN RUBRIC FOR ANALYZING
`FEASIBILITY FOR ANY OF THE PROPOSED MODIFICATIONS AND
`COMBINATIONS OF THE ASSERTED PRIOR ART ................................ 95 
`XII. CLOSING MATTERS ...................................................................................... 99 
`
`
`
`
`
`ii
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 3
`
`

`

`
`
`I. PURPOSE OF DECLARATION
` My name is Dr. Houman Homayoun. I have personal knowledge of the facts
`
`contained in this declaration, am of legal age, and am otherwise competent to testify.
`
` I have been retained as an expert by Patent Owner on the patentability of
`
`patents owned by DirectStream, LLC (“DirectStream”) regarding high-performance
`
`reconfigurable computing. I have previously submitted a declaration in co-pending U.S.
`
`District court cases against Microsoft and Amazon related to certain claim construction
`
`issues.
`
` It is my understanding that Microsoft has filed and the Board has instituted 10
`
`IPR Petitions (IPR2018-01594, -1599, -1600, -1601, -1602, -1603, -1604, -1605, -1606,
`
`-1607) (I understand that the -1601, -1602, and -1603 have been consolidated into one
`
`IPR and that the -1605, -1606, and -1607 have been consolidated into one IPR).
`
` I have reviewed the IPR Petitions and attached exhibits, Patent Owner’s
`
`preliminary responses and attached exhibits, the Board’s institution decisions, and
`
`evidence submitted by Microsoft and the Patent Owner in all 10 IPRs. I have been
`
`asked to provide my expert opinions on the patentability of DirectStream’s patents and
`
`why Microsoft’s alleged grounds of unpatentability instituted by the Board should not
`
`be sustained. I have been also asked to provide rebuttal opinions to the expert
`
`declarations and/or deposition testimony Microsoft submitted in conjunction with its
`
`IPR petitions.
`
`
`
`1
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 4
`
`

`

` In my professional opinion, all of the above-captioned IPR Petitions’ grounds
`
`of unpatentability would fail to meet the burden “by the preponderance of the evidence”
`
`with respect to any of the claims of U.S. Patent Nos. 6,434,687 (“’687”); 6,076,152
`
`(“’152”); 6,247,110 (“’110”) 7,225,324 (“’324”); 7,421,524 (“’524”); and 7,620,800
`
`(“’800”) (collectively, “the Patents-in-Suit”), and Microsoft would not prevail in its IPR
`
`challenges instituted by the PTAB for the reasons I explain below in this Declaration.1
`
`II. MATERIALS REVIEWED AND CONSIDERED
` My opinions are based on my years of education, research, and experience, as
`
`well as my review of the IPR petitions, the materials cited by Microsoft in the IPR
`
`petitions, and the Board’s institution decisions, specifically including the claims,
`
`specifications, prosecution histories, and various prior art references submitted during
`
`the prosecution of the Patents-in-Suit. In forming my opinion, I have considered the
`
`materials I identify in this report.
`
` A listing of key references I independently found are listed in Exhibit B
`
`hereto. Any material I independently searched for and found and/or reviewed and used
`
`to support my opinions will be specifically mentioned in my opinions below.
`
`
`1 The current declaration primarily focuses on my analysis of the ’324 and ’800
`Patents (-01601 & -01605 IPRs). However, for completeness, I also include a
`detailed state-of-art discussion of key concepts across all the Patents-in-Suit that a
`Person Skilled in the Art would understand at the time of the inventions disclosed
`– something I note Microsoft’s experts failed to undertake.
`
`2
`
`
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 5
`
`

`

` I was also provided deposition testimony from Dr. Harold Stone (two
`
`transcripts), Dr. Stephen Trimberger, Dr. Scott Hauck, and the Declaration of Jon
`
`Huppenthal and Tarek El-Ghazawi and the exhibits attached thereto. Additional
`
`documents provided to me are listed in Exhibit C. To the extent I relied on any of these
`
`materials, I identify them in this report.
`
` I may rely on these materials and additional materials to respond to arguments
`
`raised by the Petitioner. I may also consider additional documents and information as
`
`required to form any necessary opinions in this proceeding, including materials that I
`
`have not yet found or been provided.
`
` My analysis of the materials is ongoing and I will continue to review any
`
`new material as it is provided. This declaration only represents the opinions I have
`
`formed as of the date I sign it. I reserve the right to revise, supplement, or amend my
`
`opinions as needed based on new material or a new understanding of materials already
`
`considered.
`
`III. EXPERIENCE AND QUALIFICATIONS
` My curriculum vitae is attached as Exhibit A. A summary of my
`
`qualifications relevant to this case is provided below.
`
` I am an Associate Professor of Electrical and Computer Engineering at
`
`George Mason University (GMU). I am the director of GMU’s Accelerated, Secure,
`
`and Energy-Efficient Computing Laboratory (ASEEC). Prior to joining GMU, I spent
`
`
`
`
`3
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 6
`
`

`

`two years at the University of California, San Diego, as NSF Computing Innovation
`
`(CI) Fellow awarded by the CRA-CCC working with Professor Dean Tullsen.
`
` I currently have a pending patent application with a notice of allowance:
`
`US15/290,871.
`
` I worked in NOVELICS startup company as a design architect from January
`
`2007 to October 2008. I designed a reconfigurable and programmable processor
`
`referred as Built-in Self-test (BIST) to test various memory architecture.
`
` I am currently conducting research in big data computing, heterogeneous
`
`computing and hardware security and trust, which spans the areas of computer design
`
`and embedded systems, where I have published more than 80 technical papers in the
`
`prestigious conferences and journals on the subject.
`
` I am also currently leading six research projects funded by DARPA, AFRL
`
`and NSF on the topics of hardware security and trust, big data computing,
`
`heterogeneous architectures, and biomedical computing.
`
` I have successfully completed four projects on “Hybrid Spin Transfer
`
`Torque-CMOS Technology to Prevent Design Reverse Engineering”, “Persistence and
`
`Extraction of Digital Artifacts from Embedded Systems”, “Inter-core Selective
`
`Resource Pooling in a 3D Chip Multiprocessor”, and “Enhancing the Security on
`
`Embedded Automotive Systems” funded by DARPA, NIST, NSF and General Motors.
`
`
`
`
`4
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 7
`
`

`

` I received the 2016 Great Lakes Symposium on VLSI (GLSVLSI)
`
`conference best paper award for developing a manycore accelerator for wearable
`
`biomedical computing.
`
` I am currently serving as Member of Advisory Committee, Cybersecurity
`
`Research and Technology Commercialization (R&TC) working group in the
`
`Commonwealth of Virginia.
`
` Since 2017 I have been serving as an Associate Editor of IEEE Transactions
`
`on VLSI. I served as TPC Co-Chair for GLSVLSI 2018.
`
` I am currently the general chair of GLSVLSI 2019.
`
`IV. PRIOR TESTIMONY
` I have only previously testified in the co-pending district cases against
`
`Microsoft and Amazon and that was by deposition and declaration. Those cases are
`
`listed below:
`
` SRC Labs, LLC et al. v. Microsoft Corp., No. 2:18-cv-00321-JLR (W.D.
`
`Wash.).
`
` SRC Labs, LLC et al v. Amazon Web Services, Inc et al, No. 2:18-cv-00317-
`
`JLR (W.D. Wash.).
`
` I provided expert opinions in declaration form to support Patent Owner’s
`
`preliminary responses to the above mentioned IPRs. Specifically, Exhibit 2029 in the -
`
`
`
`
`5
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 8
`
`

`

`1601 IPR (-1602 IPR and -1603 IPR) and Exhibit 2029 in the -1605 IPR (-1606 IPR
`
`and -1607 IPR).
`
`V. LEGAL STANDARDS PROVIDED
` I understand a patent claim is invalid as anticipated when a single piece of
`
`prior art describes every element of the claimed invention, either expressly or
`
`inherently, is enabled, and arranged in the same way as in the claim. For inherent
`
`anticipation to be found, it is required that the missing descriptive material is
`
`necessarily present in the prior art.
`
` I understand that a patent claim is invalid as obvious if the subject matter of
`
`the claim as a whole would have been obvious to a person of ordinary skill in the art as
`
`of the time of the invention at issue. I understand that the following factors must be
`
`evaluated to determine whether the claimed subject matter is obvious: (1) the scope and
`
`content of the prior art; (2) the difference or differences, if any, between the scope of
`
`the claim of the patent under consideration and the scope of the prior art; and (3) the
`
`level of ordinary skill in the art at the time the patent was filed. Moreover, to avoid
`
`hindsight bias, such a person at the time of the invention would consider the scope of
`
`problems encountered in the art and the prior art solutions to these problems. Unlike
`
`anticipation, which allows consideration of only one item of prior art, I understand that
`
`obviousness may be shown by considering more than one item of prior art.
`
`
`
`
`6
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 9
`
`

`

` Furthermore, I have been informed that an invention composed of elements
`
`is not shown obvious merely by the demonstration that each element was known in the
`
`art. Instead, a motivation or reason to select the references to combine them requires an
`
`articulated or explicit reasoning with some rationale underpinning.
`
` Additionally, I have been informed that an inference of non-obviousness is
`
`strong if the prior art teaches “away” from the claimed invention and undermines the
`
`very reason it is being offered.
`
` I have also been informed and I understand that objective indicia of non-
`
`obviousness, also known as “secondary considerations,” like the following are also to
`
`be considered when assessing obviousness: (1) commercial success; (2) long-felt but
`
`unresolved needs; (3) copying of the invention by others in the field; (4) initial
`
`expressions of disbelief by experts in the field; (5) failure of others to solve the problem
`
`that the inventor solved; and (6) unexpected results. I also understand that evidence of
`
`objective indicia of non-obviousness must be commensurate in scope with the claimed
`
`subject matter, also known as a “nexus.”
`
` I understand that some claims are written in dependent form, in which case
`
`they incorporate all of the limitations of the claim(s) on which they depend. I
`
`understand that there are different claim construction standards used by the Patent
`
`Office and the federal district courts in evaluating the scope of a patent claim. It is my
`
`
`
`
`7
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 10
`
`

`

`understanding that the Patent Office uses the “broadest reasonable interpretation in light
`
`of the specification” in reviewing claims.
`
` I have been informed and I understand a patentability analysis is performed
`
`from the viewpoint of a hypothetical person of ordinary skill in the art (“POSITA”). I
`
`understand that “the person of ordinary skill” is a hypothetical person who is presumed
`
`to be aware of the universe of available prior art as of the time of the invention at issue
`
`and who can understand the terms of the various claims in the Patents-in-Suit.
`
` I have been informed and I considered several factors when determining a
`
`POSITA qualifications in this matter, including: (1) the prior art; (2) problems
`
`associated with the prior art; (3) the problem the Patents-in-Suit are attempting to solve;
`
`(4) the complexity of the prior art technologies, and (5) the level of education needed to
`
`understand the Patents-in-Suit.
`
` I understand that claim construction is the first step in the validity analysis of
`
`a patent and that claims are construed the same for both validity and infringement.
`
` I understand that in an inter partes review proceeding of an unexpired patent
`
`the claims are given their broadest reasonable interpretation in light of the specification.
`
`I understand that this standard is different than the standard applied by district courts
`
`when construing claims. I also understand that Patent Owner is asking the Board to
`
`apply the district court standard to the claims in these proceedings.
`
`
`
`
`8
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 11
`
`

`

` I have also been informed that ascertaining the meaning of the claims
`
`requires that they be viewed in the context of those sources available to the public that
`
`show what a person of skill in the art would have understood disputed claim language
`
`to mean. I have been informed that various courts have stated that different weights are
`
`to be placed on these sources. First, the words of the claims themselves provide the
`
`starting point for any claim-construction analysis. The second most relevant source is
`
`the patent's specification. Third in importance is the prosecution history, which is also
`
`part of the intrinsic evidence that directly reflects how the patentee has characterized the
`
`invention. Last, extrinsic evidence—testimony, dictionaries, learned treatises, or other
`
`material not part of the public record associated with the patent—also may be helpful
`
`but is less significant than the intrinsic record in determining the legally operative
`
`meaning of claim language.
`
` I have also been informed that when determining the “ordinary meaning” a
`
`claim term the use of technical dictionaries or even a standard dictionary, such as
`
`Webster's, is often appropriate. Generally, however, technical dictionaries in the
`
`relevant field should take precedence over general dictionaries.
`
` I do believe that the claims at issue in these proceedings should be construed
`
`the same way regardless of whether the Board applies the broadest reasonable
`
`interpretation standard or the district court claim construction standard.
`
`
`
`
`9
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 12
`
`

`

` My opinions herein are based on my application of the Board’s proposed
`
`claim constructions unless otherwise stated as discussed in greater detail below.
`
`VI. OVERVIEW OF HIGH-PERFORMANCE RECONFIGURABLE
`COMPUTING AND THE PRIOR ART SYSTEMS
`A. Background
` To understand the Patents-in-Suit, it is worthwhile to first understand the
`
`state of the art at the time of the inventions. In particular the Patents-in-Suit relate to
`
`high performance computing (“HPC”) and the various solutions to the technical
`
`problems associated in that field of endeavor to utilize reconfigurable systems.
`
` See for example, the various Patents-in-Suit’s specification disclosures that
`
`describe the HPC field of endeavor the inventors were directing their innovations to:
`
`’152 Patent (col. 1, lines 35-49); ’524 Patent (col. 1, line 21, line 28 – col. 2, line 12);
`
`’800 Patent (col. 1, lines 39-61); ’687 Patent (col. 1, line 20, col. 1, lines 52-63);
`
`Huppenthal Decl.2 at ¶¶11-79 (Inventor Jon Huppenthal discussing the evolution of
`
`adopting reconfigurable systems to HPC systems that his company SRC Computers
`
`undertook after its founders left Cray Computers).
`
` Much of the opinions and testimony I provide in this declaration is directed
`
`toward what a POSITA would have known or understood at the time of the relevant
`
`patent applications were filed (1997 or 2001, depending on the patent at issue). During
`
`
`2 IPR01601 EX2100; IPR1605 EX2101.
`
`
`
`
`10
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 13
`
`

`

`this time period (and also for many years and decades both before and after this time
`
`period), the capabilities and performance characteristics of various computing
`
`components (such as microprocessors, FPGAs, memory devices, etc.) were changing
`
`and improving very rapidly; and, the various types of components experienced
`
`performance improvements at different rates across the relevant times. Thus, to avoid
`
`hindsight bias, it is important to consider the performance characteristics of the devices
`
`at the particular time that is relevant to each patent at issue.
`
` In addition to performance improvements, the various components over time
`
`would be improved to include new feature sets and capabilities that previously were not
`
`possible or available. Also, manufacturers and standards setting organizations would
`
`update the relevant specifications and standards over time in ways that might make
`
`devices either more or less interoperable, make integration either easier or more
`
`difficult, etc.
`
` One of the ways that I ensured that my testimony was accurately grounded in
`
`the relevant time period was to refresh my own recollection regarding the capabilities
`
`and performance characteristics of the relevant components over time. I note that none
`
`of Microsoft’s experts (Dr. Stone, Dr. Trimberger, or Dr. Hauck) appear to have done
`
`this; and none of them contain information in their declarations that would allow the
`
`Board to do so. For example, none of Microsoft’s expert declarations permit the Board
`
`
`
`
`11
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 14
`
`

`

`to determine the available processing or clock speed of microprocessors or FPGAs at
`
`any particular point in time.
`
` I found the following graphs and information to be particularly helpful in
`
`ensuring that the testimony and opinions I provide herein are tied to the relevant time
`
`period:
`
` The following two charts illustrates “Moore’s Law” as it applied to
`
`performance of microprocessors over the decades (Hennessy 2019 [26]):
`
`
`
`
`
`
`12
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 15
`
`

`

` The following two charts provide a relative comparison of available
`
`bandwidth for microprocessors, memory, networks, and disks over time (Hennessy
`
`
`
`2019 [26]):
`
`
`
`
`13
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 16
`
`

`

`100,000
`
`10,0b0
`
`----------------------------------------------------------------------
`
`Mlcroprocessor
`
`1000 —..-——--——-----—--—~--—----——-———«-—-—-——-
`
`-------——— #——-—--—————-_.—-—
`
`----------------------------------------------
`
`
`
`
`
`RelativeBandwidthImprovement
`
`100
`
`10
`
`----------------------------------
`
`
`
`1975
`1980
`1985
`1990
`'1995
`2000
`2005
`2010
`Year
`
`
`
`' 2015
`
`2020
`
`
`Figure 1.23 Relative bandwidth for microprocessors, networks, memory, and disks over time, based on data in
`Figure 1.10.
`
`
`
`
`
`
`14
`14
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 17
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 17
`
`

`

` The following two charts provide a comparison between performance
`
`improvements between microprocessors and memory devices over time (Sterling 2018
`
`[24], Hennessy 2019 [26]):
`
`
`
`
`
`
`15
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 18
`
`

`

`3 100000
`61e4
`
`PI'OCQSSOF"MQMOW Gap
`
`10000
`
`1000
`
`100
`
`10
`
`1
`
`Beginning of multicore era
`
`
`
`Growing Processor«Mcrnory GAP
`
`Moore‘s law
`
`
`
`"""
`
`,
`
`,
`
`,..
`
`--¢m noes
`"*Memlandulah
`
`1990
`
`2000
`
`Time
`
`2010
`
`2020
`
`8
`5
`‘5
`E
`31>:
`9
`E
`TI
`2
`
`m E
`
`O
`'t
`a
`
`FIGURE 6.6
`
`Performance gains for processors increased by four orders of magnitude while main memory experienced an
`improvement of only two orders of magnitude during the same period of time.
`
`
`
`100,000
`
`10,000
`
`1000
`
`100
`
`Performance
`
`1980
`
`1985
`
`1990
`
`1995
`
`2000
`
`2005
`
`2010
`
`2015
`
`Year
`
`
`1‘
`
`'f
`
`lu‘smmFyii-J‘céfiinbaaiI-‘xIl-initj:-:-a:
`
`
`
`Figure 2.2 Starting with 1980 performance as a baseline, the gap In performance,
`measured as the difference in the time between processor memory requests (for
`a single processor or core) and the latency of a DRAM access, is plotted over time
`In mid-2017. AMD, Intel and Nvidia all announced chip sets using versions of HBM
`technology. Note that the vertical axis must be on a logarithmic scale to record the size
`ofthe processor-DRAM performance gap. The memory baseline is 64 KB DRAM in 1980,?
`with a 1 07 per year performance improvement in latency {see Figure2.4 on page 88).
`The processor line assumes a 1 25 improvement per year until 1986, a 1.52 improve-
`ment until 2000, a 1.20 improvement between 2000 and 2005, and only small I'mprOVe-
`- ments in processor performance (on a per-core basis) between 2005 and 2015. As you;
`can see, until 2010 memory access times in DRAM improved slowly but consisténtly;fl‘:
`since 2010 the improvement in access time has reduced, as compared with the earlier}.
`periods. although there have been continued improvements in bandwidth. Seef.
`Figure 1. i in Chapter 1 for more information.
`
`
`
`
`
`
`16
`16
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 19
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 19
`
`

`

` The following charts are useful for illustrating performance improvements
`
`for various characteristics of FPGAs over time and I note are from Dr. Trimberger’s
`
`own work not cited by Microsoft (Trimberger 2015 [27]):
`
`
`
`
`
`
`17
`
`
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 20
`
`

`

`
`
`TotalCost
`
`NRE
`
`
`
`
`
`Crossover
`
`point,
`
`FPGA
`generationn
`
`
`Crossover
`
`point,
`generation n+1
`
`Number of Units
`
`Fig. 2. FPGA versus ASIC Crossover Point. Graph shows total cost
`versus number of units. FPGA lines are darker and start at the lower
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`left comer. with the adoption of the next process node (arrows
`from the earlier node in dashed lines to later node in solid lines),
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`the crossover point, indicated by the vertical dotted line, grew larger.
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`FPGA Applica
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`
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`FPGA 1992 FPGA 1997
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`Fig. 8. Growth of the FPGA addressable market.
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`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2112, p. 21
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` In sum, understanding the Patents-in-Suit requires a POSITA to fully
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`appreciate the capabilities of the systems and state-of-art. Otherwise, as I note later in
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`this report, one could easily import hindsight bias by assuming the technical solution
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`and problem as one, which I believe Microsoft’s experts did in selecting their prior art
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`references and opinions thereto in “combining” them.
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` I now provide a deeper discussion of the various technologies disclosed in
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`the patents.
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`B. High Performance Computing (“HPC”) – Definition and Evaluation
`Metrics
` High performance computing (HPC) encompasses multiple facets of
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`computer architecture, VLSI technology, processing methodology and application
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`characteristics to achieve the greatest computing capability possible at any point in time
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`and technology. HPC can be seen as a pivotal mechanism of exploring the
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`complementing empirical and theoretical techniques to achieve the highest possible
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`performance.
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` In contrast to other areas of computing science, HPC is concerned about
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`achieving the performance at its peak capacity compared to other concerns such as
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`resources or other aspects such as area and power demanded by the system. HPC
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`engineers are highly concerned with the performance of processing, measured using
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`different metrics such as floating-point operations per second (flops – here ‘s’ refers to
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`seconds). For instance, Summit super computer at Oak Ridge National Laboratory
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`(“ORNL”) in USA topped the charts of supercomputers with 143.5 Petaflops on High
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`Performance Linpack (HPL) benchmarks, which is nearly three-fold higher in
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`magnitude compared to the peak performance achieved by supercomputers in 2013
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`(nearly 1000x improvement in the past five years).
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` Though the HPC is primarily concerned with measuring flops, there is no
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`single measure of performance that completely reflects the quality of performance.
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`Multiple perspectives and related metrics are routinely applied to characterize the
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`behavioral properties and capabilities of an HPC system. Two fundamental measures
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`are “time” and “number of operations” performed. As aforementioned, flops i.e.,
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`floating-point operations per second is a convenient metric considered to evaluate the
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`performance of the HPC that measures the number of operations performed. The HPC
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`supercomputers such as Summit, Tinahe-2A are few million times more powerful than
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`a laptop or a standard desktop system. In addition to flops, a better measure is to
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`determine the amount of time a problem takes to complete running a workload. For a
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`fair comparison, the HPC community has come up with a specific problem termed as
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`benchmarks around which the metrics are computed to standardize and perform a fair
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`comparison.
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` Some of the main distinguishing factors of an HPC system from conventional
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`computers are the organization of the component resources including processor cores,
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`GPUs, interconnectivity, physical and logical parallelism, memory hierarchy, and the
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`ability to support software to manage the operation of the system at that scale.
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`However, HPC is not always regarding optimizing flops or time to process a
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`benchmark, the HPC is also concerned with optimizing generic applications such as
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`weather prediction, hurricane modeling as well as Navier-Stokes equations and
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`Maxwell equations that has partial-differential equation solvers.
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` HPC cannot be always designed for performance maximization for standard
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`benchmarks or general purpose applications, but sometimes inspiring from HPC design
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`methodology, custom computing machines (CCMs) are introduced for special-purpose
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`computing of specific applications such as signal processing and database operations,
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`where general purpose desktops will not achieve required performance and general
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`purpose HPC systems might need more resources, though performance can be
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`achieved. Some of the CCMs are Axel [19], and CUBE [20]. Definition HPC 2018
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`[24]; Stone [31], [23], EX2070 (-1601); EX2069 (-1605).
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`C. System Architecture – It’s Impact on HPC
` As Seymour Cray rightly stated, “Anyone can build an extremely fast
`processor. The hard task is building an extremely fast computer system”. This is exactly
`what development of HPCs aim to perform. One of the most impactful factors that
`differentiates normal and high-performance computing systems is the underlying
`architecture and the way the subcomponents communicate and share resources and the
`way that applications are handled and processed. With the rise in number of
`components, the communication, splitting a task into multiple subtasks, achieving
`parallelism and addressing involved race conditions to achieve higher performance
`becomes highly complex.
` Thus, the main target or purpose of the HPC architect is to consider the
`interrelation of all the parts of the computer system (hardware and software) and
`optimize their performance by achieving an optimal balance of all relevant factors.
`Some of the differentiating aspects of HPC systems compared to the normal systems
`from an architectural perspective is the interconnectivity between different units of the
`system and the sale of the component resources (few cores in normal computing
`systems vs few tens of thousands processing cores in HPC systems and similarly scale
`of memory) rather than the components used. Such a massive architecture in HPC
`systems also facilitates massive parallelism (far more than traditional computing
`systems) in terms of physical and logical parallelism i.e., replication of physical
`resources such as processors and memory units.
` Through such massive and coordinated parallelism, the subsystems and
`components in an HPC coordinate to solve a shared problem. It needs to be noted that
`the additional functionality facilitated by system software and programming models are
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`developed to support such a