`
`Huppenthal
`
`Reference 3
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 1
`
`

`

`

`

`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 3
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 3
`
`

`

`Copyright
`
`Copyright © 1993 by Cray Computer Corporation. All Rights Reserved. This manual or parts
`thereof may not be reproduced in any fonn unless penniued by contract or by written
`pennission of Cray Computer Corporation.
`
`Copyright © 1986, 1987 by Cray Research, Inc. All Rights Reserved. This manual or parts
`thereof may not be reproduced in any fonn unless penniued by contract or by written
`pennission of Cray Research, Inc.
`
`Autotasking, CF77, CFT, CFr2, CFT77, CRAY-2, CRAY X-MP, CRAY Y-MP2E, and
`SEGLDR are trademarks and CRAY, CRAY-l, CRAY Y-MP, HSX, UNICOS, and X-MP EA
`are registered trademarks of Cray Research, Inc.
`
`bdb, CRAY-3, CRAY-4, CSOS, Doyle, Holmes, Hudson, stb, Watson, and Wigins are
`trademarks of Cray Computer Corporation.
`
`BSD is a registered trademark of the University of California, Berkeley.
`
`Ethernet is a registered trademark of the Xerox Corporation.
`
`Fluorinert is a registered trademark of 3M (Minnesota Mining and Manufacturing).
`
`HYPERchannel is a trademark, and NSC is a registered trademark of Network Systems
`Corporation.
`
`libtcl is authored by Professor John Osterhout, U.C. Berkeley and extended by Cray Computer
`Corporation.
`
`Macintosh is a registered trademark and Quadra is a trademark of Apple Computer, Inc.
`
`NeWS. NFS. OpenWindows. Sun, Sun Microsystems, Inc., SunView, and XView are
`trademarks and Sun Workstation and SunOS are registered trademarks of Sun Microsystems,
`Inc.
`
`3207 - CRAY-3 Hardware Description Manual
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 4
`
`

`

`Copyright
`
`System V is a trademark, and OPEN LOOK and UNIX are registered trademarks ofUSL
`(UNIX System Laboratories) in the United States and other countries.
`
`OSF and OSF/Motif are trademarks of Open Software Foundation.
`
`POSIX is a trademark of The Institute of Electrical and Electronics Engineers, Inc.
`
`SPARCstation and SPARCware are trademarks of SPARC International, Inc.
`
`UltraNet is a registered trademark of Ultra Network Technologies, Inc.
`
`VAST is a registered trademark of Pacific Sierra Research Corporation.
`
`X Window System is a trademark of the Massachusetts Institute of Technology.
`
`The CSOS operating system is derived from Cray Research, Incorporated's UNICOS
`operating system. The UNICOS operating system is derived from the USL's UNIX System V
`operating system. UNICOS is also based in part on the Fourth Berkeley Software Distribution
`under license from The Regents of the University of California
`
`II
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 5
`
`

`

`Reader Comments
`
`If you have any comment about the technical accuracy, content, or organization of this manual,
`please tell us. You can contact us in any of the following ways:
`
`Call our Technical Publications department at (719) 579-6464 from 8 a.m. to 5 p.m. (Mountain
`Time).
`
`Send us electronic mail from a CSOS or UNIX system to pubS@craycos.com
`
`Write to us at the following address:
`
`Cray computer Corp.
`Technical Publications Department
`P.O. Box 17500
`Colorado Springs, CO 80935
`
`We value your comments and will respond to them promptly.
`
`3207 -eRA V-3 Hardware Description Manual
`
`Iii
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 6
`
`

`

`Reader Comments
`
`Iv
`
`Cray Computer Corporation
`
`July 14, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 7
`
`

`

`Table o/Contents
`
`Copyright ......................................... i
`Reader Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
`Table of Contents ................................... v
`
`Introduction ....................................... ix
`
`Chapter 1
`
`CRAY-3 Overview
`
`1
`
`Packaging Overview ................................. 1
`The Octants ................................... 4
`The Modules .................................. 7
`The Printed Circuit Boards ....................... 11
`The Logic, Power and Resistor Plates .............. 12
`The Integrated Circuits ......................... 13
`
`Design Overview .................................. 15
`Performance Specifications ...................... 15
`Common Memory ............................. 17
`Background Processing ......................... 19
`Foreground Processing ......................... 23
`
`CRAY-3 Product Description .......................... 26
`
`1.1
`
`1.1.1
`1.1.2
`1.1.3
`1.1.4
`1.1.5
`
`1.2
`
`1.2.1
`1.2.2
`1.2.3
`1.2.4
`
`1.3
`
`3207 - CRAY-3 Hardware Description Manual
`
`v
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 8
`
`

`

`Table of Contents
`
`Chapter 2
`
`Circuit Component Design
`
`29
`
`GaAs Component Design ............................ 29
`
`Transistor Design .................................. 31
`
`Current Source Design .............................. 35
`
`Diode Design ..................................... 36
`
`Capacitor Design .................................. 40
`
`Resistor Design ................................... 46
`
`Logic Package Design .............................. 48
`o Cell Design ................................. 52
`E Cell Design ................................. 54
`F Cell Design ................................. 56
`FF and FG Cell Design ......................... 58
`FJ and FK Cell Design .......................... 59
`
`Clock Amplifier Design .............................. 60
`
`Other Circuits ..................................... 64
`
`The Vector Register Package ......................... 67
`
`The Silicon Memory Packages ........................ 70
`
`The CRAY-3 Cell Library. . ........................... 74
`
`Chapter 3
`
`Integrated Circuit Artwork
`
`79
`
`The IC Assembly .................................. 79
`
`Routing an IC ..................................... 88
`
`Verification of the IC Artwork ......................... 98
`
`Chapter 4
`
`Integrated Circuit Mask Production
`
`101
`
`The Glass Plates or Masks ......................... 101
`
`Mask Data ...................................... 102
`
`Fracturing ....................................... 104
`
`Mask Layers ..................................... 1 09
`
`Positioning of ICs from Mask to Wafer. . ............... 110
`
`2.1
`
`2.2
`
`2.3
`
`2.4
`
`2.5
`
`2.6
`
`2.7
`
`2.7.1
`2.7.2
`2.7.3
`2.7.4
`2.7.5
`
`2.8
`
`2.9
`
`2.10
`
`2.11
`
`2.12
`
`3.1
`
`3.2
`
`3.3
`
`4.1
`
`4.2
`
`4.3
`
`4.4
`
`4.5
`
`vi
`
`Cray Computer Corporation
`
`August 1, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 9
`
`

`

`Chapter 5
`
`Integrated Circuit Fabrication
`
`113
`
`Table of Contents
`
`Integrated Circuit Fabrication ........................ 113
`Canon Wafer Stepper ......................... 116
`GaAs Fab Processing Steps .................... 118
`
`Wafer Processing ................................. 124
`FAST Testing ................................ 124
`Grinding .................................... 125
`Dicing ...................................... 126
`Pick and Place ............................... 127
`Die Bonding ................................. 128
`
`Chapter 6
`
`Module Structure
`
`133
`
`Overview ........................................ 133
`
`Printed Circuit Board Manufacturing ................... 139
`
`The 25 mm Circuit Boards .......................... 141
`
`Logic Plates ..................................... 150
`
`Resistor Plates .................................... 154
`
`Power Plates .................................... 158
`
`Memory Board Bypass Capacitors. . .................. 160
`
`Power Blades .................................... 162
`
`Logic Connectors ................................. 167
`
`Chapter 7
`
`Module Assembly, Testing and Repair
`
`171
`
`Final Assembly of the Module ........................ 171
`Kitting ...................................... 173
`Board Soldering .............................. 174
`Die Attach .................................. 177
`Twist Pin Manufacturing ........................ 180
`Stacking the Module Assembly .................. 183
`Pinning the Module Assembly ................... 186
`
`Module Testing ................................... 190
`Pulse-Power Testing .......................... 190
`Full-Power Testing ............................ 196
`
`Module Repair ................................... 202
`
`5.1
`
`5.1.1
`5.1.2
`
`5.2
`
`5.2.1
`5.2.2
`5.2.3
`5.2.4
`5.2.5
`
`6.1
`
`6.2
`
`6.3
`
`6.4
`
`6.5
`
`6.6
`
`6.7
`
`6.8
`
`6.9
`
`7.1
`
`7.1.1
`7.1.2
`7.1.3
`7.1.4
`7.1.5
`7.1.6
`
`7.2
`
`7.2.1
`7.2.2
`
`7.3
`
`3207 - CRAY-3 Hardware Description Manual
`
`vII
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 10
`
`

`

`Table of Contents
`
`Failure Analysis .................................. 203
`
`7.4
`
`Chapter 8
`
`Cabinet Design
`
`207
`
`System Cabinet .................................. 207
`
`OctantAssembly ................................. 218
`
`Power Supplies .................................. 222
`
`Wire Harnesses .................................. 228
`
`Cooling ......................................... 231
`
`Translator Cards .................................. 235
`
`System Control Pod ............................... 237
`Front Panel User Controls ...................... 241
`Maintenance Panel ........................... 244
`Electronic Module ............................ 245
`Motor Starters ............................... 247
`Clock Source ................................ 247
`AC Box .................................... 247
`DC Bulkhead ................................ 248
`
`Peripheral Equipment .............................. 251
`00-49 Disk Unit. ............................. 251
`OS-40 Disk Subsystem ........................ 251
`CRAY-3 Circuits for the 00-49 and DS-40 ......... 252
`RAID Disk Array Subsystem .................... 257
`CRAY-3 HIPPI Circuitry ........................ 258
`
`8.1
`
`8.2
`
`8.3
`
`8.4
`
`8.5
`
`8.6
`
`8.7
`8.7.1
`8.7.2
`8.7.3
`8.7.4
`8.7.5
`8.7.6
`8.7.7
`
`8.8
`
`8.8.1
`8.8.2
`8.8.3
`8.8.4
`8.8.5
`
`Appendix A
`
`Integrated Circuit Packages Used in the CRAY-3 259
`
`Appendix B
`
`CRAY-3 Board Stack Assignments
`
`279
`
`List of Figures ••.•••.•••..•••.•••.•••••••••. 293
`Index .•.•.•.....•.............•...•.••..... 299
`
`vIII
`
`Cray Computer Corporation
`
`August 1, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 11
`
`

`

`Introduction
`
`This is the fifth revision of this manual. The previous version was dated
`January 15, 1991. All sections have been revised and many new sections added
`to reflect changes which have occurred over the last twenty-nine months in the
`design, manufacturing and testing of the CRA Y-3 supercomputer system. This
`current version of the manual has over 300 pages, more than 160 illustrations
`and 22 tables, whereas the previous version had just over 100 pages and 45
`illustrations.
`
`Much effort has been expended to make this latest edition of the manual
`accurate and up-to-date. However, this is really an impossible task since
`procedures and design are in an almost continuous state of flux. At some point
`a decision must be made to "go to press" knowing that by the time the manual
`reaches most readers certain items of fact will have already changed.
`
`Purpose
`
`The CRAY-3 Hardware Description Manual is intended to provide the person
`who is working on the project with a general reference manual to the
`component hardware that comprises a CRAY-3 computer system. It is ideal for
`introducing a new employee to the overall project.
`
`3207 -CRAY-3 Hardware Description Manual
`
`Ix
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 12
`
`

`

`Introduction
`
`The manual will also find interested readers among current and future
`customers, since it provides a unique summary of information on the CRAY-3
`that is not available in any other form.
`
`Organization
`
`The manual first presents an overview of the CRAY-3 computer system
`looking at both the overall architecture of the machine and the implementation
`of that design in the hardware and packaging. This is done in Chapter 1. The
`overview of the packaging begins at the highest level (the System Cabinet) and
`works down to the lowest level (the integrated circuit die). This helps the
`reader become familiar with how all the parts fit together in the complete
`machine. The overview of the packaging is presented before the overview of
`the design to introduce some of the terminology which is employed in
`discussing the design.
`
`In the remaining chapters each major component is discussed in much greater
`detail. In these chapters the presentation order is just the opposite of that in the
`introduction. The chapters proceed from the lowest level (the design of the
`integrated circuit components) to the highest level (the system cabinets and
`peripheral equipment).
`
`The manual has tried to reach a balance between being overly technical and
`obtuse, and simplistic and obvious. This has not been an easy task given the
`inherently technical subject matter and the broad spectrum of potential readers.
`
`Hopefully, employees of Cray Computer Corporation, whatever their position,
`will find the CRA Y-3 Hardware Description Manual interesting and
`informative, for they are viewed as the primary readers.
`
`x
`
`Cray Computer Corporation
`
`July 16. 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 13
`
`

`

`

`

`

`

`

`

`boards. A pulse is then formed from the square wave by the clock amplifiers in
`each integrated circuit package to gate data and control into the latches within
`the IC packages. This strobe pulse occurs simultaneously throughout the
`machine with a period of two nanoseconds. This time is referred to as the
`"machine clock period".
`
`Another pulse is also formed from the inverted clock signal by identical clock
`amplifiers and is used to gate information into the latches one-half clock period
`later than the normal clock signal. This half clock period of time (one
`nanosecond) is referred to as a "clock phase time". The normal clock signal
`latches information in the even clock phases. The invert clock signal latches
`information in the odd clock phases. This dual phase system clock allows
`information to be latched into successive logic cells every nanosecond.
`
`The System Cabinet is covered by a cosmetic shell or skin which gives the
`CRAY-3 the appearance of being of one piece. However, the System Cabinet is
`really modular in design and consists of groups of octants. Each octant
`contains a one- or two-processor piece of a complete 16-processor machine,
`including the memory modules, I/O module or modules and power supplies
`associated with the modules for that octant. Each module is in turn made up of
`various types of printed circuit boards; namely, the power plates, the resistor
`plate, the logic plates, and the smaller printed circuit boards which hold the IC
`packages for both logic and memory circuits.
`
`1.1.1 The Octants
`
`The 336 modules for a 16-processor machine are arranged in the System
`Cabinet in eight columns which form a closed octagon. Each column or octant
`contains 42 modules in two ranks, arranged in an outer rank of 32 and an inner
`rank of 10. This arrangement of modules is illustrated in Figure 3. Fluorinert,
`an inert electronic liquid, circulates in the cabinet frame and flows through the
`modules for cooling. The temperature, liquid velocity and turbulence through
`the modules are all controlled by various sensors and monitoring devices. The
`octagon of module columns is located on top of a similar structure containing
`power supplies for the system. The power supplies are also cooled by the
`circulating liquid. Total power consumption for the system is approximately
`360 kilowatts or approximately 45 kilowatts per octant.
`
`The CRAY-3 computer system can be configured in one-, two-, four-, eight-, or
`16-processor versions. Since each one- or two-processor segment of the
`machine resides in one of the octants, a one- or two-processor machine would
`consist of one octant, a four-processor machine would consist of two octants,
`an eight-processor machine would be made up of four octants, and a
`16-processor machine would have a full complement of eight octants utilizing
`the full octagon for its modules and power supplies.
`
`4
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 17
`
`

`

`

`

`

`

`

`

`

`

`

`

`power and logic plates to the die. The logic signal trace lines on each printed
`circuit board are only 0.048 mm wide (a human hair averages 0.070 mm in
`diameter). The digital data for the 25 mm circuit boards is routed, drawn, and
`tested in the Artwork Department at Cray Computer Corporation. The circuit
`boards are manufactured at Cray Computer Corporation's own facility in
`Colorado Springs.
`
`1.1.4 The Logic, Power and Resistor Plates
`
`The Logic Plate is simply a larger size circuit board (107 mm by 104 mm and
`0.46 mm thick). The reason for this difference in size should be apparent if you
`think of the logic plate's primary function-to distribute logic signals to and
`from the smaller 25 mm circuit boards which fit side-by-side making a square
`four circuit boards by four circuit boards, or sixteen in each layer of circuit
`boards. So the logic plate needs to cover the area of four 25 mm circuit boards
`if it is going to distribute signals to all those smaller boards. The logic plate
`contains eight layers, as do the 25 mm circuit boards, but whereas only two
`layers are used for drawing logic trace lines on the circuit boards, six layers are
`used for drawing logic trace lines on the logic plates.
`
`When people refer to "the logic plate" they are often using that expression to
`describe more than a single logic plate since the logic plates are always used in
`pairs, drawn together, and considered a single, functional unit even though
`they are physically two separate plates. Furthermore, in addition to the two
`logic plates, the two power plates and the single resistor plate are also
`generally considered to be part of the logic plate's working assembly.
`Therefore, in our discussions, the power plates and resistor plate will be
`included in the section on the logic plates.
`
`The power plates contain no logic signal traces. The power plate serves to
`deliver the necessary voltages from the power blades to all of the power pins at
`the corners of each 25 mm circuit board. From there the power layers of each
`circuit board deliver the appropriate voltages to the proper pins of each IC. The
`power plate is longer than the logic plates in one dimension to provide space
`for the power blades to contact· the outside surface of each power plate.
`
`The resistor plate is sandwiched between the two power plates and contains the
`55 ohm terminating resistors used to match the impedance of the signal
`transmission lines used throughout the logic circuits of the computer. The
`resistors are connected to the appropriate signal trace line through twist pin
`jumpers which carry the signal vertically through the module layers. As noted
`earlier, experiments are under way which change the positioning of the resistor
`plate in the module sandwich or which replace the resistor plate with
`individual resistor boards, also changing the position of the resistors relative to
`
`12
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 23
`
`

`

`other layers of the module sandwich. The outcome of these experiments will be
`reflected in later revisions of this manual.
`
`1.1.5 The Integrated Circuits
`
`The smallest electronic parts used in the CRAY-3 are the integrated circuit
`packages or ICs. Sometimes people will refer to them as "chips" or generally
`after they have been manufactured and without being packaged in tiny
`containers, as "die." The physical size of the gallium arsenide die as they
`appear on the printed circuit boards is 3.835 x 3.835 millimeters. There are 498
`different GaAs integrated circuit packages used in the logical networks of the
`machine. Each of these circuits consists of an array of up to 128 basic logic
`cells. There are 36 different logic cells from which all the circuits are built. The
`maximum equivalent gate capacity of the circuit packages is approximately
`500. The logic circuit packages have 52 bonding pads for connection to the
`printed circuit boards.
`
`The ICs are the active circuits that actually perform the logical functions which
`enable the computer to perform its calculations. It should not be surprising .then
`that there are a lot oflCs in a CRAY-3 computer system. The 16-processor
`machine contains over 266,000 ICs of which 147,456 are used for SO
`Common Memory. A two-processor machine has over 29,000 integrated
`circuit packages. Since there are only 498 unique types of ICs, many are used
`again and again throughout the machine to perform the necessary logical
`functions required. For example, the Vector Register integrated circuit package
`is used over 3,000 times in a 16-processor CRAY-3.
`
`Nearly all other parts of the CRAY-3 are there simply to serve these tiny
`devices-to give them a safe place in which to reside, to keep them cool, to
`give them the right kind of power and to provide communication lines so they
`can talk to each other and communicate with the outside world.
`
`The diagram in Figure 10 illustrates how the basic components of the CRAY-3,
`from the ICs to the Modules, fit together to make up a complete machine.
`
`3207 - CRAY-3 Hardware Description Manual
`
`13
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 24
`
`

`

`

`

`1.2 Design Overview
`- - - - - - -
`
`The CRAY-3 computer system represents a major enhancement over the
`CRAY-2 computer system, providing an order of magnitude performance
`improvement at a comparable cost. This performance gain is achieved through
`the use of three new design features 1) the use of gallium arsenide logic
`circuits in place of the silicon circuits previously used, 2) the use of innovative
`packaging and cooling technologies and 3) the implementation of a number of
`architectural changes, including more processors and enhanced memory
`access.
`
`1.2.1 Performance Specifications
`
`Each processor in the CRA Y-3 system is slightly more than two times as fast as
`its CRA Y-2 counterpart. With a four-fold increase in the number of total
`processors, this leads to an overall improvement range better than eight times
`that of a CRAY-2.
`
`The CRAY-3 system is functionally equivalent to the CRAY-2 system. Logic
`enhancements to the system have enabled performance to be increased while
`providing an extension of the original CRAY-2 instruction set. The following
`table lists the major differences between the CRAY-2 and CRAY-3 systems:
`
`3207 - CRAY-3 Hardware Description Manual
`
`15
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 26
`
`

`

`

`

`

`

`gigabytes. Each Background Processor can read and write a word of data per
`clock period (two nanoseconds) in a vector mode.
`
`The silicon Static Random Access Memory integrated circuits used in
`Common Memory each contain either 262,144 or 4,194,304 bits of data (with
`enhanced memory). A memory bank consists of 288 of the 256K-by-l SRAM
`integrated circuits or 72 of the 4M-by-l SRAM integrated circuits. A memory
`module then contains 576 x 256K or 72 x 4M bits of data plus logic circuits to
`support the memory access paths. Memory access time at the circuit level is 22
`nanoseconds. Memory cycle time is 30 nanoseconds.
`
`The memory enhancement for the CRAY-3, under development as this revision
`was published, would increase the Common Memory of the machine four
`times per octant of memory. With the 4 meg SRAM circuit enhancement a
`four-processor CRAY-3 (two octants) would contain 512 million words of
`Static Random Access Memory. A 16-processor machine would contain two
`gigawords of Common Memory.
`
`The CRAY-3 GaAs integrated circuits are significantly faster than the memory
`circuits. This speed discrepancy is used to minimize the number of physical
`data paths that are necessary to connect the 512 memory bank modules to the
`32 memory ports. Data is transferred by utilizing an 18-bit packet. The 64-bit
`data word and eight error correction bits require a four clock period
`transmission time-18 bits per clock period. There are independent read and
`write packets between the memory bank and access port. Memory bank
`address utilizes a 12 bit packet. The 24 bit internal bank address requires a two
`clock period transmission time between the access port and memory bank-12
`bits per clock period.
`
`An eight bit error correction code is generated at the memory access port as the
`write data is transmitted to the memory bank. This code is interpreted at a
`readout port for Single Error Correction and Double Error Detection, often
`abbreviated as SECDED. This allows the computer to continue to properly
`transfer data to and from common memory even if several single bit errors
`occur in the data during the transfer or storage process. Double bit errors are
`also detected but cannot be corrected.
`
`18
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 29
`
`

`

`

`

`FIGURE 12. Block Diagram of a Background Processor.
`
`Vector Registers Vector
`Control
`ff=;; I
`
`Vector
`Mask
`
`Logical
`Integer
`
`4
`
`CPU 0
`Secondary
`
`Port
`
`I
`j +
`Memory ~ Shift
`1
`Pop, Parity
`Leading Zero
`~VO-V7¥
`
`f-
`
`Vector
`Functional Units
`
`-1
`
`CPU 0
`Primary Common
`Memory Port
`
`' - - - -
`
`CPUs 0,4,8,12 I
`
`1/0 Channel Loop
`
`RealTime
`Clock
`Scalar Registers
`
`LLY L
`
`~
`
`SO-S7
`
`Common
`Memory
`
`Local
`Memory
`16K
`64-bit words
`
`Address Registers
`
`~
`rred~,~
`Square Root
`Lookup Table
`I Multiply
`~ Add
`
`'--
`
`Floating
`Point
`Functional Units -
`
`I
`Integer
`I Logical
`Shift
`Pop, Parity
`Leading Zero
`-
`Scalar
`Functional Units L
`
`Instruction Buffers
`7
`
`V~or
`Length
`
`Functional Units f-
`
`+1,-1,~
`
`~ I Multiply
`Add r Add~
`~ 6
`4 5
`Vector
`2 3
`Control
`~ 0
`1 ~-
`I Instruction
`~ Issue
`1 Queue
`
`t
`
`Issue
`
`P
`
`Error
`BG
`Status Base Limit
`Status
`Register Register
`
`1=
`
`CPU 0 Typical
`·-BackgrOuncrprocissor CPUS-O;-4);-12 ~
`~ Background Processor CPUs 1, 5, 9, 13
`J
`+1
`-----I Background Processor CPUs 2, 6, 10, ~
`~ Background Processor CPUs 3, 7,11,15
`~ §~u _o:.~5_S~~;~h~e_F~gi ~~6:
`~ Foreground Processor
`
`I 1/0 Interfaces
`
`External Devices
`
`Each background processor has a small high speed local memory to hold scalar
`or vector operands during a computation (16,384 words are available for each
`Background Processor). Data is moved from the Common Memory to the local
`memory and returned at the end of each computation. Arrays of data are
`addressed by the Background Processors directly in the Common Memory.
`The access to data common to multiple Background Processors is interlocked
`by the Background Processor semaphore flags.
`
`20
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 31
`
`

`

`

`

`Figure 13 shows how the different functions of each Background Processor are
`distributed among the four modules which comprise each Background
`Processor.
`
`FIGURE 13. Background Processor Functional Divisions Among the Modules.
`
`ONE BACKGROUND PROCESSOR
`
`A Module
`
`B Module
`
`CModule
`
`D Module
`
`Scalar Registers
`Bits 00-15
`
`Scalar Registers
`Bits 16-31
`
`Scalar Registers
`Bits 32-47
`
`Scalar Registers
`Bits 48-63
`
`Vector Registers
`Bits 00-15
`
`Vector Registers
`Bits 16-31
`
`Vector Registers
`Bits 32-47
`
`Vector Registers
`Bits 48-63
`
`Local Memory
`Bits 00-15
`
`Local Memory
`Bits 16-31
`
`Local Memory
`Bits 32-47
`
`Local Memory
`Bits 48-63
`
`Integer Add,
`Logical,
`Mask, RTC
`Bits 00-15
`
`Integer Add,
`Logical,
`. Mask, RTC
`Bits 16-31
`
`Integer Add,
`Logical,
`Mask, RTC
`Bits 32-47
`
`Address Registers
`
`Branch Control
`
`Floating Multiply
`
`Reciprocal
`Approximation
`
`Address Multiply
`
`Program Register
`
`Address Add
`Scalar Shift
`
`Vector Length
`Register
`
`Floating Add
`
`Common Memory
`Address
`
`Common Memory
`Write
`
`Integer Add,
`Logical,
`Mask, RTC
`Bits 48-63
`
`Instruction Issue
`Control
`
`Instruction Buffers
`
`Foreground
`Interface
`
`Vector Shift
`
`Common Memory
`Read
`
`22
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 33
`
`

`

`1.2.4 Foreground Processing
`The Foreground Processor supervises overall system activity and responds to
`requests for interaction between the system members. System communication
`is accomplished through foUf, high-speed synchronous data channels. These
`channels interconnect the Background Processors, Foreground Processor, disk
`control units and host system interfaces. The Foreground Processor does not
`execute the system program code.
`
`The Foreground Processor code is loaded at deadstart from a file on the
`maintenance console. This memory then becomes a read only memory. It
`cannot be altered during the operation of the system. Data for supervision of
`the system is maintained in the Common Memory and is moved to the
`Foreground Processor's local data memory as required.
`
`FIGURE 14. Data Channels (One of Four).
`
`HIPPI
`Interface
`Node
`
`F cf P I
`un
`Ion use
`
`Response Pulse
`
`Call Pulse
`
`Data Pulse
`
`Data
`
`I
`Foreground
`Processor
`
`r-
`
`r---
`r---
`
`-
`Speed -
`-
`- Channel - Controller
`Node -
`------
`
`Low
`
`External
`
`Interface
`
`Low
`Speed
`Disk
`
`Interface
`Node
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`-
`
`Background
`
`Background
`
`Background
`
`i---
`
`Background
`
`I--
`
`L
`-
`-
`Processor 0 - Processor 1 - Processor 2 i--- Processor 3 I - -
`Common - Common :-- Common I--- Common
`Interface - Interface - Interface I-- Interface
`-
`
`and
`
`Memory
`
`Node
`
`and
`
`and
`
`and
`
`Memory
`
`Memory
`
`Memory
`
`Node
`
`Node
`~ I--
`
`Node
`
`The primary function of the Foreground Processor program is to poll the four
`communication channel loops for requests from the Background Processors
`and control the communications on the four channel loops to facilitate data
`transfers between controllers on the channels. Many of the requests that will be
`recognized by the Foreground Processor require responses within a
`microsecond or less.
`
`Since the majority of Foreground Processor activity involves data transfer
`between the disk file storage units and the common semiconductor memory,
`the system provides for a mixture of 12 megabytes per second disk file storage
`
`3207 - CRAY-3 Hardware Description Manual
`
`23
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 34
`
`

`

`unit interfaces and 100 megabytes per second interfaces to main storage
`sub-systems such as disk arrays.
`
`FIGURE 15. Block Diagram of the Foreground Processor.
`
`.~ logical
`L
`"I Shift
`f-J
`Add
`~
`
`Console
`Register
`(32 bits)
`
`To
`Address
`Register
`
`i
`
`C
`Register
`
`B
`
`.r-J Register 7
`rL R';'mr V
`
`Arithmetic Registers
`
`local
`Memory
`(16384
`bytes)
`
`I
`RealTime
`Clock
`(32 bits)
`
`Channel Control
`and Response
`Registers
`(4)
`
`Instruction
`Translation
`
`
`Communica tion
`Loop
`(See Figure 1 4).
`
`Instruction
`Memory
`(65536 bytes)
`
`Console
`
`/
`
`/
`
`/
`
`Instruction
`Data
`/
`
`/
`
`7
`
`/
`
`/
`
`/
`
`BankO
`
`I
`
`16 0
`0l
`~ }'
`~ 7
`J1 ;//
`
`/
`7
`
`/
`
`/
`
`1 Byte
`
`Instruction
`Readout
`Register
`
`Branch
`to
`Immediate Address
`
`1+1
`
`Branch
`toB
`Register
`
`/
`
`I
`
`Bank
`
`Pointer r7-
`
`Address LJ
`
`~
`Register
`
`The Foreground Processor is divided into seven operational sections: 1)
`deadstart circuits, 2) instruction issue mechanism, 3) local data memory, 4)
`channel communication, 5) functional units, 6) console communications and
`
`24
`
`Cray Computer Corporation
`
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 35
`
`

`

`

`

`

`

`

`

`
`
`
`
`
`
`28
`28
`
`Cray Computer Corporation
`Cray Computer Corporation
`
`July 27, 1993
`July 27, 1993
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 39
`
`PATENT OWNER DIRECTSTREAM, LLC
`EX. 2104, p. 39
`
`

`

`

`

`

`

`

`

`

`

`

`

`The electrical characteristics of a transistor are shown in the graph in Figure
`21. The horizontal coordinate is the drain voltage with respect to the source
`voltage. The vertical coordinate is the amount of current that flows in the drain
`as a function of drain voltage and gate voltage.
`
`FIGURE 21. Electrical Characteristics of a Transistor.
`
`200
`-'-' _ .. --.. - .. --.. - '-"--'
`I'--+---t----+--I'--+---t----+--+----+--.. __ =. :I:;::rn_ •• -f""&'==" =i
`190
`180
`
`~/ ---_.
`
`/
`/
`
`I
`I
`I
`
`/
`
`I
`
`, • • _ . . . . . . . .
`
`I
`/
`I
`/
`I
`" I
`/
`II
`1/
`IV
`1/
`................. 11 . . . . . . . . . . . . . . . . . . . . . . . . . . III . . . . •
`I' •• , .L&,..:;.j--+----+----+-----l--+---+----+--+------I
`!I
`'1~"~-_+-~~-+_-~-_+--~-+---t---4-~
`II
`
`170
`
`160
`
`~150
`3: 140
`c e 130
`
`.~
`~
`~ 120
`Q.
`! 110
`~ 100
`~ 90
`u
`:i
`.~ 80
`C
`~ 70
`:::l
`0
`60
`c
`'e!
`c
`
`50
`
`40
`
`30
`
`20
`
`10
`
`0
`
`~----~~~
`
`0.2
`
`0.4
`
`0.6
`
`0.8