`Trials@uspto.gov
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______
`
`
`
`MICROSOFT CORPORATION,
`Petitioner,
`
`v.
`
`FG SRC LLC,
`Patent Owner.
`___________
`
`IPR2018-01601 Patent 7,225,324 B2
`IPR2018-01605 Patent 7,620,800 B2
`___________
`
`RECORD OF ORAL HEARING
`Held: February 4, 2020
`____________
`
`
`
`
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
`
`
`APPEARANCES:
`
`
`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH MICALLEF, ESQUIRE
`Sidley Austin, LLP
`1501 K Street, N.W.
`Washington, D.C. 20005
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`ALFONSO G. CHAN, ESQUIRE
`SEAN HSU, ESQUIRE
`Shore Chan DePumpo, LLP
`Bank of America Plaza
`901 Main Street
`Suite 3300
`Dallas, TX 75202
`
`
`
`
`
`The above-entitled matter came on for hearing on Tuesday,
`February 4, 2020, commencing at 12:00 p.m., at the U.S. Patent and
`Trademark Office, 600 Dulany Street, Alexandria, Virginia, before Julie
`Souza, Notary Public.
`
`
`
`
`
`2
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
`
`
` P R O C E E D I N G S
` - - - - -
`JUDGE ARBES: Hello everyone. This is the third oral hearing
`
`
`in a series of cases. Today we're here for IPR2018-01601 and 1605
`involving Patents 7,225,324 and 7,620,800. Can counsel please state your
`names for the record?
`
`
`MR. MICALLEF: Good afternoon, Your Honors. Joe
`Micallef, Sidley Austin for Petitioner Microsoft and with me at counsel table
`is my partner, Scott Border.
`
`
`MR. CHAN: Good afternoon, Your Honors. My name is
`Alfonso Chan along with my co-counsel, Mr. Hsu, Mr. Vinnacota, Mr.
`Puckett, Mr. Rafilson. We are here for the Patent Owner. Thank you.
`
`
`JUDGE ARBES: Per the Trial Hearing Order, each party will
`have 90 minutes of time to present arguments in the first hearing today. We
`will follow the same order of presentation as yesterday. We want to remind
`you again before we begin, to ensure that the transcript is clear, please only
`speak at the podium and try to refer to your demonstratives by slide number.
`Any questions from the parties?
`
`
`MR. CHAN: Yes. Your Honor, there was one point I believe
`we discussed yesterday about the disclaimer claims in the first case that we
`discussed yesterday? My colleague here, Mr. Hsu, will address those.
`
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`JUDGE ARBES: Counsel, why don't we defer that until after
`the two hearings today.
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`MR. CHAN: Okay. That's fine.
`
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`JUDGE ARBES: Let's take care of these two cases first.
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`MR. CHAN: I didn't know when you wanted to handle
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`housekeeping matters.
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`JUDGE ARBES: Sure. Thank you very much. Okay, counsel
`for Petitioner, you may proceed.
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`MR. MICALLEF: Your Honor, may I hand up some slides?
`
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`JUDGE ARBES: Yes.
`
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`MR. MICALLEF: Your Honor, may I reserve 30 minutes of
`my time, please. Thank you. Good afternoon. Joe Micallef for Petitioner
`Microsoft. I have a number of slides I'd like to go through. Right now I
`have up on the board slide 2 and this just shows the various grounds that
`have been instituted in these multiple consolidated proceedings for the two
`patents, the 324 patent and the 800 patent and my slides I believe are going
`to be citing to the 324 patent for the most part, if not entirely since the 800 is
`a straight continuation.
`
`
`You can see from this slide that there are multiple grounds but
`they are all based on the same basic prior art reference, that is the 1996
`Splash2 book and there are anticipation grounds, there are single reference
`obviousness grounds and several combination grounds. As with the other
`proceedings I'd like to walk through just a brief overview of the patents and
`then a brief overview of the prior art and then maybe dive into the issues that
`appear to be disputed from the briefing.
`
`
`So, this is slide 5. The 324 patent issued from an application
`filed in 2002. The 800 patent is a straight continuation claiming priority
`back to that same application so the priority date for our purposes is 2002.
`The patents disclose a computer system that includes a what's called an
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`adapted processor chip here on slide 6, figure 2 from the patent, which is a
`reconfigurable device in which a number of functional units can be
`instantiated or configured in order to process data or various types of data.
`The original claims in the 324 patent had an extensive file history. They
`were rejected numerous times over various pieces of prior art. They were
`amended numerous times. In the end the claims of the two patents are very
`similar. The main difference is that the 324 patent is directed to a systolic
`array where the 800 patent is directed to data driven techniques.
`
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`JUDGE ARBES: Counsel, is there a difference between those
`two terms?
`MR. MICALLEF: It seems to be. I think the systolic array
`
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`would be a subset I think, at least how these terms have been construed in
`the prosecution history of data driven because I think the notion of the data
`drive calculation is within the definition of systolic that the Applicants
`placed on the public record during prosecution. That's the way I read it.
`
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`JUDGE ARBES: And you agree that, I'm sure we'll get into
`this, the directly issue with systolic, that does not apply to data driven?
`
`
`MR. MICALLEF: That's right. We didn't put it in in that
`interpretation. So this is slide 8. Splash2 as I mentioned is the principle
`reference. It's a book published in 1996 that discloses the famous Splash2
`computer system and a number of different algorithms that were used to
`program the Splash2 computer system by various different computer
`scientists over the years in various different fields. The system itself has a
`SPARCstation connected to an interface board to a number of what are
`called array boards. Here on this slide 8 one of the array boards is shown as
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`having 17 FPGAs, those are the boxes with the Xs in them which are
`connected to the neighbors and also through a cross bar switch in the middle
`to other FPGAs.
`
`
`Now as I said, the book describes a number of different
`algorithms and processing techniques that had been used as of that date on
`Splash2. Our petition is focused on chapter 8 of the book which is directed
`to searching genetic databases on Splash2. This particular application
`compared a target sequence of genetic information to a source sequence of
`genetic information in order to calculate the edit distance between the two
`sequences, that is essentially the number, sort of a measure of how different
`the sequences are or how similar if you will based on the number of changes
`and the types of changes one would have to make to the sequences to go
`from one to the other.
`
`
`Now, our petition's chapter 8 discloses two different systolic
`arrays that perform this edit distance calculation and our petition relied on
`both of them in the alternative. The first one was a unidirectional systolic
`array which I have here on slide 10. In this array, a number of processing
`elements were instantiated within the FPGAs of the Splash2 array board. A
`source target sequence was shifted to the processing elements and then – I'm
`sorry, a source sequence was shifted in and then a target sequence was
`shifted in and through the systolic array of processing elements and at each
`time step a comparison of that particular character in the sequence with the
`character of the source sequence stored in that particular processing element
`was made and then through that comparison and edit distance a sum
`essentially was calculated through the array and passed through the array.
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
`
`JUDGE ARBES: Counsel, I'd like to ask a question of both
`
`
`parties. I'll ask Patent Owner the same thing during their presentation.
`Obviously the description of the edit distance algorithm and how the Splash2
`performs everything is a bit complicated. Is anything in our description in
`the Decision on Institution regarding the unidirectional array, the trace of
`that and how that works, is anything factually incorrect or is our
`understanding correct in your view?
`
`
`MR. MICALLEF: I can't tell you that. I cannot pick in my
`head and bring up the complete perfect picture of what you wrote, but I can
`also say when I read the Institution Decision I do not recall identifying
`anything that I thought was wrong.
`
`
`JUDGE ARBES: In particular our understanding of the trace of
`figure 8.13, I'd like to know if our understanding of the figure is correct or if
`there are any factual errors you believe in that description?
`
`
`MR. MICALLEF: I mean I bet you I have a slide with 8.13 on
`it, Your Honor, and maybe I can pull it up. I'm going to have to pull it up,
`Your Honor.
`
`
`(Counsel confers.)
`
`
`MR. MICALLEF: Oh, I see. The two processing elements
`highlighted in red and blue and the various time steps, okay. Well, like I
`said I can't remember everything you wrote in the Institution Decision but I
`have gone over that in the petition and Dr. Stone's analysis of that in his
`declaration in preparation for this and what we wrote in the petition is
`accurate.
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`IPR2018-01605 (Patent 7,620,800 B2)
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`JUDGE ARBES: Okay. Is there any dispute, the drawing that
`
`
`you referred to that has the red and the blue, is there any dispute between the
`parties as to that's exactly how Splash2 operates with the two processing
`elements shown in the columns and that each one of the sets of rows
`represents a different time step. Do the parties dispute that?
`
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`MR. MICALLEF: Well that was our reading of time step on
`the claim language --
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`JUDGE ARBES: Yes.
`
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`MR. MICALLEF: -- of time step, or claim interpretation I
`should say on the reference. I don't believe they have raised a dispute on
`that issue, I do not believe they have.
`
`
`So that's saying we have two alternative bases here. One is on
`the unidirectional array, and I'm back on slide 10, which shows the array
`figure that depicts the connections for the processing elements for that
`particular array and the code executed in each prosecution element in that
`particular unidirectional array including as shown here a loop that is
`performed, a computational loop, in pseudocode that's performed in each of
`those processing elements. Now there's also a bidirectional array, this one's
`very similar to the unidirectional array except in this case the source
`sequence is shifted through the array of processing elements in one direction
`and the target sequence is shifted through in the other direction and that at
`each time stop again there is a comparison of the characters and edit distance
`calculated, and then they have distance calculations summed up to the array
`and again Splash2 discloses the bidirectional processing element in figure
`8.6, and I'm looking at slide 11 and the loop code, the computational loop
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`IPR2018-01605 (Patent 7,620,800 B2)
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`that occurs inside each of those processing elements in figure 8.7 is shown
`here on this slide.
`
`
`Now a number of the dependent claims require that the method
`of the independent claims be used to calculate or perform certain types of
`calculations and so we had a number of prior art combinations that we relied
`on, and I just have them up here on slide 12. The Gaudiot, RaPiD, Chunky
`SLD and Roccatano references, and I do not believe that there is any
`question at all that these are prior art, including Splash2.
`
`
`So I'll just jump into the patentability analysis here. The first
`one raised by the Patent Owner in their Patent Owner response is the
`interpretation of the claim phrase "past computed data seamlessly between
`said computational loops." This was addressed in the Institution Decision
`where the Board agreed with us that the broadest reasonable interpretation --
`I guess I should stop on that -- of these cases, the broadest reasonable
`interpretation does apply to these patents. They are not expired and this
`proceeding was filed before the relevant date when the rules changed.
`
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`So the Board found at institution that this phrase under BRI
`should mean to communicate computer data directly between functional
`units that are calculating computational loops. At that time the Board
`rejected the Patent Owner's proposal that it has to go over certain
`reconfigurable routing resources and most particularly I think the Board
`relied on this passage here on slide 14 that we are quoting from the
`prosecution history when that is specifically directed to the seamlessly
`passing data of the claim language and I just note what I highlighted there
`where the Board writes at page 24 of the Institution Decision,
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`"We find this language significant for purposes of interpreting
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`the seamlessly phrase as it refers to the limitation expressly in describing
`"applicant's invention.""
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`Patent Owner doesn't take that on at all and simply ignores that
`very clear intrinsic evidence directly related to this claim language. Now
`there was other support for the Board's institution interpretation including
`Dr. Stone's analysis in his original direct declaration where he opined that
`our interpretation was consistent with the certain figures in the patent
`specification and the description and of course the inventor, Mr. Huppenthal,
`is pictured here on slide 15 and is in the room today, offered his own
`testimony in this proceeding where he testified that by seamlessly I mean the
`result of one loop streamed from that loop's output to the input of the next
`loop without being placed in a circuit element, et cetera, et cetera. So an
`opinion, the use of the term by the inventor that is entirely consistent in
`support of our interpretation utterly inconsistent with theirs.
`
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`JUDGE ARBES: Counsel, Patent Owner has pointed to the
`disclosure there of the two patents where, in figure 2 for instance, the
`functional units at the edge that connect to memory, that's the boundaries
`and that the patent was concerned with communication of data across those
`boundaries and making it seamless. Isn't the seam that's being referred to in
`the word seamlessly, isn't that the boundary with the memory there? Isn't
`that what we're talking about?
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`MR. MICALLEF: No, and I don't think there's anything in this
`patent specification that they've written that limits that to a seam first of all,
`the seamlessly was an adverb. But no, I don't think it is and the seam is
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`because the claim language is, and I'll go back, is between the functional
`units. The claim language, I'm on slide 14, is pass computer data seamlessly
`between said computational loops and the computational loops in the claim
`are being carried out by the functional units of the claim, and if you look at -
`- I'll go back to slide 6 where I have figure 2 of the patent, the functional
`units are within that reconfigurable chip or that adaptive processor chip. So
`when it says that there's seamless passing of data between these
`computational loops that are in these functional units you can see that it must
`be seamless within, not just at the boundary, but within.
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`I also note that I don't think there is a direct connection between
`a functional unit at the edge of one of these chips and then a functional unit
`at the edge of a different chip. I'm not so sure that's disclosed at all so that
`would be totally inconsistent with what they're saying.
`
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`JUDGE ARBES: What about the argument that the functional
`units are connected to each other by the reconfigurable routing resources,
`and that's specified in the claims that seamlessly is over those resources as
`Patent Owner argues -- that that's consistent with the surrounding language
`of the claim?
`
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`MR. MICALLEF: But the resources can just be connections
`without memory in them so there's seamless non-memory, i.e., direct
`communication between them as is depicted right here in figure 2.
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`JUDGE ARBES: What is a seam then in your view? What
`would a seam be?
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`MR. MICALLEF: Well I think that passage from the
`specification makes clear that you're not going through memory and I think
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`the inventor's testimony says the same thing. You're passing it directly from
`one functional unit to the other without going through memory. Now there's
`been this issue about they've mistaken that and confused that with having
`memory within the functional unit and we can talk more about that, I'm sure
`we will. But that I think is very clear from what they said to the examiner,
`that what they mean by that language is there's no memory between
`functional units.
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`JUDGE ARBES: Is that the only example of a seam or could it
`mean something else?
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`MR. MICALLEF: I think that's the only one that's supported
`by the intrinsic record.
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`JUDGE ARBES: And you would not equate seam with
`boundary, for instance, as those terms are used?
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`MR. MICALLEF: Well it's used, again, it's seamlessly and so
`it's really without a seam is what it's talking about, right? So at a boundary,
`the chip for example would seem to me how could that be seamlessly, that
`would seem to be a seam.
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`JUDGE ARBES: Perhaps we could move on to the term
`directly.
`MR. MICALLEF: Okay.
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`JUDGE ARBES: Is that, given the testimony that's been cited,
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`is that too ambiguous? Do we need to further define that term?
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`MR. MICALLEF: No, I don't think you need to further define
`that at all. I think direct is an ordinary English word and it's got the glossary
`of no memory based on the prosecution history supported by the
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`specification and the testimony of both the inventor and an expert. I don't
`think there's anything tricky about direct here. It's just there's not a memory
`in between.
`JUDGE ARBES: Correct me if I'm wrong, but I don't believe
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`the term directly was pulled from the prosecution history; is that right?
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`MR. MICALLEF: Well I have the prosecution history and it
`says, and I'm looking at slide 14 here and this is from the prosecution history
`Exhibit 1002, page 226. In the Applicant's invention systolic
`implementation will connect computational loops such that data from one
`compute loop will be passed as input data to a concurrently executing
`compute loop. In the Applicant's invention data computed by computation
`units or groups of functional units flows seamlessly and concurrently with
`data being computed by other groups and I think, so I guess we interpreted
`that to be a direct because data is being passed from one to the other and that
`was the notion that was described in here and that is the architecture that is
`described and depicted I should say, and that's figure 2 where each
`functional unit is connected directly to its neighbors without any indication
`of intervening memory or some kind of processing circuitry.
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`JUDGE ARBES: This is one of the issues with looking at these
`portions of the prosecution history. It appears that it’s talking about
`different things at different times, whether it's the systolic nature of it or
`seamlessly, it's not entirely clear though that that is a definition per se of the
`seamlessly limitation and it doesn't use the word directly.
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`MR. MICALLEF: Well the prosecution history can be used
`more than a definition. It informs the understanding of the phrase and the
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`claim phrase is seamlessly so without a seam. There are obviously multiple,
`as I go back again to figure 2, there are multiple functional units not only in
`the example of figure 2 but called out in the claim so that can't be what it
`means. There must be a border between the functional units, otherwise you
`wouldn't have multiple functional units. But it seems that the passing of data
`from one to the other is clearly what they're talking about in the specification
`and the file history and that's what Mr. Huppenthal was talking about.
`
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`JUDGE ARBES: One more question before you move on to
`that. Patent Owner's proposed interpretation of communicating the
`computed data over the reconfigurable routing resources. Is that not without
`a seam, when I'm communicating data over the reconfigurable routing
`resources not over something else -- and that's without a seam?
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`MR. MICALLEF: It could be I suppose but it wouldn't
`necessarily be because what's a reconfigurable routing resource? So within
`an FPGA, for example, you can have memory, we talked about that
`yesterday or you can have direct connections without memory. So I don't
`think that really answers your question and what's more important is when
`you bring to bear the tools of claim interpretation there's no association with
`this claim language to the verbiage that they're asking you for. But there's
`no place in the intrinsic record which indicates that what they mean is just
`over the reconfigurable routing resources where there is an indication, which
`this panel pointed out in the Institution Decision, that links this sort of direct
`passing of data to the seamlessly claim language and so --
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`JUDGE ARBES: But it doesn't use the term.
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`MR. MICALLEF: But it doesn't use the term, but certainly
`
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`informs it as does the inventor's testimony and Dr. Stone's testimony.
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`JUDGE ARBES: You responded to Patent Owner's argument
`that it kind of depends on where you arbitrarily draw the line where the
`memory is and there did seem to be a bit of confusion in the testimony of Dr.
`Stone.
`MR. MICALLEF: No, I don't think there was any confusion at
`
`
`all. Let's review the thing here. We proposed an interpretation of functional
`-- well, first of all let's go back a little bit before that to 2002. The Patent
`Owner chose to use the phrase functional unit. They used it and they could
`have used a more specific term and they could have defined it in a particular
`way in the claim or in the specification but they didn't. They used functional
`unit. We proposed a relatively specific and not amorphous interpretation of
`that phrase in our petition and then we read that claim phrase on the prior art
`in our petition.
`
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`In their Patent Owner response they did not argue that there was
`anything wrong with that interpretation –
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`JUDGE ARBES: The functional unit?
`
`
`MR. MICALLEF: -- the functional unit and they did not
`contest that we were pointing to in Splash2 and the various secondary
`references -- really only Splash2 matters -- but they did not contest that they
`were in fact functional matters. So we -- there was nothing amorphous. We
`gave a very specific interpretation and explicitly read it on the prior art.
`
`
`Now that the phrase functional unit itself might be somewhat
`flexible and the claim language is, first of all it's selected by the inventors,
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`by the Applicants, not by anybody else so if that's a problem for the Patent
`Owner that is a problem of the Patent Owner's making. But also there's
`nothing wrong with it. Broad claim language, there's just nothing wrong
`with that. It might create a validity issue which it appears to do so here but
`we all know that people write claims like that because there's another side of
`the coin, it's called infringement, and they want to capture the principle of
`the broad claim.
`
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`JUDGE ARBES: I hope we, interpreting the claim, in
`particular the claim language here -- we can come up with something that's a
`little bit more not flexible, but as you said I'm not sure that the word directly
`conveys that.
`
`
`MR. MICALLEF: Well I mean I think both sides has adopted,
`if you will, an interpretation of that word, of that interpretation to mean no
`memory and I don't think there's any dispute on that and so in that context
`that's obviously what we have been talking about in the briefing about
`directly and I think that's a perfectly fine interpretation. It's consistent with
`everything before you. So, you brought up --
`
`
`JUDGE ARBES: Can you address Dr. Stone's testimony, in
`particular from pages 85 to 87 I believe?
`
`
`MR. MICALLEF: That's where he was asked about the
`footnote that talks about a register you could add?
`
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`JUDGE ARBES: Yes.
`
`
`MR. MICALLEF: Yes. So first of all that footnote in Splash2
`is an alternative embodiment of that, I think it's the unidirectional systolic
`array. It says you can add or you may add a register, something along those
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`lines. So it's not what we actually read the claim on. It is not the disclosure
`that we read the claim on but even so it says it's within the processing
`element and I think that's what -- in fact I think I have the testimony here.
`Yes, I'm on slide 16. I think this is the testimony that you're referring to
`where he pointed out when questioned about it that that register is not
`between processing elements. So --
`
`
`JUDGE ARBES: If we can take a step back -- outside of
`Splash2, just thinking about claim interpretation and whether that word
`directly should be part of the interpretation of the limitation, what is direct
`and what's not I think is the question.
`
`
`MR. MICALLEF: I think --
`
`
`JUDGE ARBES: The original question had to do with just
`memory rather than a register in particular, at least the original question.
`
`
`MR. MICALLEF: Well I think register would be a form of
`memory and I think everybody sort of looked at it that way so I'm not sure
`what distinction you're asking me about there.
`
`
`JUDGE ARBES: Well if we can -- you have the testimony, so
`the original question at the top, or the bottom of page 85 going to 86,
`
`
`"Would memory, if the data was going from one processing
`element to memory and then back to a processing element, is that something
`you would consider as an intervening thing?"
`
`
`"That would not be a direct connection of the output of the cell
`to the next cell."
`
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`MR. MICALLEF: Yes. So the distinction here, the dichotomy
`here is whether the memory is in between functional units or not, or within a
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`functional unit and of course that matters because a functional unit is the
`thing that's doing the processing and we're in the context of a systolic and a
`data driven array. So passing data from one functional unit to the other has
`to follow that systolic technique or that data driven technique if we're going
`to talk about the claims of the 800 patent. So not having a memory in
`between, at least as these folks claimed it, is of significance. I agree, it
`might not be in a non-systolic context or non-data driven context but in this
`context to this invention it had some importance.
`
`
`But the dichotomy is whether that register is inside the thing
`that's doing the processing, the computational loop, or in between the things
`that are doing it and that is the distinction that's set forth in the intrinsic
`record and that's the distinction that Dr. Stone is pointing to. There is no
`register in between or other type of memory in between the processing
`elements of Splash2. In fact you can it on this slide 16 that I have up here.
`It depicts just a direct passing of data from one processing element to the
`other as do the other references that we pointed to. If I can pick it up at,
`unless Your Honors have any more questions about passing data seamlessly,
`I'd like to move on to the stream communication.
`
`
`JUDGE ARBES: One last question. Can you respond to the
`Patent Owner's argument that Petitioner's reading is nonsensical because
`standard FPGAs have the reconfigurable routing resources, which would
`have a buffer, for instance, between the logic blocks?
`
`
`MR. MICALLEF: Well I think Dr. Stone said not necessarily,
`that's not necessarily so that you would have to -- so wait a second, you just
`said logic blocks and so what Dr. Stone has testified to is that in as
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`IPR2018-01601 (Patent 7,225,324 B2)
`IPR2018-01605 (Patent 7,620,800 B2)
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`configured in the FPGAs of Splash2 the processing elements do not have
`any memory in between them. So they may have memory within them and
`the processing elements I expect would be made of a number of different
`logic blocks in order to perform those computational loops that are in those
`figures. I mean I don't think any of the testimony got down to that level so
`we're speculating at that point. But he was very clear that Splash2, the
`processing elements of Splash2, do not have memory between the
`processing elements which are the things that we read the functional unit
`claim language on to.
`
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`JUDGE ARBES: But do have memory as part of --
`
`
`MR. MICALLEF: May, may. There's no disclosure of that by
`the way, there's nothing in Splash2 that they actually do have. There's that
`one footnote that says you could put a register in there in the alternative
`embodiment. But I will admit -- so let me since you brought it up let me
`bring up slide 17. The same issue came up with the Splash2 RaPiD
`combination. Now there's another problem with this one because the
`combination here was taking the DCT calculations of RaPiD and
`implementing them on the system of Splash2. So whether or not the RaPiD
`system had memory between functional units is actually irrelevant because
`you have to treat the combination as a whole, not the references individually.
`But be that as it may, RaPiD does disclose the direct connection of what we
`would call functional units which I have an example of that on this slide 17
`which is -- I forget the figure number but it's in our system and you can see
`there's RAM in this functional unit inside it, within it, but there is no
`memory between this and its neighboring functions. So that's exactly the
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