Asserted Claim of ’800
`Patent
`[1A] A method for data
`processing in a reconfigurable
`computing system, the
`reconfigurable computing
`system comprising at least one
`reconfigurable processor, the
`reconfigurable processor
`comprising a plurality of
`functional units, said method
`comprising:
`
`Exemplary Disclosure of Gaudiot
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at Abstract (“New technologies of integration allow the design of powerful systems which
`may include several thousands of elementary processors. These multiprocessors may be used for a
`range of applications in signal and data processing. However, assuring the proper interaction of a
`large number of processors and the ultimate safe execution of the user programs presents a crucial
`scheduling problem. The scheduling of operations upon the availability of their operands has been
`termed the data-driven mode of execution and offers an elegant solution to the issue. This approach
`is described in this paper and several architectures which have been proposed or implemented
`(systolic arrays, data-flow machines, etc.) are examined in detail. The problems associated with
`data-driven execution are also studied. A multi-level approach to high-speed digital signal
`processing is then evaluated.”)
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 1
`
`

`

`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 2
`
`

`

`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at Abstract (“New technologies of integration allow the design of powerful systems which
`may include several thousands of elementary processors. These multiprocessors may be used for a
`range of applications in signal and data processing. However, assuring the proper interaction of a
`large number of processors and the ultimate safe execution of the user programs presents a crucial
`scheduling problem. The scheduling of operations upon the availability of their operands has been
`
`[1B] transforming an algorithm
`into a data driven calculation
`that is implemented by said
`reconfigurable computing
`system at the at least one
`reconfigurable processor;
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 3
`
`

`

`termed the data-driven mode of execution and offers an elegant solution to the issue. This approach
`is described in this paper and several architectures which have been proposed or implemented
`(systolic arrays, data-flow machines, etc.) are examined in detail. The problems associated with
`data-driven execution are also studied. A multi-level approach to high-speed digital signal
`processing is then evaluated.”)
`
`Gaudiot at 1220-21 (“The overall objective of this paper is to demonstrate the applicability of data-
`driven principles of execution to the design of high-performance signal and data processing
`architectures. Several approaches will be demonstrated and their particular domain of application
`will be contrasted. The description of low-level processing systems is beyond the scope of this paper
`and the interested readerr is referred to an excellent survey by Allen [3]. Instead, we will concentrate
`here on the issues related to building high-performance multiprocessors for signal processing
`applications. In Section II, we show the type of problems considered in signal processing. The data-
`flow principles of execution as they relate to digital signal processing problems are described in
`detail in Section Ill while several existing data-driven architectures are described in Section IV. In
`Section V, we analyze a multi-level datadriven architecture and examine its programming
`environment. Conclusions are drawn in Section VI.”)
`
`Gaudiot at 1222 (“C. Structure Handling
`This is a crucial issue in signal processing for this kind of application requires that many data
`elements which belong to the same structure be processed in a parallel or pipelined fashion. One of
`the basic premises of data-flow principles states that an output is a function of its inputs only,
`regardless of the state of the machine at the time of execution.”)
`
`Gaudiot at 1224 (“IV. DATA-DRIVEN ARCHITECTURES
`We now describe in detail several systems which operate at runtime, compile-time, or design-time
`under data-driven execution. Although it is generally considered that data-flow principles of
`execution are in effect at runtime, we extend their domain of application to design or compile time
`and refer to them as data-driven systems. We thus initially examine multiprocessor systems where
`data dependencies have been frozen at design time (systolic arrays). We then consider
`programmable systolic arrays (the Wavefront Array Processor) and multiprocessors scheduled at
`compile time by the use of data-flow program graphs (the ESL polycyclic processor).”)
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 4
`
`

`

`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 5
`
`

`

`
`
`
`Gaudiot at 1230 (“The data-flow multiprocessors which we have described (the HDFM, the MIT
`tagged token data-flow machine, and the USC TX16) offer much more flexibility in that their
`scheduling is in a larger part decided at compile time. They possess no notion of central control and
`can deliver maximum parallelism in very complex algorithms without any intervention from the
`designer, programmer, or compiler.”)
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 6
`
`

`

`[1C] forming at least two of
`said functional units at the at
`least one reconfigurable
`processor to perform said
`calculation
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 7
`
`

`

`[1D] wherein only functional
`units needed to solve the
`calculation are formed and
`
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 8
`
`

`

`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 9
`
`

`

`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`
`[1E] wherein each formed
`functional unit at the at least
`one reconfigurable processor
`interconnects with each other
`formed functional unit at the at
`least one reconfigurable
`processor based on
`reconfigurable routing
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 10
`
`

`

`resources within the at least
`one reconfigurable processor
`as established at formation
`
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 11
`
`

`

`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`[1F] wherein lines of code of
`said calculation are formed as
`clusters of functional units
`within the at least one
`reconfigurable processor;
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 12
`
`

`

`[1G] utilizing a first of said
`formed functional units to
`operate upon a subsequent data
`dimension of said calculation
`forming a first computational
`loop; and substantially
`concurrently utilizing a second
`of said formed functional units
`to operate upon a previous data
`dimension of said calculation
`forming a second
`computational loop
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 13
`
`

`

`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`At least under Plaintiff’s apparent theories of infringement and interpretations of the claims in
`alleging that any of Defendant’s accused products satisfy this claim limitation, Gaudiot alone or in
`combination with one or more references, discloses:
`
`Gaudiot at 1224-25 (“A. Systolic Arrays [32]
`The primary goal of a systolic array is to make use of the large amount of processing power
`available in VLSl technology by using repetitive circuitry to perform signal processing problems,
`matrix operations, image processing, etc. In summary, a systolic array is simply a collection of
`
`[1H] wherein said
`implementation of said
`calculation enables said first
`computational loop and said
`second computational loop to
`execute concurrently and pass
`computed data seamlessly
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 14
`
`

`

`between said computational
`loops.
`
`interconnected Processing Elements (PES). In order to incorporate as many processors as possible,
`the structure of the PES themselves is kept to a maximum simplicity and usually includes only a few
`operation units. For design simplification, there are few types of PES in the same system. By the
`same token, interconnections are kept to a nearest neighbor topology in order to minimize
`communication delays as well as power distribution issues. Note that topologies include two
`neighbors (linear arrays), four neighbors (square arrays), or six neighbors (hexagonal arrays) as
`required by the problem to solve. This is notably due to the fact that scheduling mechanisms must be
`based upon local criteria such as data availability. However, it should be noted that there is a global
`clock in all the computation cells. Linear systolic arrays can tolerate clock skews at both ends, but
`multidimensional designs require slower clocks in order to compensate. In order to simplify runtime
`mechanisms, the design of a systolic array emphasizes an efficient mapping of the problem onto
`architecture. An example of a band matrix-vector multiplication is shown in Fig. 6. It displays how
`the synchronization of the processors and of the input data rate has been mapped to meet the
`requirements of the problem. Note that each processor is designed to operate upon the arrival of the
`arguments. In summary, it should be noted that systolic arrays are very efficient at computationally
`intensive problems which involve many repetitive low-level calculations. Also, the very nature of
`their design renders their function fixed at design time.”)
`
`Gaudiot at Figure 6:
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 15
`
`

`

`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`[8] The method of claim 1
`wherein said calculation
`comprises a JPEG image
`compression calculation.
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 16
`
`

`

`[9] The method of claim 1
`wherein said calculation
`comprises an MPEG image
`compression calculation.
`
`[17] The method of claim 1
`wherein said calculation
`comprises a search algorithm
`for an image search
`
`[18] The method of claim 1
`wherein said calculation
`comprises a search algorithm
`for data mining.
`
`[21] The method of claim 1
`wherein said calculation
`comprises a genetic pattern
`matching function.
`
`[22] The method of claim 1
`wherein said calculation
`comprises a protein folding
`function.
`
`[23] The method of claim 1
`wherein said calculation
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`To the extent Plaintiff asserts this limitation is not expressly or inherently disclosed under Plaintiff’s
`apparent claim construction, or any other claim construction, the claimed subject matter would have
`been obvious to a person of ordinary skill in the art considering this reference in combination with
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 17
`
`

`

`comprises an organic structure
`interaction function.
`
`the knowledge of one of ordinary skill in the art at the time of the alleged invention and/or the
`disclosures in one or more of the references identified in Section I.B.2 of the cover pleading.
`
`
`
`
`Patent Owner Saint Regis Mohawk Tribe
`Ex. 2057, p. 18
`
`