IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`POWER INTEGRATIONS, INC.
`Petitioner,
`
`v.
`
`SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
`
`Patent Owner
`
`
`U.S. Patent No. 7,944,272
`
`DECLARATION OF DR. THOMAS SZEPESI IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,944,272
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`1
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`PI 1003
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`

`

`U.S. Patent No. 7,944,272
`
`TABLE OF CONTENTS
`
`
`I.  QUALIFICATIONS ........................................................................................... 5 
`  Testifying Expert Engagements during the past four years .......................... 8 
`II.  LEGAL STANDARDS ...................................................................................... 9 
`III.  LEVEL OF ORDINARY SKILL IN THE ART ............................................. 13 
`IV.  TECHNOLOGY OVERVIEW ........................................................................ 13 
`  Some constant current circuits used in integrated circuits .......................... 13 
`  Constant voltage circuits ............................................................................. 21 
`  Temperature compensated constant voltage and constant current circuits . 24 
`V.  OVERVIEW OF THE ’272 PATENT ............................................................. 28 
`VI.  THE CHALLENGED CLAIMS OF THE ’272 PATENT ARE INVALID ... 37 
`  Claims 1 and 2 are obvious based on the combination of Tanizawa (’990)
`with Ichimaru (’395) ................................................................................... 37 
`1.  Overview of Tanizawa ............................................................................. 37 
`2.  Overview of Ichimaru ............................................................................... 42 
`3.  Combining Tanizawa with Ichimaru ........................................................ 46 
`4.  Tanizawa in combination with Ichimaru discloses all the limitations of
`claim 1 and claim 2 of the ’272 patent ..................................................... 50 
`  Claims 1 and 2 are obvious based on the combination on Tanizawa (’990)
`with Shibata (’391) ...................................................................................... 79 
`1.  Overview of Shibata ................................................................................. 79 
`2.  Combining Tanizawa with Shibata .......................................................... 82 
`3.  Tanizawa in combination with Shibata discloses all the limitations of
`claim 1 and claim 2 of the ’272 patent ..................................................... 87 
`VII. CONCLUSION ..............................................................................................117 
`
`
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`2
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`U.S. Patent No. 7,944,272
`
`I, Thomas Szepesi, declare as follows:
`
`1.
`
`I have been engaged as an expert by Fish & Richardson P.C. on behalf
`
`of Power Integrations, Inc. (“Petitioner”) for the above-captioned inter partes review.
`
`I understand that this proceeding involves United States Patent No.7,944,272
`
`entitled “Constant current circuit”, by Tomoaki Nishi, filed September 29, 2009 and
`
`issued May 17, 2011 (the “’272 Patent” or “’272”). I understand that the ’272
`
`Patent is currently assigned to Semiconductor Components Industries, LLC.
`
`2.
`
`For purposes of this declaration, I assume the earliest possible priority
`
`date of the ’272 Patent is September 29, 2008 (see ’272, 1:6-9).
`
`3.
`
`I have reviewed and am familiar with the specification of the ’272
`
`Patent. I understand that the ’272 Patent has been provided as Exhibit 1001. I will
`
`cite to the specification using the following format (’272, 1:1-10). This example
`
`citation points to the ’272 Patent specification at column 1, lines 1-10.
`
`4.
`
`I have reviewed and am familiar with the file history of the ’272
`
`Patent. I understand that the file history has been provided as Exhibit 1002.
`
`5.
`
`I have also reviewed and am familiar with the following prior art used
`
`in the Petition for Inter Partes Review of the ’272 Patent:
`
` U.S. Patent No. 5,430,395 (“Ichimaru”, “’395 patent” or “’395”
`
`hereinafter”). I understand that Ichimaru has been provided as Exhibit
`
`1004. I will cite to the specification of Ichimaru in the following
`
`3
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`

`

`U.S. Patent No. 7,944,272
`
`format (’395, 1:1-10). This example citation points to the Ichimaru
`
`specification at column 1, lines 1-10.
`
` U.S. Patent No. 6,316,990 (“Tanizawa”, “’990 patent” or “’990”
`
`hereinafter”). I understand that Tanizawa has been provided as Exhibit
`
`1005. I will cite to the Tanizawa using the following format (’990,
`
`1:1-10). This example citation points to the Tanizawa specification at
`
`column 1, lines 1-10.
`
` European patent application No. EP 1 881 391 (“Shibata”, “’391
`
`application”, or “’391” hereinafter). I understand that Shibata has been
`
`provided as Exhibit 1006. I will cite to the Shibata using the following
`
`format (’391, [0002]:1-10). This example citation points to the
`
`Shibata specification at paragraph [0002] lines 1-10.
`
`6.
`
`A complete listing of additional materials considered and relied upon
`
`in preparation of my declaration is provided as Exhibit 1007. I have relied on these
`
`materials to varying degrees. Citations to these materials that appear below are
`
`meant to be exemplary but not exhaustive.
`
`7.
`
`The ’272 Patent describes constant current circuits comprising a
`
`temperature compensation circuit that outputs a temperature-compensated current, and a
`
`current supply circuit which supplies current to the temperature compensation circuit
`
`(’272, Title; Abstract). I am familiar with the technology described in the ’272
`
`4
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`

`

`U.S. Patent No. 7,944,272
`
`Patent as of the earliest possible priority date of the ’272 Patent (September 29,
`
`2008).
`
`8.
`
`I have been asked to provide my technical review, analysis, insights
`
`and opinions regarding the ’272 Patent and the above-noted references that form the
`
`basis for the Petition for Inter Partes Review of the ’272 Patent.
`
`QUALIFICATIONS
`I.
`9. My Resume is provided as Exhibit 1008. It includes a list of my 14
`
`publications and a list of the 23 patents I am a named inventor of.
`
`10. My expertise qualifies me to do the type of technical analysis required
`
`in this case. I have been involved in the definition, architectural design, circuit design
`
`and design management of analog integrated circuits, including linear and switching
`
`voltage regulators, since 1981.
`
`11.
`
`I was an assistant and associate professor of electrical engineering at the
`
`Department of Instrumentation and Measurement Technology at the Technical
`
`University of Budapest, Hungary between 1969 and 1980. I taught undergraduate and
`
`graduate courses in analog circuit design, computer aided design (CAD) and
`
`instrumentation. Aside of my teaching and research activities I also had a busy industrial
`
`consulting practice.
`
`12. After emigrating from Hungary in 1980, I worked as a Staff Applications
`
`Engineer at National Semiconductor Corp. from 1981 to 1983 in Fuerstenfeldbruck
`
`5
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`

`U.S. Patent No. 7,944,272
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`Germany. During that time I worked on the definition of custom integrated circuits,
`
`including the definition and architecture development of heating usage/cost
`
`measurement circuit and a controller circuit for an electronic ballast for fluorescent lights
`
`including a controller for a power factor correction circuit (PFC). I was also assigned as
`
`an application engineer supporting the products of the Hybrid IC Product Line in
`
`Europe, including supporting the design-in of hybrid amplifiers, buffers and hybrid
`
`DC/DC converter circuits like the LH1605 and the HS7067.
`
`13. Between 1983 and 1994, I worked at National Semiconductor Corp.,
`
`Santa Clara, CA, as Staff Design Engineer, Design Manager and Senior Design
`
`Manager. During my tenure as a Design Manager/Senior Design Manager I
`
`managed a group of electrical engineers responsible for the design of linear and
`
`switching voltage regulators. These integrated circuits included constant current
`
`bias and reference circuits. Based upon this experience, I have an understanding as
`
`to the skills and creativity of such engineers, including their background
`
`knowledge, their facility with applying known techniques to solve problems.
`
`14. During my tenure at National Semiconductor I defined, designed and
`
`managed the design of numerous integrated circuits in the power management
`
`area. These integrated circuits included buck switching regulators, boost switching
`
`regulators, offline DC/DC converter controllers and low dropout linear regulators,
`
`6
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`

`

`U.S. Patent No. 7,944,272
`
`e.g. the LM2575, LM2576, LM2595, LM2603/2610, LM 2577, LM2587,
`
`LM3001/3002, LP2956, LP2957, etc., and their derivative products.
`
`15. From 1994 through 2002, I served as the Product Line Director for the
`
`Power Management Group of Analog Devices, Inc., in San Jose, California. I built
`
`this product line from the ground up. My responsibilities included strategy
`
`development, product definition, design, applications, product and test engineering
`
`and marketing. We developed linear and switching voltage regulator and battery
`
`charger integrated circuits for desktop and laptop computers and cellular phones.
`
`Representative products in each category are listed in my Resume. I built the
`
`business from zero to a $62M profitable business in 6 years.
`
`16. From 2002 to 2004, I was Vice President of Engineering and member
`
`of the Board of Directors at iWatt, Inc. in Los Gatos, CA, a fabless start-up
`
`company. At iWatt Inc. we developed digital controllers for off-line switching
`
`voltage regulators. iWatt was acquired by Dialog Semiconductor in 2013 for
`
`approximately $360M.
`
`17. Since my retirement from full time work in the industry in 2004, I
`
`have been a consultant for semiconductor companies and law firms. I consulted
`
`mainly in the areas of power electronics and related controllers and integrated
`
`circuits.
`
`7
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`

`

`U.S. Patent No. 7,944,272
`
`18.
`
` My industry consulting activity related to areas including architecture
`
`design, circuit design, design reviews, layout reviews, process development, etc.
`
`My clients included start-up companies (e.g., Adaptive Digital Power Inc.,
`
`Fyrestorm Inc., Gazelle Semiconductor, Inc., and Zilker Laboratories Inc.), as well
`
`as established semiconductor companies (e.g., Dialog Semiconductor plc.,
`
`Integration Associates, Intersil Inc., Maxim Integrated Products Inc. and UMC
`
`Group (USA)).
`
`19. Since 2005, I have also acted as a testifying and non-testifying expert
`
`in numerous patent litigation cases and patent reexamination cases in the power
`
`electronics and related integrated circuit areas.
`
` Testifying Expert Engagements during the past four years
`I have testified as an expert witness at trial or by deposition during the
`
`20.
`
`previous four years in the following cases:
`
` Volterra Semiconductor Corporations v. Primarion, Inc. et al., case
`
`No. 08-5129 (N.D. Cal.). My work was related to US Patents
`
`6,278,264, 6,462,522 and 6,713,823. I was also involved with and
`
`submitted declarations in the Ex-parte Reexamination of the ’264 and
`
`’522 Patents (and two other Volterra patents which were not part of
`
`this litigation).
`
`8
`
`

`

`U.S. Patent No. 7,944,272
`
` Infineon Technologies AG v. Volterra Semiconductor Corporation,
`
`case No. CV-11-6239 (MMC) (N.D.Cal.). My work was related to US
`
`Patent 5,945,730.
`
`21. My work on this case is being billed at a rate of $450.00 per hour, with
`
`reimbursement for actual expenses. My compensation is not contingent upon the
`
`outcome of this inter partes review or the litigation involving the ’272 Patent.
`
`II.
`22.
`
`LEGAL STANDARDS
`I am not a lawyer and will not provide any legal opinions. Although I
`
`am not a lawyer, I have been advised that certain legal standards are to be applied by
`
`technical experts in forming opinions regarding the meaning and validity of patent
`
`claims.
`
`A. Anticipation
`
`23.
`
`I understand that a prior art reference anticipates a patent claim if that
`
`single reference, either expressly or inherently, discloses all limitations of that claim in
`
`the same arrangement as claimed. Where appropriate, I will conduct a step-by-step
`
`comparison between prior art references and the particular claim being evaluated. I also
`
`understand that a claim lacks novelty if it was known or used by others in the United
`
`States, or patented and/or described in a printed publication in the United States or a
`
`foreign country before it was allegedly invented by the patent applicant. I also
`
`understand that a claim lacks novelty if it was patented or described in a printed
`
`9
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`

`U.S. Patent No. 7,944,272
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`publication in the United States or a foreign country or in public use or on sale in this
`
`country, more than one year before the effective patent application date.
`
`24.
`
`I understand that a reference anticipates a claim if it discloses the claimed
`
`invention “such that a skilled artisan could take its teachings in combination with his
`
`own knowledge of the particular art and be in possession of the invention.” (In re
`
`Graves, 69 F.3d 1147, 36 U.S.P.Q.2d 1697, 1701 (Fed Cir. 1995)).
`
`B. Obviousness
`
`25.
`
`I understand that a patent claim is invalid if the claimed invention
`
`would have been obvious to a person of ordinary skill in the field at the time of the
`
`purported invention, which is often considered the time the application was filed.
`
`This means that even if all of the requirements of the claim cannot be found in a
`
`single prior art reference that would anticipate the claim, the claim can still be
`
`invalid.
`
`26. As part of this inquiry, I have been asked to consider the level of
`
`ordinary skill in the field that someone would have had at the time the claimed
`
`invention was made. In deciding the level of ordinary skill, I considered the
`
`following:
`
`
`
`
`
`
`
`the levels of education and experience of persons working in the field;
`
`the types of problems encountered in the field; and
`
`the sophistication of the technology.
`
`10
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`

`U.S. Patent No. 7,944,272
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`27. To obtain a patent, a claimed invention must have, as of the priority
`
`date, been nonobvious in view of the prior art in the field. I understand that an
`
`invention is obvious when the differences between the subject matter sought to be
`
`patented and the prior art are such that the subject matter as a whole would have
`
`been obvious at the time the invention was made to a person having ordinary skill
`
`in the art.
`
`28.
`
`I understand that to prove that prior art or a combination of prior art
`
`renders a patent obvious, it is necessary to (1) identify the particular references that,
`
`singly or in combination, make the patent obvious; (2) specifically identify which
`
`elements of the patent claim appear in each of the asserted references; and (3)
`
`explain a motivation, teaching, need or market pressure that would have inspired a
`
`person of ordinary skill in the art to combine prior art references to solve a problem. I
`
`understand that certain objective indicia can be important evidence regarding
`
`whether a patent is obvious or nonobvious. Such indicia include: commercial
`
`success of products covered by the patent claims; a long-felt need for the invention;
`
`failed attempts by others to make the invention; copying of the invention by others
`
`in the field; unexpected results achieved by the invention as compared to the closest
`
`prior art; praise of the invention by the infringer or others in the field; the taking of
`
`licenses under the patent by others; expressions of surprise by experts and those
`
`skilled in the art at the making of the invention; and that the patentee proceeded
`
`11
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`

`U.S. Patent No. 7,944,272
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`contrary to the accepted wisdom of the prior art. To the extent these factors have
`
`been brought to my attention, if at all, I have taken them into consideration in
`
`rendering my opinions and conclusions.
`
`29. Furthermore, I understand that the United Sates Supreme Court in its
`
`KSR vs. Teleflex decision ruled that “Moreover, if a technique has been used to
`
`improve one device, and a person of ordinary skill in the art would recognize that it
`
`would improve similar devices in the same way, using the technique is obvious
`
`unless its actual application is beyond that person's skill.” KSR Intern. Co. v.
`
`Teleflex Inc., 550 U.S. 398, 401 (2007). In the same decision the United Sates
`
`Supreme Court also ruled that: “When there is a design need or market pressure to
`
`solve a problem and there are a finite number of identified, predictable solutions, a
`
`person of ordinary skill has good reason to pursue the known options within his or
`
`her technical grasp. If this leads to the anticipated success, it is likely the product
`
`not of innovation but of ordinary skill and common sense. In that instance the fact
`
`that a combination was obvious to try might show that it was obvious under §103.”
`
`KSR Intern. Co. v. Teleflex Inc., 550 U.S. at 421.
`
`C.
`
`30.
`
`Inherency
`
`I understand that inherent anticipation of a limitation arises when the
`
`prior art necessarily functions in accordance with, or includes, the claimed
`
`limitation regardless of whether a person of ordinary skill in the art would
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`12
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`U.S. Patent No. 7,944,272
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`recognize the inherent characteristics or functioning of the prior art.
`
`D. Claim construction
`
`31.
`
`I understand that, during an inter partes review a claim should be
`
`given its broadest reasonable construction in light of the whole patent, including its
`
`specification and all of its claims, and in light of the knowledge of a person of
`
`ordinary skill in the art. I further understand that claim terms should be construed
`
`consistently across all claims.
`
`III. LEVEL OF ORDINARY SKILL IN THE ART
`32. A person of ordinary skill in the art at the time of the alleged invention
`
`(“POSITA”) would have had the equivalent of a Bachelor’s degree or higher in
`
`electrical engineering with at least 3 years working experience in the design of
`
`electronic circuits, would be familiar with the techniques and circuits used in analog
`
`integrated circuits and with the fabrication of analog integrated circuits. Based on my
`
`education and work experience, I consider myself to have at least the qualifications of a
`
`POSITA.
`
`IV. TECHNOLOGY OVERVIEW
` Some constant current circuits used in integrated circuits
`33. Constant current circuits (also referred to as current source circuits, or
`
`current reference circuits in the art) were well known in the art of electronic circuits
`
`and in the art of analog integrated circuits. In analog integrated circuits they were
`
`used for biasing (e.g., biasing differential input stages of operational amplifiers),
`
`13
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`

`U.S. Patent No. 7,944,272
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`timing circuits (e.g., in the oscillators of switching voltage regulators), load circuits
`
`(e.g., for amplifier stages), etc. The adjective “constant” in constant current circuits
`
`referred in the art (among other characteristics) to the characteristic of these circuits
`
`that the current they provide on their output is substantially independent of the load
`
`condition, e.g., the value of the load resistance/impedance, or the voltage on their
`
`output (assuming that the voltage is higher than a minimum value, related to the
`
`saturation of the output transistor, and lower than a maximum value related to the
`
`breakdown of the transistors utilized by the constant current source) (see e.g.,
`
`Chapter 3.1, pp. 136-143, of Analog Integrated Circuits, by Sidney Soclof , ©1985
`
`Prentice Hall, Inc.; “Soclof” hereinafter, Ex. 1009). This characteristic corresponds
`
`to a high output resistance (or impedance) of the output transistor of the constant
`
`current source. Ideally the output resistance of a current source should be infinite.
`
`As a POSITA would have known, practical transistors can be modeled as voltage
`
`controlled, or current controlled, current sources with high but finite output
`
`resistance. The output resistance of transistors operating in their linear active region
`
`depends of their Early voltage. If the Early voltage of the output transistor of a
`
`constant current source is high compared to the supply voltage of the circuit the
`
`current sourced by the transistor is substantially independent of the voltage across
`
`the transistor (e.g., collector-emitter voltage of a bipolar transistors). The higher the
`
`output resistance of a current source is the closer it is to be ideal (the more
`
`14
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`

`U.S. Patent No. 7,944,272
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`independent its output current is from its output voltage, sometimes called more
`
`compliant in the art). If higher output resistance was needed than what
`
`corresponded to the Early voltage of the output transistor of the constant current
`
`source the output resistance could be increased significantly using well known and
`
`understood circuit techniques (e.g., series feedback, cascoding, etc.).
`
`34. One of the simplest current sources used in integrated circuits (shown
`
`below in Fig. IV-1, based on Figure 3.6 of Soclof, p. 141) is based on the current
`
`mirror.
`
`
`
`
`
`
`
`
`
`
`
`Fig. VI-1
`
`
`
`35. Given that the base-emitted voltage of the two transistors are the same
`
`in this circuit their collector currents are also the same (I1=I2, neglecting the base
`
`currents, which may cause a few percent error). Hence, the output current I2, can be
`
`calculated as follows (assuming that the two transistors Q1 and Q2 have the same
`
`emitter area and the base currents are neglected): I2=(V+-V--VBE1)/R1, where VBE1
`
`15
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`

`

`U.S. Patent No. 7,944,272
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`is the base-emitter voltage of transistor Q1. The output resistance of this current
`
`source circuit is set by the output resistance of its output transistor Q2,
`
`corresponding to its Early voltage. This simple circuit has numerous shortcomings.
`
`First, the output current is strongly dependent of the supply voltage (V+-V-), as the
`
`equation above shows. Second, if small value output currents are required (in the
`
`micro Ampere range, which is typical for many integrated circuit applications) the
`
`value and corresponding size of resistor R1 can be very large, which has negative
`
`die size and cost implications for an integrated circuit using this current source.
`
`Third, the output resistance of the current source is limited by the output resistance
`
`(Early voltage) of transistor Q2, which, depending on the use of the current source
`
`may not be high enough. All of these shortcomings can be improved by a slight
`
`modification of the current source circuit, shown below in Fig. IV-2 (based on
`
`Figure 3.8 of Soclof, p. 143).
`
`
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`16
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`U.S. Patent No. 7,944,272
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`
`
`
`
`
`
`
`
`
`
`Fig. IV-2
`
`36. The insertion of resistor R2 in series with the emitter of transistor Q2
`
`represents a serial negative feedback, significantly increasing the output resistance
`
`of the current source, well beyond the output resistance of Q2 in the circuit of Fig.
`
`IV-1 above. The numeric example in Soclof shows a 5.6 times improvement of the
`
`output resistance (see Soclof pp. 142-144).
`
`37. The insertion of R2 also results in a significant reduction of the
`
`collector current of Q2 compared to the collector current of Q1, due to the nonlinear
`
`relationship of those two collector currents in the circuit of Fig. IV-2. As it was
`
`well known in the art the ratio of the two collector currents are defined by the
`
`following transcendent equation (see Soclof p. 144):
`
`
`
`
`
`
`
` I1/I2=exp(ΔVBE/VT)=exp(I2*R2/VT)
`
` Eq. IV-1
`
`where VT is the thermal voltage: VT=kT/q; where k is the Boltzmann constant, T is
`
`the absolute temperature and q is the charge of an electron. As the thermal voltage,
`
`VT, is proportional to absolute temperature its temperature coefficient is
`
`3300ppm/degC. The sensitivity of the output current I2 to the supply voltage (V+-
`
`V-) is significantly lower than the sensitivity of the simple current mirror circuit in
`
`Fig. IV-1 (which has a sensitivity of approximately 1). Based on the numerical
`
`example of Soclof the supply sensitivity of the output current of the current source
`
`circuit in Fig. IV-2 is about 5.6 times lower than the supply sensitivity of the
`
`17
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`

`U.S. Patent No. 7,944,272
`
`circuit of Fig, IV-1 (see Soclof p. 145), a significant improvement.
`
`38. Finally, the insertion of R2 also reduces the current of transistor Q2
`
`relative to transistor Q1. Based on the numerical example given by Soclof (see
`
`Soclof p. 143) a ratio of 100:1 can be easily achieved, while the total value of
`
`R1+R2 is close to 50 times lower than it would have to be using the simpler circuit
`
`of Fig. IV-1.
`
`39. While the circuit in Fig. IV-2 is a significant improvement compared
`
`to the circuit of Fig. IV-1 it still has a significant sensitivity to supply voltage (V+-
`
`V-) variations, which is undesirable in many applications. An improved prior art
`
`circuit providing a supply independent constant current source (for supply
`
`independent biasing) is shown below in Fig, IV-3, based on Figure 4.25.a (on p.
`
`283) of Analysis and Design of Analog Integrated Circuits, 2nd Edition, by Paul. R.
`
`Gray and Robert G. Meyer, © 1977, 1984 by John Wiley & Sons, Inc.; “Gray &
`
`Meyer” hereinafter; Ex. 1010).
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`18
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`U.S. Patent No. 7,944,272
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`
`
`
`
`
`
`Fig. IV-3
`
`
`
`40. This circuit is self-biased. Current mirror Q3-Q4 ensures that the
`
`collector currents of transistors Q1 and Q2 are the same (neglecting base currents).
`
`If the emitter area of transistors Q2 and Q1 have a ratio of N (EAQ2/EAQ1=N,
`
`corresponding to the same ratio of the saturation currents, IS, of the two transistors)
`
`then (see Gray & Meyer, p. 282):
`
`
`
`
`
`
`
`Vx=VT*ln(N)
`
`hence (neglecting the base currents),
`
`
`
`
`
` IOUT=Iref=IC2=(VT/R2)*ln(N)
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`
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`Eq. IV-2
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`41.
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`If, as in the numeric example in Gray & Meyer, the emitter area of
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`transistor Q2 is twice the emitter area of transistor Q1 then the equation above
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`becomes IOUT=Iref=IC2=(VT/R2)*ln 2. Based on this equation and Eq. IV-2 above,
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`U.S. Patent No. 7,944,272
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`the output current of this constant current source is substantially independent of the
`
`supply voltage VCC. This of course is the ideal case, in practical circuits there is
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`some supply voltage dependence but it is typically small enough to be considered
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`negligible.
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`42. The output current of the self-biased constant current source circuit of
`
`Fig. IV-3 is proportional to the thermal voltage VT, which is proportional to the
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`absolute temperature, T (see above in ¶37). Hence, neglecting the temperature
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`dependence of resistor R2, the output current of the constant current source is
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`proportional to absolute temperature, T, and has a temperature coefficient of
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`3300ppm/degC. Current sources with this property are often called PTAT current
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`sources, where the acronym PTAT stands for “Proportional To Absolute
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`Temperature”. PTAT constant current sources, like the one shown in Fig. IV-3
`
`above, have been well known and widely used in the prior art, e.g., for biasing
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`differential transistor pairs at the front end of operational amplifiers, thereby
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`stabilizing their transconductance over temperature. While the circuit in Fig. IV-3
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`is self-biased it has a secondary stable state at zero current. Hence, it requires a
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`small start-up current source to start up which is not shown in the circuit of Fig.
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`IV-3. There were numerous start-up circuits used and were well known in the prior
`
`art.
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`43. While the PTAT temperature dependence of the constant current
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`U.S. Patent No. 7,944,272
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`circuit of Fig. IV-3 is useful in some applications it is undesirable in others where
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`substantially constant current over temperature is needed (e.g., in oscillator
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`circuits, etc.). There were numerous constant current circuits in the prior art
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`providing output currents that were substantially independent of temperature (see
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`e.g., Ichimaru, Tanizawa, Shibata, etc., which are discussed in detail below, in
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`section VI.).
`
` Constant voltage circuits
`In analog integrated circuits there is also a need for constant voltage
`
`44.
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`circuits, e.g., for biasing, or for generating threshold voltages, or for reference
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`voltage purposes. The ideal constant voltage source has an output voltage that is
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`temperature independent (has zero temperature coefficient), supply voltage
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`independent and has very low output resistance (or impedance) making its voltage
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`substantially independent of load current. Is some applications, where the constant
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`voltage circuit has substantially zero (or negligibly low) load current, the low
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`output resistance characteristic is not necessary.
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`45. One of the simplest constant voltage sources in integrated circuits
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`utilized the forward voltage drop of a diode (or a diode connected bipolar
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`transistor) forward biased for example by a current source circuit. The approximate
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`forward voltage drop of a diode is 0.7V, it is weakly dependent of the diode’s
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`forward current, among other things. The diode forward voltage, VD, is defined by
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`U.S. Patent No. 7,944,272
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`the Shockley equation (as a POSITA would have known):
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`
`
`
`
`
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`VD=VT*ln(ID/IS)
`
`
`
`
`
` Eq. IV-3
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`where VT is the thermal voltage, ID is the forward current of the diode and IS is the
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`saturation current of the diode, which depends on the semiconductor process, the
`
`size of the diode, the temperature, etc. If higher voltage was needed multiple
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`diodes could be connected in series. However, this series connection enabled only
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`the creation of diode voltage sources with discrete values (integer multiples of a VD
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`diode voltage).
`
`46.
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`If different voltages were needed simple VBE multiplier circuits were
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`used in the prior art which could generate voltages which were rational multiples
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`of discrete diode voltages. A VBE multiplier voltage source circuit is shown below
`
`in Fig. IV-4, based on Figure 3.31 of Soclof (p. 172).
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`U.S. Patent No. 7,944,272
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`
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`
`
`Fig. IV-4
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`
`
`
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`47. The output voltage VO of this voltage source can be expressed
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`(neglecting the base current of the transistor) (see Soclof, p. 172):
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`
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`VO=VBE*(R1+R2)/R2= VBE*(1+R2/(R1)=VR1+VR2 Eq. IV-4
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`where VBE is the base-emitter voltage of the NPN transistor, VR1 and VR2 are the
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`voltage drops on resistors R1 and R2 respectively; VR1=VBE and
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`VR2=VBE*( R2/(R1). Hence, the output voltage of the VBE multiplier circuit is a
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`rational multiple of the VBE voltage of the transistor (which corresponds to a
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`forward biased diode voltage), where the rational multiple is set by the resistor
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`ratio R2/R1.
`
`48.
`
`In the diode voltage equation Eq. IV-3 above both VT and IS are
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`U.S. Patent No. 7,944,272
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`temperature dependent. As it was well known to a POSITA, their combined effect
`
`leads to a diode forward voltage temperature dependence (i.e., the temperature
`
`dependence of a VBE voltage) of approximately -2mV/degC (see e.g., Gray &
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`Meyer, p. 290).
`
`49. Aside of diode forward voltage, diode reverse breakdown voltage was
`
`also used in prior art integrated circuits as constant voltage circuit. The breakdown
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`voltage depends on the doping levels of the p-n junction forming the diode. A
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`typical emitter-base p-n junction may have had a breakdown voltage of around
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`5.6V. The p-n junction could have been reverse biased by a current source to form
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`a constant voltage source. These reverse biased diodes operating in breakdown
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`sometimes were called Zener diodes in the art. As these types of voltage references
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`are not relevant for the present case they will not be discussed in detail.
`
` Temperature compensated constant voltage and constant
`current circuits
`50. For many applications constant voltage circuits are required that are
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`temperature independent, i.e., have an output voltage with substantially zero
`
`temperature coefficient (e.g., for voltage references). The most often used such
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`circuit (in integrated circuits) is the band gap reference circuit which combines a
`
`diode forward drop voltage with negative temperature coefficient (-2mV/degC)
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`with an appropriate value of PTAT voltage which has a positive temperature
`
`coefficient. The principle is illustrated by the circuit below in Fig. IV-5, based on
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`Figure 4.28 of Gray & Meyer (see p. 290).
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`U.S. Patent