(12) United States Patent
`Luhmann et all
`
`e
`
`USOO6865152B2
`(10) Patent No.:
`US 6,865,152 B2
`45) Date of Patent:
`Mar. 8, 2005
`
`e
`
`e
`
`(54) METHOD AND APPARATUS FOR
`TRANSMITTING PACKETS ONTO A
`NETWORK
`
`(75) Inventors: East t Ey, E. RoR
`S. alrick L. UOnnor, Portland,
`
`(73) ASSignee: Intel Corporation, Santa Clara, CA
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 802 days.
`
`(21) Appl. No.: 09/738,110
`(22) Filed:
`Dec. 15, 2000
`(65)
`Prior Publication Data
`US 2002/0075801 A1 Jun. 20, 2002
`(51) Int. Cl. .................................................. H04L 1100
`(52) U.S. Cl. ..................................... 370/230; 370/236.1
`(58) Field of Search ................................. 370230, 236,
`370/236.1, 329, 390, 250, 412; 710/63
`• us
`s
`s
`s
`s
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`5,784,358 A * 7/1998 Smith et al. ............. 370/236.1
`5,978,359 A * 11/1999 Caldara et al. ............. 370/236
`6,185.229 B1 * 2/2001. Obikane et al. ............ 370/537
`
`6,301.258 B1 * 10/2001 Katseff et al. .............. 370/412
`6,349,097 B1 * 2/2002 Smith ...............
`... 370/390
`6,381,661 B1 * 4/2002 Messerly et al. ............. 710/63
`6,430,628 B1
`8/2002 Connor
`6,510,145 B1
`1/2003 Kim et al. .................. 370/329
`6,597.662 B1 * 7/2003 Kumar et al. ............... 370/236
`6,614,756 B1 * 9/2003 Morgenstern et al. ...... 370/230
`6,647.438 B1 11/2003 McVay et al.
`6,721,835 B1
`4/2004 Connor
`2002/0O83189 A1
`6/2002 Connor
`2002/O144004 A1 10/2002 Gaur et al.
`2002/O194332 A1 12/2002 Connor
`2003/0058852 A1
`3/2003 Luhmann et al.
`2003/0065735 A1
`4/2003 Connor
`* cited by examiner
`
`-
`Primary Examiner Salvatore Cangialosi
`(74) Attorney, Agent, or Firm-Libby H. Hope
`(57)
`ABSTRACT
`A network driver for transmitting packets. For a particular
`embodiment the driver receives
`indication that a packet
`S available for
`R SE FS, pris
`transmission status of a network controller. The driver then
`indicates to the network controller that the packet is avail
`able for transmission only when the pending transmission
`Status in one particular embodiment reaches a threshold
`value. Thus the driver determines how many packets to
`provide a network controller based on the amount of packets
`still waiting to be transmitted by the controller.
`
`36 Claims, 6 Drawing Sheets
`
`NPACKETS
`FROM OS
`
`70
`
`
`
`RESETX
`
`PREPARE
`NEXT
`PACKET
`
`e INCRENT
`
`66
`
`
`
`80
`
`NFORM
`CONTROLLER OF
`PREPARED
`PACKET FRAMES
`
`82
`
`84
`
`RESETI
`
`1
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`18 (a-n)
`
`ROUTER
`
`ROUTER
`
`1O
`
`7
`
`
`
`
`
`Fig. 1
`
`2
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`Mar. 8, 2005
`
`Sheet 2 of 6
`
`US 6,865,152 B2
`
`
`
`APPLICATION SENDS
`DATA TO OS
`
`OS BREAKS DATA
`INTO PACKETS AND
`FORMATS
`
`OS PROVIDES
`PACKETS TO
`NETWORK DRIVER
`
`DRIVER NOTIFIES
`CONTROLLERABOUT
`PACKET AVAILABILITY
`ORWAITS
`
`HARDWARE
`TRANSMITS PACKETS
`TO NETWORK
`
`
`
`68
`
`Fig. 2
`
`3
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`Mar. 8, 2005
`
`Sheet 3 of 6
`
`US 6,865,152 B2
`
`
`
`| LESERH
`
`SEÅ
`
`ENOCI
`
`
`
`„LNE WERBON|
`
`X CIN\/ |
`
`SO WOH-] S LEXIO\/d N
`
`X LESEXH
`
`4
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`Mar. 8, 2005
`
`Sheet 4 of 6
`
`US 6,865,152 B2
`
`INTERRUPT
`
`90
`
`
`
`RESET Y
`
`94
`
`/
`
`can
`p
`Transmit
`
`---
`
`92
`
`
`
`f.A.
`To Clean
`Up?
`98
`NP = P - Y -
`
`NO
`
`
`
`PACKETS r".
`
`---
`
`4
`
`P = bir
`106
`
`/
`
`96
`
`t Y
`? incren
`Cremen
`392
`INFORM
`CONTROLLER
`OF PREPARED
`
`1OO
`
`5
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`Mar. 8, 2005
`
`Sheet 5 of 6
`
`US 6,865,152 B2
`
`32
`
`PROCESSOR
`CACHE 408
`
`404
`
`PROCESSOR BUS
`
`410
`
`
`
`
`
`12
`
`413
`
`GRAPHICS
`CONTROLLER
`
`BRIDGE/MEMORY
`CONTROLLER
`
`38
`
`
`
`MEMORY
`
`INSTRUCTIONS
`
`DATA
`
`412
`
`FIRST /O BUS
`
`
`
`
`
`42 NETWORK
`CONTROLLER
`MODULE
`Fig. 6
`
`DISPLAY DEVICE
`CONTROLLER
`
`428
`
`BUS
`BRIDGE
`
`420
`
`SECOND /O BUS
`
`424
`
`425
`
`422
`
`
`
`DATA
`STORAGE
`
`KEYBOARD
`INTERFACE
`
`USER INPUT
`INTERFACE
`
`Fig. 5
`
`6
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`U.S. Patent
`
`Mar. 8, 2005
`
`Sheet 6 of 6
`
`US 6,865,152 B2
`
`
`
`
`
`
`
`14
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`46
`
`48
`
`/
`
`EEPROM
`
`FLASH
`ROM
`A
`
`CONNECTOR
`
`
`
`NETWORK
`CONTROLLER
`
`36
`
`50
`
`51
`
`TO PROCESSOR
`(Fig. 5)
`
`Fig. 6
`
`7
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`US 6,865,152 B2
`
`1
`METHOD AND APPARATUS FOR
`TRANSMITTING PACKETS ONTO A
`NETWORK
`
`BACKGROUND OF THE INVENTION
`
`1. Field
`The embodiments of the present invention relates gener
`ally to communication and more specifically to a driver for
`transmitting packets onto a high Speed Ethernet network.
`2. Background
`Network controllers are used to transmit and receive
`Ethernet packets from a network media. Ethernet Speeds
`typically include 10 Megabit, 100 Megabit, 1 Gigabit or 10
`Gbit per second technologies as described in the ANSI/IEEE
`802.3 specifications, published Oct. 2000. The network
`controller is typically coupled into the bus of a computer.
`The computer has a processor and host memory. The com
`puter has an operating System that communicates using a
`Software driver to the network card when an application in
`the computer needs to transfer information onto the network
`media for distribution to the Internet or other computers.
`Operating Systems provide indications to a Software
`driver that one or more packets are available for transmis
`Sion onto a network media. DriverS respond to the operating
`System by processing each packet by creating a table that
`contains a location in memory where the packets are Stored,
`as well as the length of the packet. The driver then informs
`the network controller that the packet is available for fetch
`ing and transmission onto the network media. The network
`controller receives packets from memory and stores the
`packet in an internal cache. The network controller then
`transmits the cached packet onto the network media.
`The driver typically receives multiple packets from the
`operating System. In one method, the driver then processes
`one packet at a time, and then immediately informs the
`network controller after each packet is processed, that a
`processed packet is available for transmission. Alternatively
`in a Second method, the driver may process all the packets
`it has been given, and then informs the controller that all
`packets are available for transmission.
`The first method improves packet latency because the
`network controller learns about each packet as Soon as it is
`available for transmission. However, this first method has
`the drawback of reduced bus efficiency, Since a bus trans
`action is required to proceSS each individual packet.
`The Second method increases bus efficiency because the
`entire table of packets only requires a Single bus transaction
`to inform the network controller that the packets are avail
`able for transmission. However, this method has the draw
`back of reduced packet latency because the first packet sits
`idle and is not handled by the network controller until the
`driver processes the Subsequent packets.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention will be understood more fully from the
`detailed description given below and from the accompany
`ing drawings of embodiments of the invention which,
`however, should not be taken to limit the invention to the
`Specific embodiments described, but are for explanation and
`understanding only.
`FIG. 1 is a diagram of a network having a host computer
`and router connected to other network devices,
`FIG. 2 is flow diagram of a packet transmit path in
`accordance with an embodiment of the present invention;
`
`1O
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`FIG. 3 is a flow diagram of the process executed by the
`network driver shown in FIG. 2 when transmitting packets
`in accordance with an embodiment the present invention;
`FIG. 4 is a flow diagram of the interrupt path in accor
`dance with an embodiment of the present invention;
`FIG. 5 is a diagram of a computer system shown in FIG.
`1 having a network controller in accordance with an embodi
`ment the present invention; and
`FIG. 6 is a diagram of the network controller module
`shown in FIGS. 1 & 5.
`
`DETAILED DESCRIPTION
`Referring to FIG. 1, there is shown an Ethernet network
`10 having a personal computer (PC) 12 connected through
`network media 14 to a network infrastructure device Such as
`a Router, Switch or hub 16 and PC's 18(a-n). Network
`media 14 may be an optical fiber or cable media, but may
`include other media Such as wireless, optical or other
`medias. PC 12 may be coupled through Router 16 to PC's
`20(a-n) or other network infrastructure devices Such as a
`Routers or switches 22(a-n). PC 12 includes a network
`controller module 28 having a network controller 42 coupled
`through controller 410 to processor 32 and host memory 38.
`Processor 32 executes a network driver 61 for controller
`module 28 that is stored in memory 38. Further details of
`controller 42, controller 410 and processor 32 will be
`discussed later in connection with FIGS. 5 and 6.
`Referring to FIG. 2, there is shown an embodiment of the
`flow diagram showing the proceSS for transmitting a data
`packet. In accordance with the embodiments of invention, an
`application program provides data to be transmitted to a PC
`operating System in block 60. Exemplary operating Systems
`include WindowsTM OS distributed Microsoft Corporation
`of Redmond, Wash., or Linux OS. The operating system
`then in block 62 breaks up data into packets to be transmitted
`and Stores these packets in host memory 38. The operating
`System also formats the packets by attaching headers and
`media access control information to the packets. OS formats
`the packets prior to passing them to the network driver.
`These packets or buffers, as known in the art typically
`contain an Ethernet packet having a Media Access Control
`(MAC) header, a Transmit Control Protocol/Internet Proto
`col (TCP/IP) header and application data.
`Next in block 64 the network driver 41 may be called by
`the operating System. The operating System then passes one
`or more packets to the network driver 41 and indicates a
`packet is available for transmission. The network driver 41
`then in block 66 prepares the packets for transmission by
`creating a data Structure containing the location and length
`of the packets provided by the operating System in host
`memory 38. In one embodiment, the data structure may be
`a table. The driver 41 then determines, by checking the
`Status of the network controller 42 and using the process
`described in more detail in FIG. 4, whether to indicate to the
`network controller 42 to transmit packets or whether to
`prepare more packets for transmission. Once the Status of the
`network controller 42 indicates that the number of pending
`transmissions of packets in its bufferS has reaches a prede
`termined threshold value, the driver 41 provides an
`indication, including the location and length of the packets,
`to the network controller 42 to transmit all the prepared
`packets. The number of pending transmission could be Said
`to reach this predetermined level when the number of
`pending transmission is below a predetermined value or if an
`up-counter is used to track the pending transmissions, when
`the up-counter reaches the predetermined value. The net
`
`8
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`3
`work controller 42 in block 68 transfers the prepared packets
`from host memory 38 into its internal First In First Out
`register (FIFO) 51 (FIG. 6) for transmission on the network
`media 14.
`Referring to FIG. 3, there is shown the process in block
`66 used by the network driver 41 to determine which packets
`controller 42 should transmit. The process 66 starts in block
`70 with a call by the operating System providing an indica
`tion that a number (N) of packet frames are to be transmitted.
`When driver 41 is first loaded (for example, as part of the
`boot process of the operating System), the Indexes P, T and
`I are set to Zero. Index I corresponds to the number of
`packets prepared Since the last time the driver informed the
`network controller 42 that prepared packets are ready to be
`transmitted. The network driver in block 70 sets a local
`variable X to zero.
`Then in block 72 the next packet may be prepared for
`transmission as described previously in connection with
`FIG. 2. Then in block 74, the value of Index I and X are
`incremented. In block 76 the driver determines whether
`value P, representing the current number of packets provided
`to the controller 42 for transmission and not yet transmitted,
`is less than a predetermined threshold value T. Value P is
`also referred to herein as the packet pending transmission
`status. Value P is preferably stored in host memory 38 and
`may be updated on an interrupt from network controller 42.
`The threshold value T typically ranges from 1 to 4 but does
`not require a bounded upper limit. Value T may be set to a
`value that promotes maximum performance of network
`controller 42. Value T would be set based on the time
`network controller 42 can handle an interrupt and to ensure
`that there are always packets pending in the FIFO 51 and
`available for transmission. i.e. T may be set to be a low value
`so that the network driver updates the network controller 42
`as infrequently as possible, but preferably T is not set to Such
`a low value that the network controller 42 runs out of
`packets in FIFO 51 before provided more packets.
`If Value P is not less than value T, then the driver executes
`block 78. This typically occurs if the network is congested
`or a large number of packets are provided to the network
`controller 42. If Value P is less than value T, then the
`network driver in block 80 provides an indication to con
`troller 42 that prepared packet frames are available for
`transmission, including the location and Size of the packet
`frames in host memory 38.
`In block 78, the driver determines if the value of variable
`X is equal to the number N frames to be transmitted. If it is
`not, the driver prepares the next packet frame in block 72. If
`X=N, the process ends. At a later time, either during the
`interrupt handler or during a Subsequent Send handler all the
`packets prepared by the driver may be sent to controller 42
`for transmission.
`After block 80, the driver in block 82 increments the value
`of Index P by the value of Index I. The driver then in block
`84 resets the value of Index I and then executes block 78.
`In FIG. 4, there is shown a proceSS eXecuting an interrupt
`from controller 42 in response to a packet being fetched for
`transmission, when a packet is received or when packets in
`Controller's 42 FIFO 51 have been transmitted. On an
`interrupt, the process in block 90 handles a receive packet
`using known techniques and Resets a local variable Y. Then
`in block 92, the proceSS determines by reading a status bit in
`memory 38 whether there is more packets in to be trans
`mitted by controller 42, e.g. whether all the data and
`information in FIFO 51 been transmitted. If the information
`has been transmitted, in block 94 transmit process is
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 6,865,152 B2
`
`4
`“cleaned up' by indicating to driver 41 that the information
`in FIFO has been transmitted and the transmit resources in
`controller 38 are made available. Then in block 96, variable
`Y is incremented.
`If there are not any transmits to be cleaned up, then in
`block 98 Index P is decremented by the value of variable Y.
`Then in step 100 the value of Index P is compared to the
`value of Index Y. If Index P is less than T, the controller 42
`is informed that prepared packets are available for transmis
`Sion in block 102. Then in block 104 Index Pis incremented
`by the value of Index I and the value of Index I is reset in
`block 106.
`If index P is not less than Index T in block 100 or after
`block 106 the routine in block 108 terminates by providing
`an indication to the operating System of the memory loca
`tions of the Sent packets that have been released.
`In the preceding description, various aspects of the
`present invention have been described. For purposes of
`explanation, Specific numbers, Systems and configurations
`were set forth in order to provide a thorough understanding
`of the present invention. However, it is apparent to one
`skilled in the art having the benefit of this disclosure that the
`present invention may be practiced without the Specific
`details. In other instances, well-known features were omitted
`or Simplified in order not to obscure the present invention.
`Embodiments of the present invention may be imple
`mented in hardware or Software, or a combination of both.
`However, embodiments of the invention may be imple
`mented as computer programs executing on programmable
`Systems comprising at least one processor, a data Storage
`System (including volatile and non-volatile memory and/or
`Storage elements), at least one input device, and at least one
`output device. Program code may be applied to input data to
`perform the functions described herein and generate output
`information. The output information may be applied to one
`or more output devices, in known fashion. For purposes of
`this application, a processing System includes any System
`that has a processor, Such as, for example, a digital Signal
`processor (DSP), a microcontroller, an application specific
`integrated circuit (ASIC), or a microprocessor.
`The programs may be implemented in a high level pro
`cedural or object oriented programming language to com
`municate with a processing System. The programs may also
`be implemented in assembly or machine language, if
`desired. In fact, the invention is not limited in Scope to any
`particular programming language. In any case, the language
`may be a compiled or interpreted language.
`The programs may be stored on a Storage media or device
`(e.g., hard disk drive, floppy disk drive, read only memory
`(ROM), CD-ROM device, flash memory device, digital
`versatile disk (DVD), or other storage device) readable by a
`general or Special purpose programmable processing
`System, for configuring and operating the processing System
`when the Storage media or device is read by the processing
`System to perform the procedures described herein. Embodi
`ments of the invention may also be considered to be imple
`mented as a machine-readable Storage medium, configured
`for use with a processing System, where the Storage medium
`So configured causes the processing System to operate in a
`Specific and predefined manner to perform the functions
`described herein.
`Another example of Such type of processing System is
`shown in FIG. 5, however, other systems may also be used
`and not all components of the System shown are required for
`the present invention. Sample System 12 may be used, for
`example, to execute the processing for embodiments of the
`
`9
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`US 6,865,152 B2
`
`15
`
`25
`
`S
`network driver System, in accordance with the present
`invention, Such as the embodiment described herein. Sample
`System 12 is representative of processing Systems based on
`the PENTIUM(RIII, PENTIUM(R) IV and CELERONTM
`microprocessors available from Intel Corporation, although
`other Systems (including personal computers (PCs) having
`other microprocessors, engineering WorkStations, other Set
`top boxes, and the like) and architectures may also be used.
`PENTIUM(RIII, PENTIUM(R) IV and CELERONTM are
`trademarks of Intel Corporation.
`FIG. 5 is a block diagram of a system 12 of an embodi
`ment of the present invention. The System 12 includes a
`processor 32 that processes data Signals. Processor 32 may
`be coupled to a processor buS 404 that transmits data Signals
`between processor 32 and other components in the System
`12.
`System 12 includes a memory 38. Memory 38 may store
`instructions and/or data represented by data Signals that may
`be executed by processor 32. The instructions and/or data
`may comprise code for performing any and/or all of the
`techniques of the present invention. Memory 38 may also
`contain additional Software and/or data (not shown). A cache
`memory 408 may reside inside processor 32 that stores data
`signals stored in memory 38.
`A bridge/memory controller 410 may be coupled to the
`processor bus 404 and memory 406. The bridge/memory
`controller 410 directs data signals between processor 32,
`memory 38, and other components in the System 12 and
`bridges the data Signals between proceSSorbus 404, memory
`38, and a first input/output (I/O) bus 412.
`In this embodiment, graphics controller 413 interfaces to
`a display device (not shown) for displaying images rendered
`or otherwise processed by the graphics controller 413 to a
`USC.
`35
`First I/O bus 412 may comprise a single bus or a com
`bination of multiple buses. First I/O bus 412 provides
`communication links between components in System 12. A
`network controller module 28 may be coupled to the first I/O
`buS 412. In Some embodiments, a display device controller
`416 may be coupled to the first I/O bus 412. The display
`device controller 416 allows coupling of a display device to
`System 12 and acts as an interface between a display device
`(not shown) and the System. The display device receives
`data Signals from processor 32 through display device
`controller 416 and displays information contained in the data
`Signals to a user of System 12.
`Referring to FIG. 6, Controller module 28 includes a
`network controller 42 coupled through a media connector 44
`to network 14. In one embodiment exemplary network
`controller 42 may be model number 82559 manufactured by
`Intel Corporation. Network controller 42, is preferably
`coupled on module 28 to a non-volatile memory Such as an
`EEPROM 46 and electrically programmable memory 48.
`EEPROM 46 holds static configurations of network control
`ler 42. Flash ROM 48 allows network controller 42 to
`operate independently of control circuit 30. Network 14 is
`typically a physical network medium such as a CAT5 or fiber
`cable that handles 10 or 100 or 1000 Base TX signals.
`Network controller 42 is preferably an Ethernet network
`controller with an integrated physical interface.
`Network controller 42 preferably contains an internal
`memory element, or external memory element hereafter
`referred to as cache 50 and a Direct Memory Access (DMA)
`controller 36. Module 42 also has an internal memory such
`as a FIFO 51 to Store incoming and outgoing packets or
`alternately may use cache 50 to function as a FIFO. DMA
`
`6
`controller 36 can perform direct memory access function
`ality to transfer multiple fragments of a packet from host
`memory 38 into its internal cache prior to transmission.
`Referring to FIG. 5, Network controller 42 receives
`commands and data from processor 32 through bus 412. Bus
`412 is preferably a PCI bus, but could be any bus that
`permits address and data to be transferred between module
`42 and controller 410. Data in host memory 38 is typically
`transferred to controller 42 using a DMA controller 36 or
`read/write instructions of microprocessor 42. Referring to
`FIG. 6, network controller 42 transmits and receives packet
`information 53 on line 14 through media connector 44.
`Network controller 42 on receipt of a packet or upon
`transmission of all packets in its FIFO 51 provides an
`interrupt to microprocessor 32.
`Referring to FIG. 5, a second I/O bus 420 may comprise
`a single buS or a combination of multiple buses. The Second
`I/O bus 420 provides communication links between com
`ponents in System 12. A data Storage device 422 may be
`coupled to the second I/O bus 420. A keyboard interface 424
`may be coupled to the second I/O bus 420. A user input
`interface 425 may be coupled to the second I/O bus 420. The
`user input interface may be coupled to a user input device,
`Such as a remote control, mouse, joystick, or trackball, for
`example, to provide input data to the computer System. AbuS
`bridge 428 couples first I/O bridge 412 to second I/O bridge
`420.
`Embodiments of the present invention are related to the
`use of the System 12 as a network driver. According to one
`embodiment, Such processing may be performed by the
`System 12 in response to processor 32 executing sequences
`of instructions in memory 404. Such instructions may be
`read into memory 404 from another computer-readable
`medium, Such as data Storage device 422, or from another
`Source via the network controller 414, for example. Execu
`tion of the Sequences of instructions causes processor 32 to
`execute the network driver according to embodiments of the
`present invention. In an alternative embodiment, hardware
`circuitry may be used in place of or in combination with
`Software instructions to implement embodiments of the
`present invention. Thus, the present invention is not limited
`to any specific combination of hardware circuitry and Soft
`WC.
`The elements of system 12 perform their conventional
`functions in a manner well-known in the art. In particular,
`data Storage device 422 may be used to provide long-term
`Storage for the executable instructions and data structures for
`embodiments of the network driver System in accordance
`with the present invention, whereas memory 406 is used to
`Store on a shorter term basis the executable instructions of
`embodiments of the network driver System in accordance
`with the present invention during execution by processor 32.
`Reference in the specification to “an embodiment,” “one
`embodiment,” “some embodiments,” or “other embodi
`ments' means that a particular feature, Structure, or charac
`teristic described in connection with the embodiments is
`included in at least Some embodiments, but not necessarily
`all embodiments, of the invention. The various appearances
`“an embodiment,” “one embodiment,” or “some embodi
`ments' are not necessarily all referring to the same embodi
`mentS.
`If the Specification States a component, feature, Structure,
`or characteristic “may”, “might', or “could be included,
`that particular component, feature, Structure, or characteris
`tic is not required to be included. If the Specification or claim
`refers to “a” or “an element, that does not mean there is
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`10
`
`CISCO 1032
`Cisco v. ChriMar
`
`

`

`US 6,865,152 B2
`
`1O
`
`15
`
`25
`
`7
`only one of the element. If the Specification or claims refer
`to “an additional element, that does not preclude there
`being more than one of the additional element.
`Those skilled in the art having the benefit of this disclo
`Sure will appreciate that many other variations from the
`foregoing description and drawings may be made within the
`Scope of the present invention. Indeed, the invention is not
`limited to the details described above. Rather, it is the
`following claims including any amendments thereto that
`define the Scope of the invention.
`What is claimed is:
`1. A method for transmitting packets in a network driver
`comprising:
`receiving an indication that a packet is available for
`transmission;
`monitoring a packet pending transmission Status of a
`network controller; and
`indicating to the network controller that the packet is
`available for transmission when the pending transmis
`Sion Status reaches a threshold value.
`2. The method as recited in claim 1 wherein the threshold
`value is a predetermined threshold value, and transmitting
`the packet onto a network when the indication is provided to
`network controller that the packet is available for transmis
`Sion.
`3. The method as recited in claim 2 further comprising
`Storing in a host memory the current number of packets
`pending for transmission by the network controller, and
`monitoring the packet pending transmission Status by read
`ing from host memory Said current number of packets
`pending.
`4. The method as recited in claim 3 further comprising:
`receiving a packet with the network controller from the
`network, and
`monitoring the packet pending transmission Status of the
`network controller in host memory when the network
`controller receives a packet from the network.
`5. The method as recited in claim 2 further comprising
`preparing packets for transmission by Storing in a host
`memory the location and length of the packet to be trans
`mitted.
`6. The method as recited in claim 2 further comprising
`delaying indicating to the network controller that the packet
`is available for transmission until the pending transmission
`status falls below the predetermined threshold value.
`7. The method as recited in claim 1 further comprising
`receiving the indication that the packet is available from an
`operating System.
`8. The method as recited in claim 1 further comprising
`50
`providing the packet as an Ethernet packet having a MAC
`header, a TCP/IP header and application data.
`9. An apparatus for transmitting packets comprising:
`A network controller to receive an indication that a packet
`is available for transmission; and
`A processor to monitor a packet pending transmission
`Status of the network controller, wherein Said processor
`provides an indication to the network controller that the
`packet is available for transmission in response to the
`pending transmission Status reaching a threshold value.
`10. The apparatus as recited in claim 9 wherein said
`processor indicates to the network controller when the
`number of packets remaining to be transmitted by the
`network controller is below a predetermined threshold, and
`wherein Said network controller transmits the packet onto a
`network when the indication is provided to network con
`troller that the packet is available for transmission.
`
`8
`11. The apparatus as recited in claim 9 further comprising
`a memory in communication with the processor for Storing
`the packet pending transmission Status of the network con
`troller and for Storing the packet.
`12. The apparatus as recited in claim 11 further compris
`ing a memory element disposed within the network control
`ler to Store the packet prior to transmission; and a DMA
`controller to transfer packets from the memory element to
`the network controller.
`13. The apparatus as recited in claim 12 wherein the
`processor is operative to monitor the packet pending trans
`mission Status of the network controller when a packet is
`received from the network media.
`14. The apparatus as recited in claim 12 wherein the
`processor is operative to cause the network controller to
`Store in a buffer, packets to be transmitted and to read the
`transmission Status of the network controller after the net
`work controller has transmitted all its packets.
`15. The apparatus as recited in claim 9 wherein the
`threshold values range from 1 to 4.
`16. An apparatus for transmitting packets comprising:
`Means for receiving an indication that a packet is avail
`able for transmission;
`Means for monitoring a packet pending transmission
`Status of a network controller; and
`Means for indicating to the network controller that the
`packet is available for transmission in response to the
`pending transmission Status falling below a predeter
`mined threshold value.
`17. The apparatus as recited in claim 16 further compris
`ing means for transmitting the packet onto a network when
`the indication is provided to network controller that the
`packet is available for transmission.
`18. The apparatus as recited in claim 17 further compris
`ing means for Storing the packet prior to transmission, and
`means for transferring packets form the Storage means to the
`network controller.
`19. A System for transferring packets comprising:
`a. a computer having
`i. a processor coupled to a host memory and a bus,
`ii. a network controller coupled to the bus, Said con
`troller having a driver operative to receive an indi
`cation that a packet is available for transmission; Said
`processor operative to monitor a packet pending
`transmission Status of a network controller and pro
`vide an indication to the network controller that the
`packet is available for transmission in response to the
`pending transmission Status reaching a threshold
`value; and
`b. a network media to which said packets are transmitted
`when the indication is provided to network controller
`that the packet is available for transmission.
`20. The system as recited in claim 19 further comprising
`a host memory operative to Store the current number of
`packets pending for transmission by the network controller;
`and Said processor monitoring the packet pending transmis
`Sion Status by reading from host memory Said current
`number of packets pending.
`21. The s