(12) United States Patent
`Shiomoto
`
`USOO62894.85B1
`US 6,289,485 B1
`(10) Patent No.:
`Sep. 11, 2001
`(45) Date of Patent:
`
`(54) METHOD FOR ADDING AND ENCODING
`ERROR CORRECTING CODES AND ITS
`DEVICE AND METHOD FOR
`TRANSMITTING DATA HAVING ERROR
`CORRECTING CODESADDED
`
`(75) Inventor: Shoji Shiomoto, Tokyo (JP)
`(73) Assignee: Sony Corporation (JP)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/177,692
`(22) Filed:
`Oct. 22, 1998
`(30)
`Foreign Application Priority Data
`Oct. 24, 1997
`(JP) ................................................... 9-292986
`(51) Int. Cl." .................................................... H03M 13700
`(52) U.S. Cl. .............................................................. 714/779
`(58) Field of Search ..................................... 714/752, 779,
`714/746; 375/240.03, 243, 240.16; 382/232,
`240
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,748,787 * 5/1998 Sugiyama ............................. 382/240
`5,781,561 * 7/1998 Machida et al. ..
`... 714/752
`5,881,070
`3/1999 Hoshi ................................... 714/752
`OTHER PUBLICATIONS
`Wehnes et al., Fast LOSSleSS Image Compression, IEEE, pp.
`145-148, Aug. 1996.*
`Whoi-Yulet al. Hierarchy Embedded Differential Image for
`Progressive Transmission Using LOSsleSS Compression,
`IEEE, p. 1 to 13, Feb. 1995.*
`
`Luttrell, S. P., Hierarchical Vector Quantisation, IEEE, pp.
`405-413, Dec. 1989.*
`Cuenca et al., An error concealment Scheme for MPEG-2
`video transmission over ATM-based networks, IEEE 1997.*
`Cuenca et al., dynamic error concealment technique for the
`transmission of hierarchical encoded MPEG-2 video over
`ATM networks, IEEE, 1997.*
`Cuenca et al., Packing scheme for layered coding MPEG-2
`Video transmission over ATM based networks, IEEE,
`1997.*
`Pancha et al., Mpeg coding for variable bit rate Video
`transmission, IEEE 1994.*
`* cited by examiner
`
`Primary Examiner Albert Decady
`Assistant Examiner. Shelly A. Chase
`(74) Attorney, Agent, or Firm-Lerner, David, Littenberg,
`Krumholz & Mentlik, LLP
`(57)
`ABSTRACT
`A method for encoding error correcting codes to generate
`plural coded data having different error correction ability
`according to significance. An error correcting code having
`different code length is added to a fixed length of input data
`according to the significance of the input data (S14). The
`error correcting codes added which have different error
`correction ability corresponding to its code length are
`encoded to generate coded data having different packet
`length according to the code length of the error correcting
`code. Thus, plural coded data (S15A and S15B) which have
`different error correction ability according to Significance
`can be generated. Thereby, even if a quality of transmission
`System deteriorates when the above coded data is
`transmitted, the coded data having high error correction
`ability can be Surely decoded.
`
`26 Claims, 9 Drawing Sheets
`
`10 IMAGE DATA ENCODING DEVICE
`
`11 HIERARCHICALLY-ENCODING BLOCK
`- - - - - -
`llA
`2
`
`
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`S14
`
`3
`
`S15A
`IERARCHICAL ERROR
`CORRECTING
`CODE ENCODER
`
`S1 5
`
`14
`INTERLEAWE
`CIRCUIT
`
`
`
`15
`
`INNER CODE
`ENCODING CIRCUIT
`
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`U.S. Patent
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`Sep. 11, 2001
`
`Sheet 1 of 9
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`US 6,289,485 B1
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`1 IMAGE DATA DECODING DEVICE
`
`S1
`
`
`
`
`
`2
`SOURCE
`ENCODING
`CIRCUIT
`
`S2
`
`3
`OUTER CODE
`ENCODING
`CIRCUIT
`
`
`
`S3
`
`4
`
`S4
`
`INTERLEAWE
`CIRCUIT
`
`
`
`INNER CODE
`ENCODING
`CIRCUIT
`
`FIG. 1 (PRIOR ART)
`
`PARITY
`me PAYLOAD
`PAYLOAD
`N-- N--
`k BYTES
`V. k. BYTES
`n BYTES
`
`FIG. 2(RELATED ART)
`
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`U.S. Patent
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`Sep. 11, 2001
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`Sheet 2 of 9
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`US 6,289,485 B1
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`ZIS
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`
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`8000 HANNI
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`US. Patent
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`Sep. 11, 2001
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`Sheet 3 0f 9
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`US 6,289,485 B1
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`U.S. Patent
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`Sep. 11, 2001
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`Sheet 4 of 9
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`US 6,289,485 B1
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`BASE LAYER CODE STRING 1 PARITY
`BASE LAYER CODE STRING 2 PARITY
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`
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`|
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`L+1b BYTES
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`FIG. 5A
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`REINFORCED LAYER CODE STRING 1 PARITY
`|REINFORCED LAYER CODE STRING 2 PARITY
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`He-on-Ham---ee
`L+1e BYTES
`
`FIG. 5B
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`US. Patent
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`Sep.11,2001
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`Sheets 0f9
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`US 6,289,485 B1
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`US. Patent
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`Sep.11,2001
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`US 6,289,485 B1
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`U.S. Patent
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`Sep. 11, 2001
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`Sheet 7 of 9
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`US 6,289,485 B1
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`h BYTES
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`PART OF BASE PARITY PARTOERENEORGEP
`LAYER CODE STRING
`LAYER CODE STRING
`PART OF REINFORCED
`YERC6ESERPARITY
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`BASEAYER PARITY PART OFREINFORED
`CODE STRING
`LAYER CODE STRING
`PART OFREINFORCED PARITY
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`LAYER CODE STRING
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`
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`US. Patent
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`Sheet8 0f9
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`US 6,289,485 B1
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`U.S. Patent
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`Sep. 11, 2001
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`Sheet 9 of 9
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`US 6,289,485 B1
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`

`1
`METHOD FOR ADDING AND ENCODING
`ERROR CORRECTING CODES AND ITS
`DEVICE AND METHOD FOR
`TRANSMITTING DATA HAVING ERROR
`CORRECTING CODESADDED
`
`FIELD OF THE INVENTION
`The present invention relates to a method for encoding
`error correcting codes and its device and method for trans
`mitting data having error correcting codes added, and is
`applicable to a digital Satellite broadcasting System, for
`example.
`DESCRIPTION OF THE RELATED ART
`Heretofore, this type of digital Satellite broadcasting SyS
`tem compressively encodes image data of plural programs
`using an MPEG (Moving Picture Experts Group)2 system as
`a compression-encoding System for image data, and then
`multiplexes them into one bit Stream for transmission. At
`this time, this digital Satellite broadcasting System adds error
`correcting codes to compressively-coded image data and
`then transmits it on a transmitting Side, and decodes the error
`correcting codes on a receiving Side to correct errors gen
`erated in the process of transmission. Thereby, the digital
`Satellite broadcasting System can properly restore a trans
`mission Signal on the receiving Side even if the carrier-to
`noise ratio (C/N ratio) of the transmission signal deteriorates
`owing-to rainfall or the like, when in transmission.
`AS shown in FIG. 1, a conventional image data encoding
`device 1 used in Such digital Satellite broadcasting System is
`composed of a Source encoding circuit 2, an outer code
`encoding circuit 3, an interleave circuit 4 and an inner code
`encoding circuit 5. The image data encoding device 1 inputs
`input image data S1 Supplied from a hard disk or the like to
`the Source encoding circuit 2.
`The Source encoding circuit 2 performs high efficiency
`compression coding to the input image data S1 using the
`MPEG2 system, and feeds thus obtained source coded data
`S2 to the outer code encoding circuit 3. The outer code
`encoding circuit 3, as shown in FIG. 2, performs encoding
`of error correction codes Such as reed-Solomon (RS) encod
`ing with respect to each of Successive payloads having fixed
`length (k-bytes) forming the Source coded data S2 to add a
`parity bit of fixed length to each payload. Then, the outer
`code encoding circuit 3 feeds outer code coded data S3 in
`which the parity bit is added to this payload, formed by
`Successive parity added data of fixed length (n-bytes), to the
`interleave circuit 4.
`Hereinafter, the outer code encoding circuit 3 represents
`the relationship between the number of bytes of payloads to
`be inputted and the number of bytes of the parity added data
`as (n, k). In this case, it is assumed that RS encoding of (n,
`k) form is executed. In case of the MPEG2 system, the outer
`code encoding circuit 3 performs RS encoding to each
`payload of 188 bytes and adding 16 bytes of parity bit
`thereto respectively. Thus obtained parity added data is
`outputted in data unit of 204 bytes. In this case, the outer
`code encoding circuit 3 can be represented that has executed
`RS encoding in (204, 188) form.
`The interleave circuit 4 changes write Sequence when the
`outer code coded data S3 is written into a built-in memory
`from read Sequence when that is read from the above
`memory and rearranging the data of the Outer code coded
`data S3, and Supplies this as interleave data S4 to the inner
`code encoding circuit 5. Accordingly, in the digital Satellite
`broadcasting System using Such image data encoding device
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`1, even if errors concentrated in during transmission
`generate, So-called burst errors generate, the burst errors can
`be distributed by performing deinterleave on the receiving
`Side, thus error correction ability can be reinforced.
`The inner code encoding circuit 5 performs convolution
`encoding to the interleave data S4 and further reinforcing the
`error correction ability, and feeds this as inner code coded
`data S5 to the outside. This inner code coded data S5 is
`converted into a transmission signal by Subjected to digital
`modulation by a modulator which is not shown, provided
`after the image data encoding device 1, or the like, before
`transmitted to the receiving Side. According to the above, in
`the digital Satellite broadcasting System, Since encoding of
`error correcting codes Such as the RS encoding or the
`convolution encoding or the like is performed to the Source
`coded data S2 before transmission, even if the C/N ratio of
`the transmission signal deteriorates, error correcting can be
`performed on decoding Side, provided that the errors gen
`erated in the above transmission signal is less than a pre
`Scribed threshold value. Thereby, the original input image
`data S1 can be restored.
`By the way, in the digital Satellite broadcasting System
`using the image data encoding device 1 having the above
`configuration, Since payload length and parity length are
`fixed, it has fixed error correction ability. Thus, in Such
`digital Satellite broadcasting System, if many errors generate
`during transmission and the C/N ratio lowers below the
`prescribed threshold value, a problem Such that received
`transmission signals cannot be properly decoded has been
`occurred by unfortunately exceeding the error correction
`ability.
`
`SUMMARY OF THE INVENTION
`In View of the foregoing, an object of this invention is to
`provide a method for adding and encoding error correcting
`codes and its device and a method for transmitting data
`having error correcting codes added, capable of improving
`the reliability of transmitting and receiving with a simple
`configuration.
`The foregoing object and other objects of the invention
`have been achieved by the provision of a method for adding
`and encoding error correcting codes and its device and a
`method for transmitting data having error correcting codes
`added, in which, in a method for adding and encoding
`prescribed error correcting codes to input data, an error
`correcting code of different code length is added to each
`fixed length of the input data according to the Significance of
`the input data. And the error correcting codes having dif
`ferent error correction ability corresponding to the code
`length of error correcting code are encoded. Thus, coded
`data having different packet length according to the code
`length of error correcting code is generated.
`AS described above, an error correcting code having
`different code length is added to a fixed length of input data
`according to the significance of the input data. The error
`correcting codes added which have different error correction
`ability corresponding to its code length are encoded to
`generate coded data having different packet length according
`to the code length of the error correcting code. Thus, plural
`coded data having different error correction ability accord
`ing to significance can be generated.
`The nature, principle and utility of the invention will
`become more apparent from the following detailed descrip
`tion when read in conjunction with the accompanying draw
`ings in which like parts are designated by like reference
`numerals or characters.
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`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the accompanying drawings:
`FIG. 1 is a block diagram Showing the configuration of a
`conventional image data encoding device;
`FIG. 2 is a Schematic diagram Showing the State of adding
`of error correcting code;
`FIG. 3 is a block diagram showing the configuration of an
`image data encoding device according to a first embodiment
`of the present invention;
`FIGS. 4A to 4C are schematic diagrams showing the state
`of multiplexing,
`FIGS. 5A and 5B are schematic diagrams showing the
`State of interleave processing,
`FIG. 6 is a block diagram showing the configuration of an
`image data decoding device according to the first embodi
`ment,
`FIG. 7 is a block diagram showing the configuration of an
`image data encoding device according to a Second embodi
`ment,
`FIGS. 8A and 8B are schematic diagrams showing the
`State of interleave processing,
`FIG. 9 is a Schematic diagram showing a data structure of
`frame header; and
`FIG. 10 is a block diagram showing the configuration of
`an image data decoding device according to the Second
`embodiment.
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENT
`
`4
`base layer code Strings corresponding to a payload shown in
`FIG. 2, as shown in FIGS. 4A to 4C. At the same time, the
`multiplexer 12 packetizes the reinforced layer coded data
`S13 (FIG. 4B) by fixed data length L and generating plural
`reinforced layer code Strings corresponding to the aforemen
`tioned payload. The multiplexer 12 Superimposes a code
`String identification flag on each of these base layer code
`String and reinforced layer code String and multiplexes them
`into one System of Stream. Thus obtained multiplexed data
`S14 (FIG. 4C) is supplied to the hierarchical error correcting
`code encoder 13.
`The hierarchical error correcting code encoder 13 (FIG.3)
`adds a parity bit having different data length to each of the
`base layer code String and the reinforced layer code String
`forming the multiplexed data S14 for addition of error
`correcting codes corresponding to the above parity bits.
`Specifically, the hierarchical error correcting code encoder
`13 first detects a partition of code Strings forming the
`multiplexed data S14 based on the code string identification
`flags Superimposed on the base layer code String and the
`reinforced layer code String, and then identifies whether the
`above code String is base layer code String or reinforced
`layer code String. In this case, in the hierarchical error
`correcting code encoder 13, Since base layer code Strings and
`reinforced layer code Strings have fixed length, So that it can
`be more easily identified than the case of variable length.
`Then, the hierarchical error correcting code encoder 13
`adds a parity bit of 1b bytes to each base layer code String
`of L bytes to perform RS encoding in (L+1b, L) form of
`output L-1b bytes to input L bytes. Thus obtained base layer
`coded data S15A is supplied to the interleave circuit 14 as
`output data of hierarchically-coded error correcting code
`S15. At the same time, the hierarchical error correcting code
`encoder 13 adds a parity bit of le bytes which is Smaller than
`1b byte to each reinforced layer code string of L bytes to
`perform RS encoding in (L+1e, L) form. Thus obtained
`reinforced layer coded data S15B is supplied to the inter
`leave circuit 14 as output data of hierarchically coded error
`correcting code S15.
`In this case, in the hierarchical error correcting code
`encoder 13, a parity bit having a longer parity length than a
`reinforced code String is added to a base layer code String
`equal to the reinforced code String in data length. Therefore,
`base layer parity added data in which parity bits are added
`to base layer code Strings has higher error correction ability
`than reinforced layer parity added data in which parity bits
`are added to reinforced layer code Strings. The hierarchical
`error correcting code encoder 13 can adaptively Switch error
`correction ability according to the Significance of data as the
`above.
`The interleave circuit 14 identifies about the base layer
`parity added data forming the base layer coded data S15A
`and the reinforced layer parity added data forming the
`reinforced layer coded data S15B. These base layer parity
`added data and reinforced layer parity added data are
`Sequentially written into different memories respectively.
`Then, the interleave circuit 14 rearranges the data by making
`read Sequence differ from write Sequence at the time of
`reading-out of data, and Supplies this to the inner code
`encoding circuit 15 as interleave data S16.
`That is, as shown in FIG. 5A, the interleave circuit 14
`Sequentially writes the base layer parity added data one for
`line in a region from a first line to an m-th line with respect
`to a rectangular region on the memory formed by L+1b bytes
`in line direction and (m) bytes in column direction. Then, the
`interleave circuit 14 adds frame headers to these (m) base
`layer parity added data written, So that base layer transmis
`Sion frames are generated.
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`Preferred embodiments of this invention will be described
`with reference to the accompanying drawings:
`(1) First Embodiment
`Referring to FIG. 3 generally shows an image data
`encoding device 10. The device 10 is composed of a
`hierarchically encoding block 11, a multiplexer 12, a hier
`archical error correcting code encoder 13, an interleave
`circuit 14 and an inner code encoding circuit 15. The image
`data encoding device 10 inputs HDTV (High Definition
`Television) image data S10 Supplied from a hard disk or the
`like into the hierarchically-encoding block 11.
`The hierarchically-encoding block 11 has a base layer
`encoder 11A and a reinforced layer encoder 11B. The HDTV
`45
`image data S10 is supplied to the base layer encoder 11A and
`the reinforced layer encoder 11B to be divided into two
`image data having different resolutions for respective encod
`ing (so-called hierarchical encoding).
`The base layer encoder 11A thins out desired picture
`elements from among picture elements of the HDTV image
`data S10 and generating SDTV (Standard Definition
`Television) image data. The base layer encoder 11A com
`pressively codes this SDTV image data by the MPEG2
`system. Thus obtained base layer coded data S11 is supplied
`55
`to the multiplexer 12. Furthermore, the base layer encoder
`11 A performs interpolating filter processing to the SDTV
`image data and Supplying thus obtained SDTV image inter
`polated data S12 to the reinforced layer encoder 11B.
`The reinforced layer encoder 11B obtains difference
`between the HDTV image data S10 and the SDTV image
`interpolated data S12 to generate difference data. The rein
`forced layer encoder 12 compressively encodes this differ
`ence data and Supplying thus obtained reinforced layer
`coded data S13 to the multiplexer 12.
`The multiplexer 12 packetizes the base layer coded data
`S11 (FIG. 4A) by fixed data length L and generating plural
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`S
`Similarly, as shown in FIG. 5B, the interleave circuit 14
`Sequentially writes the reinforced layer parity added data to
`a rectangular region on the memory formed by L+1e bytes
`in line direction and (n) bytes in column direction. Then, the
`interleave circuit 14 adds a frame header to each of (n)
`reinforced layer parity added data thus written to generate
`reinforced layer transmission frames. A Sync bit String
`showing the head of frame and a frame identification flag for
`identifying whether the above frame is base layer transmis
`Sion frame or reinforced layer transmission frame are
`inserted into these frame headers.
`The interleave circuit 14 then reads out the base layer
`transmission frames and the reinforced layer transmission
`frames written in two different memories respectively in the
`order shown by arrows in FIGS. 5A and 5B to rearrange the
`data respectively, and Supplies these as interleave data S16
`to the inner code encoding circuit 15. The inner code
`encoding circuit 15 convolution-codes the interleave data
`S16 to further reinforce the error correction ability, and
`supplies thus obtained inner code coded data S17 to the
`outside. This inner code coded data S17 is subjected to
`digital modulation or the like by a modulator (not shown)
`provided after the image data encoding device 10 and
`converted into a transmission Signal, and then it is transmit
`ted to the receiving Side.
`Thus transmitted transmission Signal is demodulated by a
`demodulator (not shown) on the receiving side, and then the
`demodulated Signal is fed to an image data decoding device
`20 provided after the above demodulator, such as shown in
`FIG. 6. The image data decoding device 20 is composed of
`an inner decoding circuit 21, a deinterleave circuit 22, a
`hierarchical error correcting code decoder 23, a multiplex
`Separator 24 and a hierarchically-decoding block 25. The
`demodulated received data S30 is fed to the inner code
`decoding circuit 21.
`The inner code decoding circuit 21 performs error cor
`recting of the received data S30 by, for example, a Viterbi
`decoding method, and Supplies thus obtained inner code
`decoded data S31 to the deinterleave circuit 22. The deinter
`leave circuit 22 detects a Sync bit String from the frame
`header inserted in the inner code decoded data S31 to
`identify the head of the base layer transmission frame and
`the head of the reinforced layer transmission frame, and
`Sequentially writes these base layer transmission frame and
`reinforced layer transmission frame to different memories
`respectively. Then, the deinterleave circuit 22 rearranges the
`data by reading it out in such order different from the write
`Sequence to return them in the original order. Thus obtained
`base layer transmission frame S32A and reinforced layer
`transmission frame S32B are supplied to the hierarchical
`error correcting code decoder 23.
`The hierarchical error correcting decoder 23 decodes the
`frame identification flags inserted in the frame headers of the
`base layer transmission frame S32A and the reinforced layer
`transmission frame S32B to discriminate whether to be the
`base layer transmission frame S32A or the reinforced layer
`transmission frame S32B. The hierarchical error correcting
`code decoder 23 performs the error correcting of the base
`layer transmission frame S32A and the reinforced layer
`transmission frame S32B based on this discriminated result
`and generating error correcting code decoded data S33, and
`Supplies this to the multiplex Separator 24.
`The multiplex Separator 24 Separates the error correcting
`code decoded data S33 to generate base layer coded data S34
`and reinforced layer coded data S35. The base layer coded
`data S34 is supplied to the base layer decoder 25A of the
`hierarchically-decoding block 25. On the other hand, the
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`reinforced layer coded data S35 is supplied to the reinforced
`layer decoder 25B of the hierarchically-decoding block 25.
`The base layer decoder 25A extensionally decodes the
`base layer coded data S34 and Supplying thus obtained
`SDTV image data S36 to the outside. In addition, the base
`layer decoder 25A performs interpolating filter processing to
`the SDTV image data S36, and Supplies thus obtained
`interpolated SDTV image data S37 to the reinforced layer
`decoder 25B.
`The reinforced layer decoder 25B generates difference
`data by extensionally decoding the reinforced layer coded
`data S35. The reinforced layer decoder 25B adds this
`difference data to the interpolated SDTV image data S37 to
`restore HDTV image data S38, and Supplies it to the outside.
`Such digital Satellite broadcasting System Selects desired
`one of the SDTV image data S36 and the HDTV image data
`S38 according to the resolution of a television monitor (not
`shown) or the like, and displaying on the above television
`monitor. Accordingly, even in the case where the SDTV
`image data S36 in which only the base layer coded data S34
`is extensionally decoded is Selected, this digital Satellite
`broadcasting System can obtain the quality of image as well
`as the current broadcasting. Besides, in the case where the
`HDTV image data S38 in which both of the base layer coded
`data S34 and the reinforced layer coded data S35 are
`extensionally decoded is Selected, the quality of image
`higher than the current broadcasting can be obtained
`(hereinafter, this is referred to as space Scalability function).
`According to the above configuration, each data of the
`ba.se layer transmission frame and the reinforced layer
`transmission frame formed in the interleave circuit 14 is
`Supplied to transmission System via the inner code encoding
`circuit 15 at prescribed timing. That is, each data of the base
`layer transmission frame and the reinforced layer transmis
`Sion frame is transmitted in the transmission System.
`Accordingly, for example, if C/N at receiving Side dete
`riorates owing to the influence of rainfall or the like, the base
`layer coded data S15Ahaving high error correction ability is
`Surely decoded at least.
`Thus, according to the above configuration, the Significant
`coded data (base layer coded data S15A) can be transmitted
`while improving its error correction ability. Thereby, decod
`ing on the receiving Side can be ensured.
`(2) Second Embodiment
`FIG. 7 in which the same reference number is added to the
`corresponding part of FIG. 3 shows an image data encoding
`device 30 according to a second embodiment. This device 30
`is configured similarly to the image data encoding device 10
`according to the first embodiment except for the configura
`tion of an interleave circuit 31.
`The interleave circuit 31 sequentially writes the base layer
`parity added data forming the base layer coded data S15A
`and the reinforced layer parity added data forming the
`reinforced layer coded data S15B into one memory in
`desired order. When reading data out, the interleave circuit
`31 rearranges the data by reading the data out in different
`order from write Sequence, and Supplies this to the inner
`code encoding circuit 15 as interleave data S50.
`That is, as shown in FIG. 8A, the interleave circuit 31
`Sequentially writes in desired number of the base layer parity
`added data and the reinforced layer parity added data in
`desired order from the top of a first line to a rectangular
`region on a memory formed by (h) bytes in line direction and
`(k) bytes in column direction. In this case, any inconve
`nience does not occur even if write to the rectangular region
`on the memory is started from the middle of the parity-added
`data or even if write is stopped in the middle of the
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`parity-added data. When write is stopped, the interleave
`circuit 31 generates transmission frames by adding frame
`headers to plural base layer parity-added data and reinforced
`layer parity-added data written-in, as shown in FIG. 8B.
`As shown in FIG. 9, a sync bit string showing the head of
`the transmission frame, the number of bytes from the head
`of the transmission frame until the head of the parity-added
`data first appears, and the number of longitudinal and lateral
`bytes of the transmission frame are Sequentially inserted into
`this frame header. In this frame header, the number of the
`parity-added data included in the transmission frame is
`further inserted in the specified width of the number of bits,
`and parity-added data identification flags for identifying
`whether each parity-added data forming transmission frame
`is the base layer parity-added data or the reinforced layer
`parity added-data from the top in order are inserted by the
`number of parity-added data.
`Since each data forming Such frame header is more
`Significant data than a base layer code String or a reinforced
`layer code String in the transmission frame, it is desired that
`error correction ability is reinforced more than the case
`where parity bits are added to these base layer code String
`and reinforced layer code String.
`The interleave circuit 31 rearranges data by reading out
`the transmission frames written in the memory in Such order
`as shown by arrows in FIGS. 8A and 8B, and Supplies this
`to the inner code encoding circuit 15 as interleave data S50.
`The inner code encoding circuit 15 further reinforces error
`correction ability by convolution-encoding the interleave
`data S50, and Supplies thus obtained inner code coded data
`S51 to the outside.
`On the other hand, in the decoding Side of the Second
`embodiment, as shown in FIG. 10 in which the same
`reference numeral is added to the corresponding part of FIG.
`6, an image data decoding device 40 is provided. The above
`image data decoding device 40 has a Similar configuration as
`the image data decoding device 20 according to the first
`embodiment except for the configuration of a deinterleave
`circuit 41.
`The inner code decoding circuit 21 performs error cor
`rection of received data S60 and supplying thus obtained
`decoded inner code data S61 to the deinterleave circuit 41.
`The deinterleave circuit 41 identifies the head of transmis
`Sion frames by detecting a Sync bit String in a frame header
`inserted into the decoded inner code data S61, and writes the
`above transmission frame in a memory.
`If finishing the write-in, the deinterleave circuit 41 reads
`the frame headers out in different order from write Sequence
`to detect the position of each parity-added data after check
`ing the number of parity-added data forming the transmis
`Sion frame, and obtains identification information for iden
`tifying whether the detected parity-added data is the base
`layer parity-added data or the reinforced layer parity-added
`data. Then, the deinterleave circuit 41 reads out the parity
`added data of the transmission frame in a different order
`from the write Sequence based on this identification
`information, So that data is rearranged and restored in the
`original Sequence. Thus obtained base layer transmission
`frame S62A and reinforced layer transmission frame S62B
`are Supplied to the hierarchical error correcting code decoder
`23.
`According to the above configuration, each data of the
`transmission frame formed in the interleave circuit 31 is
`Supplied to the transmission System via the inner code
`encoding circuit 15 at prescribed timing. That is, each data
`of the transmission frame is transmitted in the transmission
`System.
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`Accordingly, for example, if C/N at receiving Side dete
`riorates owing to the influence of -rainfall or the like, the
`base layer coded data S15A having high error correction
`ability is Surely decoded at least, in the transmission frame.
`Thus, according to the above configuration, the Significant
`coded data (base layer coded data