throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`John Jianhong Zhu et al.
`In re Patent of:
`9,024,418 Attorney Docket No.: 39521-0045IP1
`U.S. Patent No.:
`May 5, 2015
`
`Issue Date:
`Appl. Serial No.: 13/829,864
`
`Filing Date:
`March 14, 2013
`
`Title:
`LOCAL INTERCONNECT STRUCTURES FOR
`HIGH DENSITY
`
`
`
`DECLARATION OF DAVID KUAN-YU LIU, PH.D.
`
`1. My name is Dr. David Kuan-Yu Liu. I understand that I am
`
`submitting a declaration in connection with Inter Partes review (“IPR”)
`
`proceedings before the United States Patent and Trademark Office for U.S. Patent
`
`Number 9,024,418 (“’418 Patent”).
`
`2.
`
`I have been retained by Fish & Richardson P.C. (“Counsel”), on
`
`behalf of Apple Inc. to offer technical opinions with respect to the ’418 Patent and
`
`the references cited in this IPR. My compensation is not based on the outcome of
`
`my opinions.
`
`3. My curriculum vitae (“CV”) is provided as Exhibit 1004.
`
`4.
`
`I am not a lawyer. As set forth in my CV, I hold M.S. and Ph.D.
`
`degrees in Electrical Engineering from Stanford University and have 20 years of
`
`experience as an engineer and engineering manager/director of Complementary
`
`Metal Oxide Semiconductor (CMOS) technology development. I hold over 90
`
`1
`
`APPLE 1003
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`U.S. patents, a large number of which are directed to CMOS processes and
`
`semiconductor technology.
`
`5.
`
`The vast majority of my patents are in the area of CMOS high density
`
`circuit and memory architecture. As such, I am intimately familiar with the
`
`concept of having a compact layout of transistors to implement a library of logic
`
`gate functions. For example, US Patent Nos. 6,693,027 and 8,988,103 relate to the
`
`use of novel device physics to facilitate compact and high performance logic gate
`
`functions.
`
`6.
`
`I have also authored several technical papers that have been published
`
`in well-respected, peer-reviewed journals, such as the IEEE Electron Device
`
`Letters, the IEEE Journal of Solid-State Circuits, and the IEEE Transactions on
`
`Electron Devices. As an example, I worked on a new conductivity-modulated
`
`Power MOSFET that features a buried minority-carrier injector to enhance the
`
`current conduction capability of the Power MOSFET. This work was published in
`
`the IEEE Transactions on Electron Devices.
`
`7.
`
`During my career, I have worked at some of the leading technology
`
`companies in the world, such as Texas Instruments, Advanced Micro Devices,
`
`Altera Corporation (now a subsidiary of Intel Corp.), and Xilinx. At these
`
`2
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`companies, my work focused on various aspects of CMOS and semiconductor
`
`technology.
`
`8.
`
`The following provides a chronological highlight of my experience as
`
`discussed above and in my CV. From 1989 to 1992, I was a member of technical
`
`staff at Texas Instruments, Inc. At Texas Instruments, my job responsibilities at
`
`Texas Instruments also included process integration, device modeling, high-
`
`voltage CMOS process integration, and investigating novel source-side injection
`
`mechanisms for Flash EPROM channel hot-electron programming.
`
`9.
`
`From 1992 to 1995, I was a member of the technical staff at Advanced
`
`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
`
`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
`
`technology. My job responsibilities at AMD also included process integration,
`
`device modeling, and development of triple-well process technology for
`
`accommodate x-decoder transistors and high voltage transistors for negative gate
`
`erase operation. While at AMD, I was awarded a Spotlight Award for developing
`
`a method of manufacturing a self-aligned source (SAS) etch for a NOR flash
`
`memory.
`
`10.
`
`I spent the next five years of my career in managerial and director
`
`roles at several California-based semiconductor companies. I was responsible for
`
`3
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`increasing yield and for leading teams of engineers working to develop next-
`
`generation memory devices.
`
`11.
`
`In 2000, I co-founded Progressant Technologies in Fremont,
`
`California. Progressant Technologies developed IP for negative differential
`
`resistance transistor technology and was eventually acquired by Synopsys, Inc.
`
`12. From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
`
`where I was responsible for developing nonvolatile memory process technology
`
`for flash and CPLD product applications, as well as advanced CMOS process
`
`technology (specifically 75nm CMOS technology node, a half node version
`
`between 90nm and 65nm).
`
`13. From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
`
`Products where I was responsible for developing Embedded Non-volatile Memory
`
`process technology for Power Management product applications.
`
`14. Since 2007, I have served as a technical consultant where I have
`
`provided expert advice regarding Flash memory technology, CMOS process
`
`technology, and semiconductor device physics.
`
`15.
`
`I am not now, and have never been an employee of the Petitioner.
`
`16.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the fields of
`
`4
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`semiconductor design and processes; and my experience in working with others
`
`involved in those fields. I have reviewed the ’418 Patent, including the claims of
`
`the patent in view of the specification and the file history. In addition, I have
`
`reviewed the following documents:
`
` U.S. Patent No. 9,024,418 (“’418 patent” or “Ex. 1001”), and its
`
`accompanying prosecution history (“’418 Prosecution History” or
`
`“Ex. 1002”)
`
` U.S. Patent No. 8,618,607 (“Rashed 607” or “Ex. 1005”)
`
` U.S. Patent No. 9,123,565 (“Lu” or “Ex. 1006”)
`
` Bram Nauta, A CMOS Transconductance-C Filter Technique for Very
`
`High Frequencies, 27 2 IEEE J. Solid-State Cir., 142-153, Feb. 1992
`
`(“Nauta” or “Ex. 1007”)
`
` Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2001
`
`(“Razavi” or “Ex. 1008”)
`
` Chenming Hu, Modern Semiconductor Devices for Integrated
`
`Circuits, 195-258, 2010 (“Hu” or “Ex. 1009”)
`
` U.S. Patent No. 8,110,854 (“Becker” or “Ex. 1012”)
`
` U.S. Provisional Patent Application 61/747,751 ("Lu Provisional" or
`
`"Ex. 1011")
`
`5
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
` U.S. Patent No. 8,741,763 (“Ma” or “Ex. 1013”)
`
`17. Counsel has informed me that I should consider these materials
`
`through the lens of one of ordinary skill in the art related to the ’418 patent at the
`
`time of the earliest effective priority date (“Critical Date”) of the ’418 Patent, and
`
`I have done so during my review of these materials. My understanding is that the
`
`Critical Date in this case is March 14, 2013, the filing date of U.S. Application No.
`
`13/829,864, from which the ’418 patent issued.
`
`18.
`
`I am familiar with the knowledge and capabilities of one of ordinary
`
`skill in the areas mentioned above, notably including the areas of semiconductors
`
`and semiconductor processes. My experience working in industry has allowed me
`
`to become directly and personally familiar with the level of skill of individuals and
`
`the general state of the art in these areas. Unless otherwise stated, my testimony
`
`below refers to the knowledge of one of ordinary skill (as described in Section II
`
`below) in the fields as of the Critical Date, or before.
`
`19. This declaration is organized as follows:
`
`I.
`
`II.
`
`Brief Overview of the ’418 Patent
`
`Level of Ordinary Skill in the Art
`
`III. Terminology
`
`IV. Discussion of References
`
`6
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`V.
`
`Legal Principles
`
`VI. Conclusion and Additional Remarks
`
`I.
`
`Brief Overview of the ’418 Patent
`
`20. The ’418 Patent includes 20 claims, of which claim 1, 12 and 17 are
`
`independent. Claims 2-11, 13-16, and 18-20 depend directly or indirectly from
`
`claims 1, 12, and 17, respectively. The technology in the ’418 Patent generally
`
`relates to a local interconnect structure that includes a gate-directed local
`
`interconnect coupled to an adjacent gate layer through a diffusion-directed local
`
`interconnect. ’418 Patent at Abstract.
`
`
`
`
`
`Design Trade-offs Discussed by the ’418 Patent
`
`21. The Background section of the ’418 Patent (“The Background”)
`
`describes the design trade-offs when trying to implement high density circuits in
`
`sub-micron processes. ’418 Patent at 1:10-2:22. The discussion of design trade-
`
`offs begins in the ’418 Patent with the need to have high density circuits while
`
`sustaining sufficient transistor strength. ’418 Patent at 1:15-25. The Background
`
`notes that “[t]o achieve high density yet have adequate transistor strength, strain
`
`engineering techniques have been developed so that the crystal lattice for the
`
`7
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`semiconductor substrate is strained in the diffusion region used to form the
`
`transistor source and drains.” ’418 Patent at 1:16-20.
`
`22. However, one design trade-off here is that straining techniques, such
`
`as compressive strain or tensile strain, introduce “a number of constraints into the
`
`layout process.” Id. at 1:26-58. For example, shorter diffusion regions that are
`
`provided for individual transistors may relax the strain and reduce the enhancement
`
`in the transistor strength compared to longer diffusion regions, or continuous
`
`diffusion regions, that are shared by multiple transistors. Id. On the other hand,
`
`implementing continuous diffusion regions shared by multiple transistors may
`
`cause one or more of the multiple transistors to be electrically shorted. Id.
`
`23. One solution noted in the ’418 Patent is to use a blocking transistor to
`
`isolate two neighboring transistors. Id. at 1:66-2:10. For example, as shown in the
`
`’418 Patent’s FIG. 2 below, a blocking transistor 201 may be used to isolate
`
`transistors 100 and 101. Id. The “diffusion region 200 is continuous for both
`
`transistors such that it can develop adequate lattice strain for satisfactory transistor
`
`strength.” Id. at 1:64-66.
`
`8
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`24. Yet, the introduction of a blocking transistor results in another trade
`
`off with chip density. In particular, the ’418 Patent explains that when blocking
`
`transistors were used, chip density decreased and layout designs became difficult
`
`
`
`to implement at the desired density. Id. at 2:10-18.
`
`
`
`Layout for Implementing High-Density Circuit with sufficient transistor
`strength
`
`25. To address the limitations and trade-offs noted above, the ’418 Patent
`
`discloses a circuit architecture that purportedly “provide[d] an advantageously
`
`dense local interconnect coupling for blocking transistors”. Id. at 5:49-41. An
`
`aerial layout view of the circuit implementation proposed by the ’418 Patent is
`
`provided in FIGS. 4A and 4B (reproduced below).
`
`9
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`’418 Patent at FIGS. 4A (left) and 4B (right) (with colored annotations)
`
`
`
`26. As shown in FIGS. 4A and 4B, the ’418 Patent proposes
`
`implementing a blocking transistor 430 between two transistors, a first transistor
`
`405 and a second transistor 420, all in a common diffusion region OD 400. Id. at
`
`6:6-29. The following sentences from the ’418 Patent describe the layouts in
`
`FIGS. 4A and 4B.
`
`27.
`
`“A gate layer 410, a gate layer 425, and a gate layer 415 form the
`
`gates for transistor 405, blocking transistor 430, and transistor 420, respectively.”
`
`Id. at 6:15-17. “A gate-directed local interconnect 440 couples (through a
`
`corresponding level 1 gate-directed interconnect, which is not illustrated) to a drain
`
`(D) for transistor 405. Similarly, a gate-directed local interconnect 435 couples to
`
`10
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`a source for transistor 420. A via VO coupled to gate-directed local interconnect
`
`435 provides the appropriate source voltage for transistor 420.” Id. at 6:17-23.
`
`28.
`
`In the ’418 Patent, "gated-directed" appears to refer to layers and
`
`elements that extend according to a "gate-layer" pitch or parallel to a gate structure,
`
`and "diffusion-directed" appears to refer to layers or elements that "extend in a
`
`diffusion-directed direction that is generally orthogonal to the gate-directed
`
`direction." Id. at 2:36-44.
`
`29.
`
`In FIG. 4A, a diffusion-directed local interconnect 445 “couples
`
`between gate layer 425 and gate-directed local interconnect 435 to provide the bias
`
`to gate layer 425 to turn blocking transistor 430 fully off.” Id. at 6:36-39. In FIG.
`
`4B, similarly, “a diffusion-directed local interconnect 450 couples between gate-
`
`directed local interconnect 435 and gate layer 425 analogous to the coupling
`
`provided by diffusion-directed local interconnect 445 of Figure 4A.” Id. at 7:9-12.
`
`In my opinion, the main difference between FIGS. 4A and 4B is the location of the
`
`diffusion-directed local interconnect. For example, in FIG. 4B, the diffusion-
`
`directed local interconnect 450 overlaps a portion of the diffusion region OD 400.
`
`In contrast, in FIG. 4A, the diffusion-directed local interconnect 450 does not
`
`overlap any portion of the diffusion region OD 400, and is placed outside of the
`
`diffusion region OD 400.
`
`11
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`30.
`
`In addition to the layout of transistors in a circuit, as indicated by the
`
`Abstract and Summary of the ’418 Patent, an important aspect of the ’418 Patent is
`
`the local interconnect structure “that includes a gate-directed local interconnect
`
`coupled to an adjacent gate layer through a diffusion-directed local interconnect.”
`
`’418 Patent at Abstract, 2:44-67. FIG. 3 (shown below) depicts a lateral view or
`
`vertical profile of the interconnect structures.
`
`31. The interconnect structure includes three levels of interconnects
`
`formed between the diffusion region 305 and a first metal layer M1. The first level
`
`of interconnects include interconnects Llc 310 and gate layer 300. Id. at 4:5-17,
`
`4:44-46. The first level of interconnects are formed on the continuous diffusion
`
`
`
`12
`
`’418 Patent at FIG. 3 (with colored annotations)
`
`
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`region 305 and provide direct electrical coupling to diffusion region 305. Id.
`
`Level 1 local interconnects must be gate-directed local interconnects. Id. at 4:47-
`
`50.
`
`32. The second level of interconnects include interconnects Lla 315 and
`
`Llb 320. Id. at 4:5-17. The second level of interconnects are formed between the
`
`first level and the third level of interconnects and “couple to first metal layer Ml
`
`(or higher metal layers) through vias such as a via V0” Id. at 4:19-23. Level 2
`
`local interconnects can be either gate-directed local interconnects (e.g., 315) or
`
`diffusion-directed local interconnects (e.g., 320). Id. at 4:47-54, 2:46-49. Level 2
`
`interconnects are distinguished from level 1 interconnects in that level 1
`
`interconnects are “directly couple[d] to a continuous diffusion region” and are
`
`implemented at “the level for a gate layer.” Ex.1001, 4:4-23.
`
`33. Level 3 interconnects include vias, e.g., via V0, and are arranged
`
`between level 2 interconnects and a first metal layer Ml. Id. at 4:19-23. Ex.1001,
`
`4:4-23. Level 3 interconnects are distinguished from level 2 interconnects in that
`
`level 2 interconnects do not include vias that connect to metal layer M1. Id.
`
`34. The ’418 Patent contends that the combination of the interconnect
`
`structure shown in FIG. 3 and the layout structure shown in FIG. 4A or FIG. 4B
`
`would address the design trade-offs and issues discussed above in paragraphs. Id.
`
`13
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`at 2:10-44, 5:1-64. In particular, a blocking transistor can be implemented between
`
`two transistors so that satisfactory transistor strength and a continuous diffusion
`
`region may be provided for multiple transistors. Id. At the same time, the
`
`interconnect structure helps with providing the requisite chip density. Id. at 6:58-
`
`7:23.
`
`35. The embodiments disclosed in the ’418 Patent could be implemented
`
`in various types of circuits. For instance, FIGS. 5A-5C appear to disclose a diode-
`
`connected transistor in which a diffusion-directed local interconnect is used. ’418
`
`Patent at 3:20-33. FIGS. 6A-6B disclose an inverter-to-inverter circuit in which a
`
`diffusion-directed local interconnect is used. ’418 Patent at 3:34-40. Although
`
`just limited types of circuits are described in the ’418 Patent, it is my
`
`understanding that the embodiments disclosed in the ’418 Patent could be
`
`implemented in other types of circuits as well.
`
`36. Notwithstanding the above, as noted in Section IV, based on my
`
`knowledge and experience in the industry, prior to the Critical Date, there existed
`
`numerous products, publications, and patents that implemented or described the
`
`embodiments claimed in the ’418 patent. As detailed in Section IV below, the
`
`circuit and circuit implementations disclosed in the ’418 patent were well-known
`
`14
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`in the prior art. To the extent there was any problem to be solved in the ’418
`
`patent, it had already been solved in the prior art systems before the Critical Date.
`
`
`
`II. Level of Ordinary Skill in the Art as of the Critical Date
`
`37.
`
`It is my understanding that obviousness and claim interpretation,
`
`among other things, are determined, in part, from the point of view of a person of
`
`ordinary skill in the art as of the Critical Date of the ’418 Patent (“APOSITA”).
`
`APOSITA would have had a Master’s of Science Degree (or a similar technical
`
`Master’s Degree, or higher degree) in an academic area emphasizing electrical
`
`engineering or computer engineering with a concentration in semiconductors or,
`
`alternatively, a Bachelors Degree (or higher degree) in an academic area
`
`emphasizing electrical or computer engineering and having two or more years of
`
`experience in integrated circuit design and/or semiconductor processing.
`
`Additional education in a relevant field, such as computer engineering, or electrical
`
`engineering, or industry experience may compensate for a deficit in one of the
`
`other aspects of the requirements stated above. Unless noted otherwise in this
`
`Petition, references to what would have been known or understood by APOSITA
`
`refer to the knowledge of APOSITA as of the Critical Date, or before.
`
`
`
`15
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`III. Terminology
`
`38.
`
`I am not a lawyer. However, I have been informed that, during an
`
`IPR proceeding involving the ’418 Patent, claim terminology is given the broadest
`
`reasonable interpretation (BRI) at the time of the Critical Date. Counsel has also
`
`informed me that PTAB is considering a change of the claim interpretation
`
`standard from BRI to the Phillips standard under which the words of the claims
`
`should be given their ordinary meaning.
`
`39.
`
`I have been requested to provide some guidance in this proceeding
`
`with respect to the terms below. In response to the request, I considered the
`
`context of the terms within the claims, use of the terms within the specification, my
`
`understanding of how APOSITA would have understood the terms as of the
`
`Critical Date, and have provided my interpretation below. I have used the Critical
`
`Date as the point in time for claim interpretation purposes, although in many cases
`
`the same analysis would hold true even at an earlier time than the Critical Date.
`
`A.
`
`“ means” for coupling
`
`40. Based on my review, I believe the “means” in “means for coupling,”
`
`as recited in claims 17-19 encompasses a “diffusion-directed local interconnect.”
`
`41. The ’418 Patent explicitly states that “[t]he diffusion-directed local
`
`interconnect [ ] serves as a means for coupling one of the gate-directed local
`
`16
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`interconnects to the gate layer.” ’418 Patent at 5:62-64. The “diffusion-directed
`
`local interconnect 445 [ ] couples between gate layer 425 and gate-directed local
`
`interconnect 435” and “diffusion-directed local interconnect 450 couples between
`
`gate-directed local interconnect 435 and gate layer 425 analogous to the coupling
`
`provided by diffusion-directed local inter-connect 445.” ’418 Patent at 6:36-38,
`
`7:9-12; see also FIGS. 4A, 4B, 5A, 5B. Thus, based on the explicit description in
`
`the ’418 Patent, in my opinion, the “means” in “means for coupling” encompasses
`
`a “diffusion-directed local interconnect.”
`
`
`
`IV. Discussion of References
`
`42. The following exemplary references demonstrate the prevalence of the
`
`claimed features in the prior art.
`
`A. Rashed 607
`
`43. Similar to the ’418 Patent, Rashed 607 is directed to addressing design
`
`and layout problems in high-density integrated circuits. Ex.1005, 2:16-34.
`
`According to Rashed 607, when more circuit devices are squeezed into a circuit
`
`area, the lateral spacing between the active regions of the circuit devices decreases,
`
`for example, up to “as little as about 40 nm.” Id. Rashed 607 recognizes that as
`
`this lateral spacing decreases, there is an increased risk of creating short circuits
`
`17
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`between the two adjacent cells. Ex.1005, 2:16-25. Accordingly, Rashed 607
`
`discloses the layout of a plurality of semiconductor devices formed in a continuous
`
`region in a manner in which the above-described lateral spacing and short circuit
`
`problems are avoided or reduced. Id., 2:34-37.
`
`44. Rashed 607 discloses Field Effect Transistors (FETs) that are formed
`
`in and above a continuous active region. Id., 1:17-24: 4:19-30. In particular, as
`
`shown in FIGS. 4A, 4B, and 4C below, two PFET devices 120P2-3 (shown in
`
`purple) are disposed in a first continuous active region 112P and two NFET
`
`devices 122N2-3 (shown in light blue) are disposed in a second continuous active
`
`region 112N. Ex.1005, 4:36-40, 6:27-65. FIGS. 4A-4C depict the same set of
`
`transistors arranged in different ways.
`
`45.
`
`In FIG. 4A, the two neighboring PFETs 120P2-3 have adjoining
`
`source regions (shown in red), and the two neighboring NFETs 122N2-3 have
`
`adjoining source regions (shown in red). Ex.1005, 6:23-36. Isolating electrode
`
`150PG (shown in green) is positioned between the adjoining source regions in the
`
`neighboring PFETs 120P2-3, and isolating electrode 150NG (shown in green) is
`
`positioned between the adjoining source regions in the neighboring NFETs 122N2-
`
`18
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`19
`
`Isolating electrode
`
`P
`
`F
`
`E
`
`T
`
`
`
`drain
`regions
`
`source regions
`
`power
`rail
`
`PF ET
`
`drain
`regions
`
`PF ET
`
`Isolating electrode
`
`power
`rail
`
`PF ET
`
`NFET
`
`NFET
`
`NFET
`
`NFET
`
`power
`Isolating electrode
`
`Isolating electrode
`rail
` FIG. 4A FIG. 4B
`
`
`
`power
`rail
`
`Isolating electrode
`
`power rail
`
`PF ET
`
`PF ET
`
`NFET
`
`NFET
`
`Isolating electrode
`
`FIG. 4C
`
`power rail
`
`
`’418 Patent at FIGS. 4A-4C (shown with colored annotations)
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`3. Id. Conductive structures 144 connect the source regions of PFETs 120P2-3 to
`
`a power rail 140H (shown in beige), and conductive structures 146 connect the
`
`source regions of NFETs 122N2-3 to a power rail 140L (shown in beige). Id.
`
`46.
`
`In FIG. 4B, the source region of PFET 120P2 is separated from the
`
`drain region of PFET 120P3 by isolating electrode 150PG. Ex.1005, 6:37-54. The
`
`source region of NFET 122N2 is separated from the drain region of NFET 122N3
`
`by isolating electrode 150NG. Id. Conductive structure 144 connects the source
`
`region of PFET 120P2 to power rail 140H, and conductive structure 146 connects
`
`the source region of NFET 122N2 to power rail 140L. Id. Conductive strip 148
`
`connect the drain of PFET 120P3 to the drain of NFET 122N3. Id. Power rail
`
`140H is at a logically high voltage, e.g., Vdd, and power rail 140L is at logically
`
`low voltage, e.g., ground. Ex.1005, 5:18-23.
`
`47.
`
`I have not provided a detailed description of FIG. 4C.
`
`48.
`
`In FIGS. 4A and 4B, a gate electrode 130 is shared between PFET
`
`120P2 and NFET 122N2, and another gate electrode 130 is shared between PFET
`
`120P3 and NFET 122N3. Ex.1005, 4:62-66, 5:34-42. “[I]solating electrodes
`
`150PG and 150NG have the same structure and configuration as the gate structures
`
`130,” and effectively function as gate electrodes for a dummy or blocking
`
`transistor when “isolating electrode 150PG … is conductively coupled to a
`
`20
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`schematically depicted power rail 140H at a logically high voltage, e.g., Vdd.” and
`
`“isolating electrode 150NG … is conductively coupled to a power rail 140L that is
`
`at a logically low voltage, e.g., ground.” Ex.1005, 5:18-40.
`
`49. A schematic plan view of FIG. 4A is shown in FIG. 5A. As depicted
`
`in FIG. 5A below, conductive contacts 190P (shown in blue) conductively couple
`
`power rail 140H (shown in beige) to source regions 120S (shown in red) of
`
`transistors 120P2 and 120P3, and conductive contacts 190N (shown in blue)
`
`conductively couple power rail 140L (shown in beige) to source regions 122S
`
`(shown in red) of transistors 122N2 and 122N3. Ex.1005, 7:29-37. A conductive
`
`contact 192P connects the isolating electrode 150PG (shown in green) to power
`
`rail 140H, and a conductive contact 192N connects the isolating electrode 150NG
`
`(shown in green) to power rail 140L. Id. Conductive contacts 190P and 190N are
`
`formed between the isolating electrode 150PG and the gate electrodes 130, and are
`
`connected to conductive line-type device level contacts 175, which “are formed on
`
`each of the source/drain regions for the various transistor devices” 120 P2-3 and
`
`122N2-3. Ex.1005, 7:21-23.
`
`50. Conductive structures, such as the power rails 140H, 140L, and
`
`contacts 190P, 192P, 190N and 192N, may be formed using tungsten in the local
`
`interconnect level of the device 100. Ex.1005, 7:49-8:14. That is, the power rails
`
`21
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`140H, 140L and contacts 190P, 192P, 190N and 192N may be formed between the
`
`device level contacts 175 and the so-called ‘metal 1’ layer that is typically the first
`
`general wiring layer formed above the substrate.” In other words, these are the
`
`second level local interconnects. Ex.1005, 7:49-57.
`
`51. Keeping in mind the overview of Rashed 607 noted above, it is clear
`
`to me that Rashed 607 discloses each and every feature of at least claims 1-3, 5-9,
`
`
`
`22
`
`conductive contacts
`
`power rail
`
`source regions
`
`isolating
`electrode
`
`isolating
`electrode
`
`conductive contacts
`
`power rail
`
`FIG. 5A (shown with colored annotations)
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`11-14, and 16-19. I will discuss the prior art’s disclosure of the claimed subject
`
`matter in more detail below.
`
`52.
`
`It is clear to me that that Rashed 607 discloses a circuit. As noted
`
`above, Rashed 607’s FIGS. 4A, 4B, 4C, and 5A display two PFET devices 120P2-
`
`3 disposed in a first continuous active region 112P and two NFET devices 122N2-
`
`3 disposed in a second continuous active region 112N. Ex.1005, 4:36-40, 6:27-65.
`
`Each continuous active region may be used for thousands of transistors. Id., 6:8-
`
`20, FIG. 3C. As is well-known in the art, a single FET transistor, by itself, is a
`
`circuit such as a switch. Evidence of this well-known understanding is provided
`
`by Hu, which as depicted by Hu’s FIG. 6-2 (shown below), teaches that a FET can
`
`be represented by a circuit symbol or a switch. Ex.1009, 196.
`
`53. Multiple FETs would form a more complex circuit. Rashed 607
`
`discloses multiple FETs connected to each other and therefore necessarily
`
`
`
`23
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`discloses “a circuit,” as recited in claims 1-11 and 17-20 of the ’418 Patent. The
`
`interconnect structure of Rashed 607’s circuit is shown below in FIGS. 4A, 4B,
`
`4C.
`
`54. As depicted in Rashed 607’s FIGS. 4A, 4B, and 5A, isolating
`
`electrodes 150PG/150NG (shown in green) operate effectively as gate electrodes
`
`since they have “the same structure and configuration as the gate structures 130.”
`
`Ex.1005, 5:33-40, 6:23-54. Gate electrodes 130 are shown in yellow for
`
`convenience and differentiation in the figures above.
`
`55. Rashed 607’s gate electrodes 130 and isolating electrodes 150PG and
`
`150NG are arranged according to a gate pitch. For instance, as is shown in Rashed
`
`607’s FIGS. 4A, 4B, and 5A, the central longitudinal axes of gate electrodes 130
`
`are separated from the central longitudinal axes of isolating electrodes 150PG and
`
`150NG by equal distances (constant gate pitch). At least because either one of
`
`Rashed 607’s isolating electrode 150PG or isolating electrode 150NG is arranged
`
`according to a gate layer pitch between gate electrodes 130 of transistors 120P2
`
`and 120P3, Rashed 607 discloses “a first gate layer arranged according to a gate
`
`layer pitch between a second gate layer and a third gate layer.”
`
`24
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`Second
`gate
`layer
`
`Third
`gate
`layer
`
`25
`
`
`
`
` FIG. 4A FIG. 4B
`
`
`
`
`Color Key for FIGS. 4A, 4B, 5A
`
`
`
`(figures shown with annotations in color)
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP1
`
`
`56. Furthermore, the isolating electrodes 150PG and 150NG and gate
`
`electrodes are disposed, at least in part, over the continuous active regions 112P
`
`and 112N and substrate. For example, Rashed 607 teaches forming a first
`
`continuous active region 112P and a second continuous active region 112N in a
`
`semiconducting substrate. Ex.1005, 4:36-39. In addition, a plurality of PFETs
`
`120P2 and 120P3 and NFET devices 122N2 and 122N3 with common gate
`
`structures 130 are formed over the first continuous active region 112P and the
`
`second continuous active region 112N, respectively. Ex.1005, 4:52-66. Thus,
`
`Rashed 607 discloses “forming a first gate layer over a semiconductor substrate
`
`according to a gate layer pitch between adjacent second and third gate layers.”
`
`57. As depicted in Rashed 607’s FIGS. 4A, 4B, and 5A (shown above),
`
`conductive structure 144 or conductive contact 190P (both shown in blue)
`
`conductively couple power rail 140H to the source regio

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