Paper 20
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`
`APPLE, INC.,
`
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED,
`
`Patent Owner
`______________
`
`Case IPR2018-01460
`
`U.S. Patent No. 9,024,418
`______________
`
`
`
`
`
`QUALCOMM INCORPORATED’S
`PATENT OWNER RESPONSE
`
`
`
`74681532.1
`
`

`

`Case IPR2018-01460
`Patent 9,024,418
`
`TABLE OF CONTENTS
`
`2.
`
`2.
`
`INTRODUCTION .......................................................................................... 1
`I.
`OVERVIEW OF U.S. PATENT NO. 9,024,418 (THE ’418 PATENT) ....... 3
`II.
`III. LEVEL OF ORDINARY SKILL IN THE ART ............................................ 5
`IV. CLAIM CONSTRUCTION ........................................................................... 6
`A. Means for Coupling the Gate-Directed Local Interconnect to the
`Third Gate Layer .................................................................................. 6
`“Configured To” / “Forming … To” .................................................... 7
`“Diffusion-Directed Local Interconnect” ........................................... 10
`“First Gate Layer For The Second Transistor To A Power Supply
`Node” .................................................................................................. 10
`THE INVENTORS’ INVENTION OF CLAIMS 1-2, 4-5, 8, 12-13,
`15-18, AND 20 ANTEDATES BOTH RASHED AND LU........................ 11
`A.
`The Swear-Behind Claims Were Conceived by January 17, 2012 .... 12
`1.
`The Swear-Behind Claims were conceived and embodied
`in a test structure included in a test chip submitted for
`fabrication on January 17, 2012 .............................................. 12
`The DUT 16 test structure embodies all elements of the
`Swear-Behind Claims ............................................................... 13
`The Swear-Behind Claims Were Reduced to Practice by June 28,
`2012, Antedating Rashed and Lu ....................................................... 34
`1.
`By June 28, 2012, the fabrication of an embodiment of the
`Swear-Behind Claims in QPTC20_1T test chips was
`completed ................................................................................. 34
`By June 28, 2012, testing showed that the MP over OD
`concept embodied in the Swear-Behind Claims would work
`for its intended purpose ........................................................... 36
`
`V.
`
`B.
`C.
`D.
`
`B.
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`74681532.1
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`

`C.
`
`D.
`
`2.
`
`Case IPR2018-01460
`Patent 9,024,418
`Further Activities from June Through September 2012 Also
`Demonstrate the Swear-Behind Claims Antedate Rashed and Lu
`Through Additional Reductions to Practice Coupled with
`Reasonably Continuous Diligence ..................................................... 37
`1.
`Additional fabrication of embodiments of the Swear-
`Behind Claims completed between July and August 2012 ...... 37
`Analysis of additional test results culminating no later than
`September 2012 again confirm that MP over OD concept
`embodied in the Swear-Behind Claims would work for its
`intended purpose ...................................................................... 38
`Patent Owner Exhibited Reasonably Continuous Diligence With
`Regard to the QPTC20_1T Test Chip From July to September
`2012 .................................................................................................... 40
`VI. RASHED DOES NOT ANTICIPATE OR RENDER OBVIOUS
`CLAIMS 1-3, 5, 8, 9, 12-14, AND 16-19 .................................................... 49
`A.
`Rashed Does Not Disclose Or Suggest the Configuration or
`Arrangement of Structures Petitioner Asserts and Relies Upon ........ 49
`1.
`Power rails 140H and 140N are configured to deliver
`power to each of a variety of components ............................... 49
`Petitioner’s purported “diffusion-directed local
`interconnect” is not in physical contact with Petitioner’s
`purported “first gate layer”..................................................... 51
`Figures 4A and 4B of Rashed do not contain sufficient
`detail to demonstrate the structural arrangements required
`by the Challenged Claims ........................................................ 54
`Petitioner’s mapping does not map contacts 192P or 192N
`to any claim elements, despite misleading annotated
`figures to the contrary .............................................................. 56
`
`
`2.
`
`3.
`
`4.
`
`
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`

`2.
`
`2.
`
`Case IPR2018-01460
`Patent 9,024,418
`Claim 1 is Not Anticipated or Rendered Obvious by Rashed
`Because Rashed Does Not Disclose or Render Obvious Element
`[1.5]. ................................................................................................... 56
`1.
`Petitioner fails to show power rail 140H or 140L is
`“configured to” couple the first gate layer to one of the
`first and second gate-directed local interconnects .................. 56
`The multiple structures that physically connect the first
`gate layer and one of the first and second gate-directed
`local interconnects are not what Petitioner asserts is the
`diffusion-directed local interconnect layer .............................. 58
`Conclusion ............................................................................... 59
`3.
`Claim 12 is Not Anticipated or Rendered Obvious by Rashed
`Because Rashed Does Not Disclose or Render Obvious Element
`[12.5]. ................................................................................................. 59
`1.
`Petitioner fails to show power rail 140H or 140L is
`“form[ed] … to” couple the first gate layer to one of the
`first and second gate-directed local interconnects .................. 59
`The multiple structures that physically connect the first
`gate layer and one of the first and second gate-directed
`local interconnects are not what Petitioner asserts is the
`diffusion-directed local interconnect layer .............................. 60
`Conclusion ............................................................................... 60
`3.
`Claim 17 is Not Anticipated or Rendered Obvious by Rashed
`Because Rashed Does Not Disclose or Render Obvious Element
`[17.6]. ................................................................................................. 60
`1.
`Petitioner fails to identify anything in Rashed meeting the
`corresponding structure for the “means for coupling …”
`of element 17.6 ......................................................................... 60
`Conclusion ............................................................................... 61
`
`
`2.
`
`B.
`
`C.
`
`D.
`
`
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`

`B.
`
`B.
`
`Case IPR2018-01460
`Patent 9,024,418
`VII. CLAIM 5 IS INDEPENDENTLY NOT ANTICIPATED OR
`RENDERED OBVIOUS BY RASHED BECAUSE RASHED DOES
`NOT DISCLOSE OR RENDER OBVIOUS ELEMENT [5.2]. .................. 62
`A.
`Petitioner Fails to Show any “Power Supply Node” Connected to
`Metal 1 ................................................................................................ 62
`Petitioner’s mapping is inconsistent with Petitioner’s identification
`of the purported first gate-directed interconnect layer in earlier
`claim elements .................................................................................... 65
`VIII. CLAIMS 4, 15, AND 20 ARE NOT RENDERED OBVIOUS BY
`RASHED IN VIEW OF LU ......................................................................... 65
`A.
`Petitioner’s Proposed Modified Structure is Nonfunctional, and a
`Complete Functional Modified Structure Would be Contain
`Duplicative Components Without Any Advantages .......................... 67
`1.
`A functional modification of Rashed in view of Lu would
`not remove the power rails of Rashed ..................................... 67
`The complete combination provides no advantage over
`Rashed itself that would warrant the combination .................. 70
`Petitioner Offers No Credible Motivation to Combine ...................... 70
`1.
`There is No Area Reduction Achieved by the Rashed-Lu
`Combination Proposed by Petitioner. ..................................... 71
`Petitioner’s additional rationales offered in conclusory
`fashion to show a reasonable expectation of success also
`would not have motivated a POSITA to combine Rashed
`and Lu as proposed by Petitioner. ........................................... 74
`Conclusion ............................................................................... 76
`3.
`IX. CONCLUSION ............................................................................................. 77
`
`
`
`2.
`
`2.
`
`
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`74681532.1
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`

`

`TABLE OF AUTHORITIES
`
`Case IPR2018-01460
`Patent 9,024,418
`
` Page(s)
`
`Cases
`Acclarent, Inc. v. Ford Albritton, IV,
`IPR2017-00498, slip op. (PTAB July 9, 2018) (Paper 40) .......................... 2, 7, 8
`Aspex Eyewear, Inc. v. Marchon Eyewear, Inc.,
`672 F.3d 1335 (Fed. Cir. 2012) .............................................................. 2, 7, 8, 10
`ATI Techs. ULC v. Iancu,
`920 F.3d 1362 (Fed. Cir. 2019) .................................................................... 40, 49
`Belden Inc. v. Berk–Tek LLC,
`805 F.3d 1064 (Fed. Cir. 2015) .......................................................................... 75
`Cheese Sys., Inc. v. Tetra Pak Cheese & Powder Sys., Inc.,
`725 F.3d 1341 (Fed. Cir. 2013) .......................................................................... 76
`Cooper v. Goldfarb,
`154 F.3d 1321 (Fed. Cir. 1998) .......................................................................... 34
`In re Giannelli,
`739 F.3d 1375 (Fed. Cir. 2014) ...................................................................... 8, 75
`Hybritech Inc. v. Monoclonal Antibodies, Inc.,
`802 F.2d 1367 (Fed. Cir. 1986) .......................................................................... 12
`Innogenetics, N.V. v. Abbott Labs.,
`512 F.3d 1363 (Fed. Cir. 2008) .......................................................................... 71
`In re Kahn,
`441 F.3d 977 (Fed. Cir. 2006) ...................................................................... 70, 74
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ............................................................................................ 70
`In re Lee,
`277 F.3d 1338 (Fed. Cir. 2002) .......................................................................... 75
`
`74681532.1
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`

`Case IPR2018-01460
`Patent 9,024,418
` Page(s)
`
`Cases (cont.)
`In re Man Machine Interface Technologies LLC,
`822 F.3d 1282 (Fed. Cir. 2016) ............................................................................ 8
`In re Nuvasive,
`842 F.3d 1376 (Fed. Cir. 2016) .......................................................................... 75
`Pers. Web Techs., LLC v. Apple, Inc.,
`848 F.3d 987 (Fed. Cir. 2017) ............................................................................ 75
`R.J. Reynolds Vapor Co. v. Fontem Holdings 1 B.V.,
`IPR2016-01268, slip op. (PTAB Dec. 19, 2017) (Paper 63) .............................. 71
`Williamson v. Citrix Online, LLC,
`792 F.3d 1339 (Fed. Cir. 2015) ............................................................................ 6
`Other Authorities
`37 CFR § 1.131(b) ....................................................................................... 11, 34, 37
`
`
`
`
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`

`PATENT OWNER’S EXHIBIT LIST
`
`Case IPR2018-01460
`Patent 9,024,418
`
`No.
`2001
`
`2006
`
`Description
`Excerpts of Qualcomm and Apple Joint Claim Construction Hearing
`Statement (CASE NO. 3:17-cv-2402-CAB-MDD) (pages relating to other
`patents omitted)
`2002 Declaration of Pradeep Lall
`2003
`CV of Pradeep Lall
`2004
`Transcript of Deposition of David Kuan-Yu Liu (May 22, 2019)
`2005
`Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 15 Submitted to TSMC on January 17, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 16 Submitted to TSMC on January 17, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Excerpted Screenshots from Qualcomm Tapeout Manager Program
`Documenting Submission of QPTC20_1T Test Chip to TSMC
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`[omitted]
`Presentation by Chock Gan dated January 5, 2012 titled "20SOC
`QPTC20_1T Consolidated module DRC Waiver Request"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Yang dated January 19, 2012 Documenting Completion
`of QPTC20_1T Tapeout and Summarizing Design Team
`Accomplishments
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2011A E-mail dated February 15, 2012 from R. Bucki to Dr. Yang Summarizing
`CPU1 Test Modules with Continuous OD Test Structures in DUTs 13-16
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2011B Attachment to E-mail in Exhibit 2011A named "QPTC20_1T CPU1
`documentation-Feb.15th-2012.xlsx"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`2007
`
`2008
`2009
`
`2010
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`74681532.1
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`Case IPR2018-01460
`Patent 9,024,418
`
`2012
`
`2011C Attachment to Email in Exhibit 2011A named "QPTC20_1T_CPU1
`documentation-02152012.pptx"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Calendar Appointments and Agendas from Dr. Nallapati for Weekly Calls
`between Qualcomm and TSMC regarding QPTC20_1T and 20 Nanometer
`Technology Development from February 27, 2012 through September 27,
`2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`[omitted]
`2013
`2014A E-mail dated April 17, 2012 to Qualcomm 20 nanometer Team Leads
`with Finalized Test Plan and Overview of Testplan for Evaluating
`QPTC20_1T Test Chips
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2014B Attachment to Email in Exhibit 2014A named "QPTC20_1T TSMC
`testplan overview.pptx"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2014C Attachment to Email in Exhibit 2014A named
`"qptc20_1T_test_plan_v1p0_04162012.xls"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Presentation from TSMC dated May 24, 2012 Summarizing Status of
`QPTC20_1T Fabrication and Testing
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2016A Images of Lead Lot (N96Y08) QPTC20_1T Test Chip Samples Analyzed
`with TEM in EX2016B
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2016B Transmission Electron Microscope Images of CPU1 DUT16 Structures in
`the Lead Lot (N96Y08) QPTC20_1T Test Chip Samples
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2016C Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 16 Analyzed with TEM in EX2016B
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`2015
`
`74681532.1
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`

`Case IPR2018-01460
`Patent 9,024,418
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`E-mail Thread from March 30, 2012 through September 24, 2012
`containing Agendas for Weekly Call Meetings over that Period
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`TSMC Summary of QPTC20_1T Status dated June 28, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from TSMC Regarding Cancellation of Weekly Joint Qualcomm-
`TSMC Development Call in Observence of US National Holiday on July
`4, 2012 dated July 3, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`TSMC Summary of QPTC20_1T Status dated July 12, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Internal Qualcomm E-mail Thread Confirming Receipt of QPTC20_1T
`testing data from TSMC on July 13, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2022A E-mail from Dr. Yang Assigning Responsibility to Qualcomm Team for
`Analyzing Testing Data for QPTC20_1T Received from TSMC dated
`July 13, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2022B Attachment to Exhibit 2022B containing N96Y08 Lot Test Data named
`"Copy of N96Y08 QPTC20 Device data-working on by Frank Yang.xls"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Mr. Sy to Qualcomm 20 Nanometer Team Members dated
`July 14, 2012 Summarizing Weekly Meeting Held on July 13, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Nallapati to 20 Nanometer Development Team regarding
`Status of 20 Nanometer Chips with TSMC dated July 14, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail with Attachment from Dr. Nallapati to TSMC and Mr. Sy dated
`July 19, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`TSMC Summary of QPTC20_1T Status dated July 19, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`2023
`
`2024
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`2025
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`2026
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`Case IPR2018-01460
`Patent 9,024,418
`
`2029
`
`2030
`
`2027A E-mail thread between TSMC, Dr. Nallapati, Mr. Sy, and others between
`July 18, 2012 and August 22, 2012 discussing missing test data,
`debugging, and re-testing related to TSMC's July 13, 2012 QPTC20_1T
`tests and status of back up wafers to first lot
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2027B Attachment to E-mail dated August 22, 2012 in Exhibit 2027A Defining
`revised QPTC20_1T Test Plan
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2028A E-mail from Qualcomm to TSMC and Dr. Nallapati Providing Shipping
`Instructions of QPTC20_1T Test Chips
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2028B Attachment to Exhibit 2028A containing QPTC20_1T Test Chip Build
`Plan
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail thread between TSMC, Dr. Nallapati, Mr. Sy, and others between
`July 18, 2012 and July 27, 2012 discussing re-testing related to TSMC's
`July 13, 2012 QPTC20_1T tests and Shipment of First Lot (N96Y08) of
`QPTC20_1T to Qualcomm
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Yang regarding Data Summary and Remaining Action
`Items for First Lot QPTC20_1T Silicon dated July 25, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`TSMC Summary of QPTC20_1T Status dated July 26, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Nallapati dated July 30, 2012 Summarizing Status and
`Action Items after July 25, 2012 Joint Call between Qualcomm and
`TSMC
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`[omitted]
`E-mail Discussion between Qualcomm and TSMC dated July 31, 2012
`through August 2, 2012 Rescheduling Qualcomm-TSMC Joint Joint Call
`for August 2, 2012 after Cancellation on August 1, 2012 Due to Typhoon
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
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`2031
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`2032
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`2033
`2034
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`74681532.1
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`Case IPR2018-01460
`Patent 9,024,418
`
`2035
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`2036
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`2037
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`2038
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`2039
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`2040
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`2041
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`2042
`2043
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`2044
`
`TSMC Summary of QPTC20_1T Status dated August 1, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Testing Data for One QPTC20_1T Test Chip Wafer from Lot ID N97H63
`dated August 1, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Nallapati to 20 Nanometer Development Team dated
`August 7, 2012 Summarizing Internal Qualcomm Meeting Held on
`August 3, 2012 to Discuss Plan of Record and Design Rules for
`Continued Development of 20 nanometer Chipsets
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Spreadsheet dated August 8, 2012 Containing TSMC Re-Test Data for
`QPTC20_1T Ring Oscillator Test Modules from Original N96Y08 Lot
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Yang Assigning Responsibility to Qualcomm Team for
`Analyzing Testing Data for QPTC20_1T Lot ID N97H63 Received from
`TSMC dated August 8, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Testing Data for QPTC20_1T Test Chips from Lot ID N97H63 dated
`August 8, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail Thread between Dr. Nallapati and TSMC beginning August 13,
`2012 and ending August 23, 2012 discussing Alignment of 20 nanometer
`Design Rules and Consistency of Test Results for QPTC20_1T Testing
`between Qualcomm and TSMC Testing
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`[omitted]
`TSMC Summary of QPTC20_1T Status dated August 16, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Testing Data for QPTC20_1T Test Chips from Lot ID N97H65 dated
`August 23, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
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`74681532.1
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`

`Case IPR2018-01460
`Patent 9,024,418
`
`2045
`
`2046
`
`Internal E-mail to Qualcomm 20 nanometer Development Team
`Summarizing Status for Work Week 34 dated August 24, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Nallapati dated August 27, 2012 Summarizing Status and
`Action Items after August 22 and August 24, 2012 Joint Calls between
`Qualcomm and TSMC
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail thread between Dr. Nallapati and TSMC containing Weekly Joint
`Call Agendas from April 2, 2012 through August 28, 2012 including
`discussions of the August 28, 2012 Agenda dated August 29, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Mr. Sy to TSMC and Dr. Nallapati regarding Receipt of Re-
`Test Data for QPTC20_1T Lot ID N97H65 (DOE Lot) dated August 30,
`2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Internal E-mail to Qualcomm 20 nanometer Development Team
`Summarizing Status for Work Week 35 dated August 31, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Internal E-mail to Qualcomm 20 nanometer Development Team from Dr.
`Nallapati Summarizing Status of work with TSMC for Work Week 35
`dated August 31, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail from Dr. Nallapati dated September 1, 2012 Summarizing Status
`and Action Items after August 29, 2012 Joint Calls between Qualcomm
`and TSMC
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail Correspondence between Qualcomm and TSMC dated September
`4, 2012 Reporting Completion of Re-test for Back Up Lead Lot Wafers
`(N97H63) and DOE Lot Wafers (N97H65) using updated Test Plan
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2053A E-mail Thread between Qualcomm and TSMC from July 23, 2012 until
`September 7, 2012 regarding Shipment of QPTC20_1T Test Chips from
`TSMC to Qualcomm
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`2047
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`2048
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`2049
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`2050
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`2051
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`Case IPR2018-01460
`Patent 9,024,418
`
`2054
`
`2055
`
`2053B Attachment to E-mail in Exhibit 2053A named "Jan 2012 20nm QPTC
`Build Plan Rev 3 120906.xlsx"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2053C Attachment to E-mail in Exhibit 2053A named "U33912094259.txt"
`Containing Shipment Details for 62 Chips from QPTC20_1T Lot N97H65
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail dated September 13, 2012 Documenting Minutes from Internal
`Qualcomm Meeting on September 12, 2012 discussing Development of
`Qualcomm Chips Code Named "Krait" and 20 nanometer Chips Called
`"20SOC"
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`Calendar Appointment from Dr. Nallapati Titled "20nm Internal Design-
`Tech Sync" dated September 14, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2056A Qualcomm Presentation titled "20SoC - QPTC-1T Si Ring Oscillator
`Data" dated September 14, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2056B Native PowerPoint File for EX2056A titled "20SoC - QPTC-1T Si Ring
`Oscillator Data" dated September 14, 2012, last modified September 21,
`2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2057 Qualcomm In-House Test Results for QPTC20_1T Test Chips Created
`August 15, 2012 and Last Modified September 18, 2012
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`E-mail thread between Dr. Nallapati and Mr. Bucki at Qualcomm between
`September 4, 2012 and September 5, 2012 regarding Review of
`QPTC20_1T DUTs 15 and 16
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`[omitted]
`2059
`2060 Declaration of Dr. Giridhar Nallapati
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2061 Declaration of Dr. John Zhu
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`2058
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`Case IPR2018-01460
`Patent 9,024,418
`
`2062 Declaration of Dr. Bin Yang
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`2063 Declaration of Dr. Lavakumar Ranganathan
`**ATTORNEYS ONLY PROTECTIVE ORDER MATERIAL**
`
`
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`74681532.1
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`

`

`Case IPR2018-01460
`Patent 9,024,418
`
`I.
`
`INTRODUCTION
`Each ground Petitioner asserts relies primarily on Rashed, a patent filed July
`
`2, 2012. For claims 4, 15, and 20, Petitioner also relies up Lu, a patent filed February
`
`27, 2013. For all but a handful of the Challenged Claims,1 neither Rashed nor Lu is
`
`prior art because the inventors’ invention antedates the claims. The inventors
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`conceived of the Swear-Behind Claims no later than January 17, 2012, as
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`corroborated by a circuit layout (GDS) file of that date defining a test chip known as
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`QPTC20_1T that contains structures embodying the Swear-Behind Claims. The
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`claims were reduced to practice by June 28, 2012—prior to Rashed’s and Lu’s filing
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`date—through fabrication and testing of that test chip.2
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`Further, Petitioner’s mapping of all the challenged independent claims is
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`flawed. Claims 1 and 12 of the ’418 Patent require that a diffusion-directed local
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`interconnect be configured to or formed to couple a first gate layer to a first or
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`second gate-directed local interconnect. The Federal Circuit has repeatedly held that
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`1 The Challenged Claims are 1-5, 8-10, and 12-20. Patent Owner’s swear-behind
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`covers claims 1-2, 4-5, 8, 12-13, 15-18, and 20 (“Swear-Behind Claims”).
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`2 Moreover, out of an abundance of caution, Patent Owner identifies additional
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`evidence of further fabrication and testing activities between July and September
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`2012 showing further reductions to practice and reasonably continuous diligence.
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`language such as configured to and formed to should be interpreted as “requiring
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`structure designed to or configured to accomplish the specified objective, not simply
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`that they can be made to serve that purpose.” Acclarent, Inc. v. Ford Albritton, IV,
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`IPR2017-00498, slip op. at 16 (PTAB July 9, 2018) (Paper 40) (quoting Aspex
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`Eyewear, Inc. v. Marchon Eyewear, Inc., 672 F.3d 1335, 1349 (Fed. Cir. 2012)).
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`Petitioner asserts that these elements are met in Rashed based on the purported “first
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`gate layer” and “gate-directed local interconnect” each being independently coupled
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`to a power rail. But Rashed is clear that the single power rail is configured and
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`formed to supply power to numerous components. Rashed never suggests that the
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`power rail is designed to achieve the claimed coupling objective. Unlike the
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`disclosure to which Petitioner cites, Rashed does explicitly describe other structures
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`as configured to couple other structures together. See, e.g., APPLE-1005, 7:27-30
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`(describing two components being “conductively coupled” “by a plurality of
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`conductive contacts 190P”). Moreover, even if the claim language “configured to”
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`and “formed … to” were ignored, the structures physically arranged between the
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`purported “first gate layer” and “gate-directed local interconnect” are not a
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`“diffusion-directed local interconnect” under the specification’s explicit definition.
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`Claim 17 recites a “means for coupling” whose corresponding structure in the
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`’418 Patent is limited to a diffusion-directed local interconnect, and nothing more,
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`performing the “coupling” function. But the power rail of Rashed, to which
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`Petitioner again points, does not perform this function, even under Petitioner’s view,
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`without additional structures.
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`Next, Petitioner’s mapping of dependent claim 5’s “power supply node” fails
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`because it is not based on any actual disclosure in Rashed. Rather, Petitioner
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`describes and relies upon a purported “power supply node”—not actually disclosed
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`in Rashed—that Petitioner asserts is different from the power rails described above.
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`Finally, Petitioner’s assertion that claims 4, 15, and 20 are rendered obvious
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`by Rashed in view of Lu fails because Petitioner identifies no legitimate basis other
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`than hindsight to combine these two references. Petitioner’s primary motivation to
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`combine—a purported reduction in area—is founded upon an unexplained removal
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`of power rails in the proposed modified device despite the facts that all combined
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`references include power rails, and any modified structure would not function
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`without power rails.
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`II. OVERVIEW OF U.S. PATENT NO. 9,024,418 (THE ’418 PATENT)
`The ’418 Patent describes arrangements of semiconductor structures to
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`improve interconnect and transistor densities in circuit layouts. See, e.g., APPLE-
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`1001, 1:6-8; 5:2-3; 5:66-6:3; 6:67-7:8. In particular, the ’418 Patent describes
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`interconnect structures between transistor structures on a chip to maximize transistor
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`density. Compare id., 2:16-18 with id., 5:2-3. Adjacent transistors are isolated from
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`one another with a blocking transistor that may be biased to ground or to a supply
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`voltage. Id., 5:54-57, 6:23-31. The gate of the blocking transistor is separated from
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`the gate of each adjacent transistor according to a gate layer pitch. Id., 5:54-57. To
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`implement and bias the blocking transistor, the ’418 Patent discloses a novel routing
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`scheme for biasing the blocking transistor gate that utilizes local interconnect
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`structures, located between the lower-most metal layer and the underlying
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`semiconductor substrate, to tie the gate of the blocking transistor to the source of an
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`adjacent transistor that is tied to ground or to a supply voltage. Id., FIGS. 4A-4B,
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`6:30-7:3. This eliminates the need to extend the gate of the blocking transistor to
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`independently connect the blocking transistor’s gate to ground or to a supply voltage
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`using a separate via (contact hole). Id., FIGS. 4A-4B, 6:30-7:3. This eliminates the
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`previously-required elements shown in dotted line at the top of Figure 4A below,
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`thereby reducing the height of the circuit layout to allow rows of circuits to be spaced
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`closer together.
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`APPLE-1001, FIGs. 4A-4B (Annotated)
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`III. LEVEL OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) relevant to the ’418 Patent
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`at the time of its invention would have had (a) a Bachelor’s of science degree in an
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`engineering discipline or physics, or a closely-related field, and at least two years of
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`work or research experience in the field of semiconductor design or fabrication, or
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`(b) a Master’s of science degree in an engineering discipline or physics, or a closely-
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`related field, and at least one year of work or research experience in that same field.
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`EX2002, ¶¶33-36. For this issues in this Response, there is no material difference if
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`the January 17, 2012 conception date or March 14, 2013, filing date is used as the
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`date of invention. Id.
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`IV. CLAIM CONSTRUCTION
`A. Means for Coupling the Gate-Directed Local Interconnect to the
`Third Gate Layer
`Elements subject to Section 112, Paragraph 6 are limited to “structure,
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`materials, or acts described in the specification as corresponding to the claimed
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`function and equivalents thereof.” Williamson v. Citrix Online, LLC, 792 F.3d 1339,
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`1347 (Fed. Cir. 2015). Petitioner fails to follow this standard, vaguely stating “[t]he
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`‘means’ in ‘means for coupling’ encompasses a ‘diffusion-directed local
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`interconnect.’” Pet., 13.
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`In the co-pending litigation, Petitioner agreed to a proper identification of
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`corresponding structure as: “a diffusion-directed local interconnect as described at
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`7:8-12, Fig. 4A, 3:9-14, Fig. 4B, 3:15-19, 7:12-16, 5:62-64, 6:36-39, 8:9-11, 2:48-
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`52, Figs. 5A, 5B, 6A, 7A, or 7B, and equivalents thereof.” See EX2001, 26-28.
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`(emphasis added). Thus, the relevant corresponding structures are the specific
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`diffusion-directed local interconnects described and illustrated in the ’418 Patent as
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`performing the claimed function and equivalents.
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`For each corresponding structure, the diffusion-directed local interconnect—
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`and the diffusion-directed local interconnect alone—performs the claimed function.
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`EX2002, ¶40. This is shown, for example, in Figure 4B, in which diffusion-directed
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`local interconnect 450 is arranged so as to directly contact gate layer 425 and gate-
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`directed local interconnect 435:
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`
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`None of the diffusion-directed local interconnects rely upon other structures,
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`for example an intermediate connection, to complete the physical connection
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`between the gate-directed local interconnect or gate layer. EX2002, ¶42.
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`“Configured To” / “Forming … To”
`B.
`Under the BRI, the phrase “configured to” in claim 1 should be construed as
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`“requiring structure