UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________
`
`
`APPLE, Inc.,
`
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED,
`
`Patent Owner
`______________
`
`Case IPR2018-01460
`
`U.S. Patent No. 9,024,418
`______________
`
`
`
`DECLARATION OF PRADEEP LALL, PH.D.
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`
`
`
`
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`1
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`Apple, Inc. v. Qualcomm Incorporated
`IPR2018-01460
`Qualcomm Ex. 2002
`Page 1 of 69
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`A. Qualifications
`1. My name is Pradeep Lall. I am the MacFarlane Endowed Distinguished
`
`Professor of Mechanical Engineering and Director of the NSF-CAVE3 Electronics
`
`Research Center at Auburn University. I hold a courtesy joint appointment in the
`
`Department of Electrical and Computer Engineering at Auburn University. I have
`
`been retained by Qualcomm Incorporated to provide opinions in the inter partes
`
`review proceeding IPR2018-01460 (the “’1460 proceeding”) challenging U.S.
`
`Patent No. 9,024,418 (the “’418 Patent”).
`
`2.
`
`I have a Bachelor of Engineering degree in Mechanical Engineering from
`
`Delhi College of Engineering, a Master of Science degree from the University of
`
`Maryland, College Park in Mechanical Engineering, a Master of Business
`
`Administration degree from the Kellogg School of Management at Northwestern
`
`University, and a Doctor of Philosophy degree from the University of Maryland,
`
`College Park in Mechanical Engineering.
`
`3.
`
`I was previously an engineer at Motorola, Inc. from 1994 until 2002, where I
`
`held various roles from Lead Engineer to Distinguished Member of the Technical
`
`Staff.
`
`4.
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`At Auburn University, where I have worked in teaching and research since
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`2002, I currently hold the position of Director for the NSF-CAVE3 Electronics
`
`Research Center and the John Anne MacFarlane Endowed Distinguished
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`2
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`Professor. I am also on the Technical-Council and Governing-Council for the
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`NextFlex Manufacturing Institute.
`
`5. My research and primary fields within engineering concern electronics
`
`device design, including analysis and designs to prevent or delay electronic failures
`
`and related modeling and simulations.
`
`6.
`
`I have conducted research or worked in the general field of electronics for
`
`the last 30-years, since starting my graduate studies in 1988. I have authored 2
`
`books, 14 book chapters, and over 550 journal and conference papers related to
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`integrated circuit design, testing, reliability, and prognostics health management of
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`electronics systems for engineering societies, such as the Institute of Electrical and
`
`Electronics Engineers (IEEE), the Surface Mount Technology Association
`
`(SMTA) International, American Society of Mechanical Engineers (ASME),
`
`International Society of Hybrid Microelectronics (now IMAPS), and many others.
`
`I am the named inventor on three patents related to semiconductor interconnects
`
`and related structures.
`
`7.
`
`I am a fellow of the IEEE, fellow of the ASME, fellow of the Alabama
`
`Academy of Science, and a Fellow of the NextFlex National Manufacturing
`
`Institute.
`
`8.
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`I am a member of the technical council and the governing council of the
`
`NextFlex Flexible Electronics Manufacturing Institute. I also serve as the
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`3
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`technical co-lead of the asset and situational awareness technical working group of
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`the NextFlex Manufacturing Institute.
`
`9.
`
`I have served as the Vice-President of Publications for the IEEE Reliability
`
`Society. Presently, I serve on the Advisory Committee (AdCom) and the Executive
`
`Committee (ExCom) of the IEEE Reliability Society. In addition, I serve on the
`
`Board-of-Governors of the IEEE Electronic Packaging Society.
`
`10.
`
`I am recipient of the National Science Foundation IUCRC Program’s Alex
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`Schwarzkopf Award for Technology Innovation.
`
`11.
`
`I am also the recipient of the IEEE Outstanding Sustained Technical
`
`Contribution Award and the IEEE Exceptional Technical Contribution Award. In
`
`total, my research in the general field of electronics has been recognized with over
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`30-Awards. A list of awards and honors can be found in my CV.
`
`12. My attached Curricula Vitae (EX2003) details my overall expertise and
`
`experience in the field of semiconductor design or fabrication.
`
`B. Materials Reviewed
`I have reviewed the Petition submitted in the ’1460 proceeding, as well the
`13.
`
`Patent Owner Preliminary Response submitted in the ’1460 proceeding.
`
`14.
`
`I have reviewed the ’418 Patent that is included as Ex. APPLE-1001 in the
`
`’1460 proceeding, and I have reviewed the prosecution history for the ’418 Patent,
`
`excerpts of which are included as Ex. APPLE-1002 in the ’1460 proceeding.
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`4
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`15.
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`I have reviewed the declaration of Dr. Liu, which is Ex. APPLE-1003 in the
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`’1460 proceeding.
`
`16.
`
`I have reviewed the Institution Decision entered by the Panel in the ’1460
`
`proceeding.
`
`17.
`
`I have reviewed the transcript of Dr. Liu’s deposition conducted as part of
`
`the ’1460 proceeding, which is Ex. 2004 in the ’1460 proceeding.
`
`18.
`
`I have reviewed the declaration of Dr. Giridhar Nallapati, which is Ex. 2060
`
`in the ’1460 proceeding.
`
`19.
`
`I have reviewed the declaration of Dr. John Zhu, which is Ex. 2061 in the
`
`’1460 proceeding.
`
`20.
`
`I have reviewed the declaration of Dr. Bin Yang, which is Ex. 2062 in the
`
`’1460 proceeding.
`
`21.
`
`I have reviewed the declaration of Dr. Lavakumar Ranganathan, which is
`
`Ex. 2063 in the ’1460 proceeding.
`
`22. A complete listing of the documents I reviewed is as follows:
`
`Pr / Ex Title
`2 Petition
`6 Patent Owner Preliminary Response
`7 Institution Decision
`1001 U.S. Pat. No. 9,024,418
`1002 Excerpts of ’418 Patent Prosecution History
`1003 Liu Declaration
`1005 Rashed
`
`
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`5
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`1006 Lu
`1007 Nauta
`2001 Excerpts of Qualcomm and Apple Joint Claim Construction Hearing
`Statement (CASE NO. 3:17-cv-2402-CAB-MDD) (pages relating to
`other patents omitted)
`2004 Deposition of David Liu (May 22, 2019)
`2005 Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 15 Submitted to TSMC on January 17, 2012
`2006 Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 16 Submitted to TSMC on January 17, 2012
`2007 Excerpted Screenshots from Qualcomm Tapeout Manager Program
`Documenting Submission of QPTC20_1T Test Chip to TSMC
`2009 Presentation by Chock Gan dated January 5, 2012 titled "20SOC
`QPTC20_1T Consolidated module DRC Waiver Request"
`2010 E-mail from Dr. Yang dated January 19, 2012 Documenting Completion
`of QPTC20_1T Tapeout and Summarizing Design Team
`Accomplishments
`2011A E-mail dated February 15, 2012 from R. Bucki to Dr. Yang
`Summarizing CPU1 Test Modules with Continuous OD Test Structures
`in DUTs 13-16
`2011B Attachment to E-mail in Exhibit 2011A named "QPTC20_1T CPU1
`documentation-Feb.15th-2012.xlsx"
`2011C Attachment to Email in Exhibit 2011A named "QPTC20_1T_CPU1
`documentation-02152012.pptx"
`2012 Calendar Appointments and Agendas from Dr. Nallapati for Weekly
`Calls between Qualcomm and TSMC regarding QPTC20_1T and 20
`Nanometer Technology Development from February 27, 2012 through
`September 27, 2012
`2014A E-mail dated April 17, 2012 to Qualcomm 20 nanometer Team Leads
`with Finalized Test Plan and Overview of Testplan for Evaluating
`QPTC20_1T Test Chips
`2014B Attachment to Email in Exhibit 2014A named "QPTC20_1T TSMC
`testplan overview.pptx"
`2014C Attachment to Email in Exhibit 2014A named
`"qptc20_1T_test_plan_v1p0_04162012.xls"
`2015 Presentation from TSMC dated May 24, 2012 Summarizing Status of
`QPTC20_1T Fabrication and Testing
`2016A Images of Lead Lot (N96Y08) QPTC20_1T Test Chip Samples
`Analyzed with TEM in Ex. 2016B
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`2016B Transmission Electron Microscope Images of CPU1 DUT16 Structures
`in the Lead Lot (N96Y08) QPTC20_1T Test Chip Samples
`2016C Excerpted Screenshots regarding QPTC20_1T Test Chip Module CPU1
`DUT 16 Analyzed with TEM in Ex. 2016B
`2017 E-mail Thread from March 30, 2012 through September 24, 2012
`containing Agendas for Weekly Call Meetings over that Period
`2018 TSMC Summary of QPTC20_1T Status dated June 28, 2012
`2019 E-mail from TSMC Regarding Cancellation of Weekly Joint
`Qualcomm-TSMC Development Call in Observence of US National
`Holiday on July 4, 2012 dated July 3, 2012
`2020 TSMC Summary of QPTC20_1T Status dated July 12, 2012
`2021 Internal Qualcomm E-mail Thread Confirming Receipt of QPTC20_1T
`testing data from TSMC on July 13, 2012
`2022A E-mail from Dr. Yang Assigning Responsibility to Qualcomm Team for
`Analyzing Testing Data for QPTC20_1T Received from TSMC dated
`July 13, 2012
`2022B Attachment to Exhibit 2022B containing N96Y08 Lot Test Data named
`"Copy of N96Y08 QPTC20 Device data-working on by Frank Yang.xls"
`2023 E-mail from Mr. Sy to Qualcomm 20 Nanometer Team Members dated
`July 14, 2012 Summarizing Weekly Meeting Held on July 13, 2012
`2024 E-mail from Dr. Nallapati to 20 Nanometer Development Team
`regarding Status of 20 Nanometer Chips with TSMC dated July 14,
`2012
`2025 E-mail with Attachment from Dr. Nallapati to TSMC and Mr. Sy dated
`July 19, 2012
`2026 TSMC Summary of QPTC20_1T Status dated July 19, 2012
`2027A E-mail thread between TSMC, Dr. Nallapati, Mr. Sy, and others
`between July 18, 2012 and August 22, 2012 discussing missing test
`data, debugging, and re-testing related to TSMC's July 13, 2012
`QPTC20_1T tests and status of back up wafers to first lot
`2027B Attachment to E-mail dated August 22, 2012 in Exhibit 2027A Defining
`revised QPTC20_1T Test Plan
`2028A E-mail from Qualcomm to TSMC and Dr. Nallapati Providing Shipping
`Instructions of QPTC20_1T Test Chips
`2028B Attachment to Exhibit 2028A containing QPTC20_1T Test Chip Build
`Plan
`2029 E-mail thread between TSMC, Dr. Nallapati, Mr. Sy, and others
`between July 18, 2012 and July 27, 2012 discussing re-testing related to
`TSMC's July 13, 2012 QPTC20_1T tests and Shipment of First Lot
`
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`(N96Y08) of QPTC20_1T to Qualcomm.
`2030 E-mail from Dr. Yang regarding Data Summary and Remaining Action
`Items for First Lot QPTC20_1T Silicon dated July 25, 2012
`2031 TSMC Summary of QPTC20_1T Status dated July 26, 2012
`2032 E-mail from Dr. Nallapati dated July 30, 2012 Summarizing Status and
`Action Items after July 25, 2012 Joint Call between Qualcomm and
`TSMC
`2034 E-mail Discussion between Qualcomm and TSMC dated July 31, 2012
`through August 2, 2012 Rescheduling Qualcomm-TSMC Joint Joint
`Call for August 2, 2012 after Cancellation on August 1, 2012 Due to
`Typhoon
`2035 TSMC Summary of QPTC20_1T Status dated August 1, 2012
`2036 Testing Data for One QPTC20_1T Test Chip Wafer from Lot ID
`N97H63 dated August 1, 2012
`2037 E-mail from Dr. Nallapati to 20 Nanometer Development Team dated
`August 7, 2012 Summarizing Internal Qualcomm Meeting Held on
`August 3, 2012 to Discuss Plan of Record and Design Rules for
`Continued Development of 20 nanometer Chipsets
`2038 Spreadsheet dated August 8, 2012 Containing TSMC Re-Test Data for
`QPTC20_1T Ring Oscillator Test Modules from Original N96Y08 Lot
`2039 E-mail from Dr. Yang Assigning Responsibility to Qualcomm Team for
`Analyzing Testing Data for QPTC20_1T Lot ID N97H63 Received
`from TSMC dated August 8, 2012
`2040 Testing Data for QPTC20_1T Test Chips from Lot ID N97H63 dated
`August 8, 2012
`2041 E-mail Thread between Dr. Nallapati and TSMC beginning August 13,
`2012 and ending August 23, 2012 discussing Alignment of 20
`nanometer Design Rules and Consistency of Test Results for
`QPTC20_1T Testing between Qualcomm and TSMC Testing
`2043 TSMC Summary of QPTC20_1T Status dated August 16, 2012
`2044 Testing Data for QPTC20_1T Test Chips from Lot ID N97H65 dated
`August 23, 2012
`2045 Internal E-mail to Qualcomm 20 nanometer Development Team
`Summarizing Status for Work Week 34 dated August 24, 2012
`2046 E-mail from Dr. Nallapati dated August 27, 2012 Summarizing Status
`and Action Items after August 22 and August 24, 2012 Joint Calls
`between Qualcomm and TSMC
`2047 E-mail thread between Dr. Nallapati and TSMC containing Weekly
`Joint Call Agendas from April 2, 2012 through August 28, 2012
`
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`including discussions of the August 28, 2012 Agenda dated August 29,
`2012
`2048 E-mail from Mr. Sy to TSMC and Dr. Nallapati regarding Receipt of
`Re-Test Data for QPTC20_1T Lot ID N97H65 (DOE Lot) dated August
`30, 2012
`2049 Internal E-mail to Qualcomm 20 nanometer Development Team
`Summarizing Status for Work Week 35 dated August 31, 2012
`2050 Internal E-mail to Qualcomm 20 nanometer Development Team from
`Dr. Nallapati Summarizing Status of work with TSMC for Work Week
`35 dated August 31, 2012
`2051 E-mail from Dr. Nallapati dated September 1, 2012 Summarizing Status
`and Action Items after August 29, 2012 Joint Calls between Qualcomm
`and TSMC
`2052 E-mail Correspondence between Qualcomm and TSMC dated
`September 4, 2012 Reporting Completion of Re-test for Back Up Lead
`Lot Wafers (N97H63) and DOE Lot Wafers (N97H65) using updated
`Test Plan
`2053A E-mail Thread between Qualcomm and TSMC from July 23, 2012 until
`September 7, 2012 regarding Shipment of QPTC20_1T Test Chips from
`TSMC to Qualcomm
`2053B Attachment to E-mail in Exhibit 2053A named "Jan 2012 20nm QPTC
`Build Plan Rev 3 120906.xlsx"
`2053C Attachment to E-mail in Exhibit 2053A named "U33912094259.txt"
`Containing Shipment Details for 62 Chips from QPTC20_1T Lot
`N97H65
`2054 E-mail dated September 13, 2012 Documenting Minutes from Internal
`Qualcomm Meeting on September 12, 2012 discussing Development of
`Qualcomm Chips Code Named "Krait" and 20 nanometer Chips Called
`"20SOC"
`2055 Calendar Appointment from Dr. Nallapati Titled "20nm Internal
`Design-Tech Sync" dated September 14, 2012
`2056A Qualcomm Presentation titled "20SoC - QPTC-1T Si Ring Oscillator
`Data" dated September 14, 2012
`2056B Native PowerPoint File for Ex. 2056A titled "20SoC - QPTC-1T Si
`Ring Oscillator Data" dated September 14, 2012, last modified
`September 21, 2012
`2057 Qualcomm In-House Test Results for QPTC20_1T Test Chips Created
`August 15, 2012 and Last Modified September 18, 2012
`2058 E-mail thread between Dr. Nallapati and Mr. Bucki at Qualcomm
`
`
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`between September 4, 2012 and September 5, 2012 regarding Review of
`QPTC20_1T DUTs 15 and 16
`2060 Declaration of Dr. Giridhar Nallapati
`2061 Declaration of Dr. John Zhu
`2062 Declaration of Dr. Bin Yang
`2063 Declaration of Dr. Lavakumar Ranganathan
`
`C. Grounds on which Inter Partes Review has been Instituted
`I understand that Inter Partes Review has been instituted for claims 1-5, 8-
`23.
`
`10, and 12-20 (the “Challenged Claims”) in the ’1460 Proceeding. I understand
`
`that the four grounds on which Inter Partes Review has been instituted are:
`
`(1A) claims 1-3, 5, 8, 9, 12-14, and 16-19 of the ’418 Patent as allegedly
`
`anticipated in view of Rashed alone;
`
`(1B) claims 1-3, 5, 8, 9, 12-14, and 16-19 as allegedly obvious in view of
`
`Rashed alone;
`
`(1C) claims 4, 15, and 20 as allegedly obvious in view of Rashed in view of
`
`Lu; and
`
`(1D) claim 10 as allegedly obvious in view of Rashed in view of Nauta.
`
`24.
`
`I understand that all asserted Grounds rely on Rashed.
`
`D. Legal Principals
`I understand that for a prior art reference to anticipate a claim, elements of a
`25.
`
`claim must be disclosed within the reference either expressly or inherently. For a
`
`claim element to be inherent in a reference, I understand that the claim element
`
`
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`10
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`must be necessarily present in the reference. I also understand that the reference
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`must clearly and unequivocally disclose the claimed invention or direct those
`
`skilled in the art to the invention without any need for picking, choosing, and
`
`combining various disclosures not directly related to each other by the teachings of
`
`the cited reference.
`
`26.
`
`I understand that a claim may be written in functional language by reciting a
`
`means for performing a function. For a claim written this way to be anticipated, I
`
`understand that a prior art reference must disclose the identical function as stated in
`
`the claim.
`
`27.
`
`I understand that for a combination of prior art references to render a claim
`
`prima facie obvious, all elements of that claim must be disclosed in the references
`
`that make up the combination.
`
`28.
`
`I understand that a patent claim is unpatentable if it is obvious over the prior
`
`art, i.e., if a person of ordinary skill in the art at the time of the invention would
`
`have viewed the claimed invention as obvious. Obviousness may be shown by
`
`considering more than one item of prior art in combination with others or based on
`
`a single prior art reference in combination with the general state of the art.
`
`However, a claim is not rendered obvious merely because the various limitations of
`
`the claim can be found piecemeal in the prior art.
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`
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`29.
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`I understand that obviousness requires a conclusion that a person of ordinary
`
`skill in the art at the time of the invention would have had some reason to combine
`
`the piecemeal prior art in some way that would lead to the subject matter claimed
`
`in the patent. I further understand that there must be a clear articulation of the
`
`reason or reasons why the claimed invention would have been obvious. I
`
`understand that some rationales that may support a conclusion of obviousness
`
`include: (A) Combining prior art elements according to known methods to yield
`
`predictable results; (B) Simple substitution of one known element for another to
`
`obtain predictable results; (C) Use of known technique to improve similar devices
`
`(methods, or products) in the same way; (D) Applying a known technique to a
`
`known device (method, or product) ready for improvement to yield predictable
`
`results; (E) “Obvious to try” – choosing from a finite number of identified,
`
`predictable solutions, with a reasonable expectation of success; (F) Known work in
`
`one field of endeavor may prompt variations of it for use in either the same field or
`
`a different one based on design incentives or other market forces if the variations
`
`are predictable to one of ordinary skill in the art; (G) Some teaching, suggestion, or
`
`motivation in the prior art that would have led one of ordinary skill to modify the
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`prior art reference or to combine prior art reference teachings to arrive at the
`
`claimed invention.
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`30.
`
`I understand and have been instructed that claim construction is a matter of
`
`law to be performed by the court. I further understand and have been instructed
`
`that claim terms should be construed as one of ordinary skill in the art would have
`
`understood them in light of the surrounding claim language, other claims, the
`
`specification, and its file history, which are generally referred to as intrinsic
`
`evidence. I also understand and have been instructed that cited references are
`
`considered intrinsic evidence. I also understand and have been instructed that
`
`extrinsic evidence, which is evidence outside of the file history, such as
`
`dictionaries and technical articles, may be relied upon to, for example, show how
`
`one skilled in the art would have understood the claim language at the time of the
`
`invention.
`
`31.
`
`I understand that the broadest reasonable interpretation (“BRI”) standard
`
`applies for interpreting claim terms in this IPR proceeding, which means claim
`
`terms generally are given their ordinary and customary meaning, as would be
`
`understood by a person of ordinary skill in the art in the context of the entire
`
`disclosure.
`
`32.
`
`I understand that it is not reasonable to interpret individual words of a claim
`
`without considering the context in which those words appear. I also understand
`
`that it is the use of a particular claim term in the context of the written description
`
`
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`13
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`and by those of skill in the art that correctly reflects both the “ordinary” and
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`“customary” meaning of the term in the claims.
`
`Level of Ordinary Skill in the Art
`E.
`33. The ’418 Patent was filed on March 14, 2013. I understand that the ’418
`
`Patent may have been conceived by no later than January 17, 2012. I consider the
`
`time of the invention to be no later than January 17, 2012. However, I do not
`
`believe there is any difference in the knowledge of a person of ordinary skill in the
`
`art between January 17, 2012 and March 14, 2013. Accordingly, my opinion
`
`presented in this declaration is the same regardless of whether the date of the
`
`invention is January 17, 2012 or March 14, 2013.
`
`34.
`
`In my opinion, a person of ordinary skill in the art relevant to the ’418 Patent
`
`at the time of its invention would have had (a) a Bachelor’s of science degree in an
`
`engineering discipline or physics, or a closely-related field, and at least two years
`
`of work or research experience in the field of semiconductor design or fabrication,
`
`or (b) a Master’s of science degree in an engineering discipline or physics, or a
`
`closely-related field, and at least one year of work or research experience in that
`
`same field. At the time of the invention of the ’418 Patent, I was at least a person
`
`of ordinary skill in the art relevant to the ’418 Patent.
`
`35.
`
`I note that the Liu Declaration defines a person of ordinary skill in the art as
`
`having a Master’s of Science Degree (or a similar technical Master’s Degree, or
`
`
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`higher degree) in an academic area emphasizing electrical engineering or computer
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`engineering with a concentration in semiconductors or, alternatively, a Bachelors
`
`Degree (or higher degree) in an academic area emphasizing electrical or computer
`
`engineering and having two or more years of experience in integrated circuit
`
`design and/or semiconductor processing.
`
`36. To the extent there are any differences in these two definitions of a person of
`
`ordinary skill in the art, I do not believe that there is a meaningful change of
`
`outcome using one definition of a person of ordinary skill in the art or the other.
`
`Brief Overview of the ’418 Patent
`F.
`37. The ’418 Patent describes arrangements of semiconductor structures to
`
`improve interconnect and transistor densities in circuit layouts. See, e.g., APPLE-
`
`1001 at 1:6-8; 5:2-3; 5:66-6:3; 6:67-7:8. In particular, the ’418 Patent describes
`
`interconnect structures between transistor structures on a chip to maximize
`
`transistor density. Compare id. at 2:16-18 to 5:2-3. Adjacent transistors are
`
`isolated from one another with a blocking transistor that may be biased to ground
`
`or to a supply voltage. Id. at 5:54-57; 6:23-31. The gate of the blocking transistor
`
`is separated from the gate of each adjacent transistor according to a gate layer
`
`pitch. Id. at 5:54-57. To implement and bias the blocking transistor, the ’418
`
`Patent discloses a novel routing scheme for biasing the blocking transistor gate that
`
`utilizes local interconnect structures, located between the lower-most metal layer
`
`
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`and the underlying semiconductor substrate, to tie the gate of the blocking
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`transistor to the source of an adjacent transistor that is tied to ground or to a supply
`
`voltage. Id. at Figs. 4A and 4B and 6:30-7:3. This eliminates the need to extend
`
`the gate of the blocking transistor to independently connect the blocking
`
`transistor’s gate to ground or to a supply voltage using a separate via (contact
`
`hole). Id. That is, this arrangement eliminates the previously-required elements
`
`shown in dotted line at the top of Figure 4A (provided below, with annotations in
`
`red corresponding to claim 1), thereby reducing the cell-height of the circuit layout
`
`to allow rows of circuits to be spaced closer together.
`
`
`
`16
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`38.
`
`I have reviewed each of claims 1-5, 8-10, and 12-20 of the ’418 Patent that
`
`Petitioner is challenging in its petition.
`
`G. Claim Construction
`i. Means for Coupling the Gate-Directed Local Interconnect to the
`Third Gate Layer
`I understand that Petitioner and Patent Owner agreed that the corresponding
`
`39.
`
`structure for the “means” is “a diffusion-directed local interconnect as described at
`
`7:8-12, Fig. 4A, 3:9-14, Fig. 4B, 3:15-19, 7:12-16, 5:62-64, 6:36-39, 8:9-11, 2:48-
`
`52, Figs. 5A, 5B, 6A, 7A, or 7B, and equivalents thereof.” See EX2001 at 26-28.
`
`40. A person of ordinary skill in the art would readily understand that for each
`
`corresponding structure of the diffusion-directed local interconnect described at the
`
`portions of the ’418 Patent cited above, the diffusion-directed local interconnect—
`
`and the diffusion-directed local interconnect alone—performs the claimed
`
`function.
`
`41. As one example from the portions of the ’418 Patent cited above, FIG. 4B of
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`the ’418 Patent (provided immediately below) shows a diffusion-directed local
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`interconnect 450 that is arranged so as to directly contact gate layer 425 and gate-
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`directed local interconnect 435.
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`42. Thus, as I understand the ’418 Patent, the only diffusion-directed local
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`interconnect structures described in the portions of the ’418 Patent cited above that
`
`perform the function of “coupling the gate-directed local interconnect to the third
`
`gate layer” are diffusion-directed local interconnects that alone perform the
`
`claimed function. Stated differently, none of the diffusion-directed local
`
`interconnects of the ’418 Patent rely upon other structures, for example an
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`intermediate connection such as a “via” (or contact hole), to couple to either a gate-
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`directed local interconnect or gate layer.
`
`ii.
`
`“First Gate Layer For The Second Transistor To A Power Supply
`Node”
`43. Claim 5 includes an obvious typographical error in that the phrase “first gate
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`layer for the second transistor” would be readily understood by a person of
`
`ordinary skill in the art as “first gate layer for the blocking transistor.” Claim 2,
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`
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`from which claim 5 depends, provides the previous basis for claim 5 and states that
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`“the first gate layer comprises a gate for a blocking transistor.” APPLE-1001,
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`9:20-21. Claim 2 also recites an “adjacent second transistor,” that is therefore not
`
`the same as the “blocking transistor.” Id., 9:26. Claim 2, and not the
`
`typographical error in claim 5, is consistent with the specification.
`
`H. Test Structure Embodying the Invention of the ’418 Patent
`I understand that a Qualcomm test chip known as QPTC20_1T contains a
`44.
`
`test device known as “Device Under Test” (“DUT 16”). EX2060, ¶4; EX2061, ¶4;
`
`EX2062, ¶¶2, 4. I also understand that the structures of DUT 16, as taped out, are
`
`described in a GDS file named “qptc20_1t_top_fill_no215_20120117.gds.gz” and
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`dated January 17, 2012. EX2060, ¶7, 109-112; EX2061, ¶¶7, 73-76; EX2062, ¶¶6-
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`8, 58-63. GDS files like that shown in EX2006 are used to guide fabrication of
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`semiconductor devices, such as the structures illustrated in EX2006.
`
`45.
`
`I have reviewed the excerpts of the QPTC20_1T GDS file contained in
`
`EX2006. I have reviewed the declarations of Drs. Giridhar Nallapati (EX2060)
`
`and John Zhu (EX2061) describing the portion of the GDS file excerpted in
`
`EX2006.
`
`46.
`
`I have reviewed Transmission Electron Microscope (“TEM”) images of the
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`QPTC20_1T test chip provided in EX2016B along with the corresponding GDS
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`screenshots provided in EX2016C that correlate with structures shown in
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`
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`EX2016B. I have reviewed the declaration of Dr. Lavakumar Ranganathan in
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`EX2063 that includes a description of Exs. 2016B and 2016C. I have reviewed
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`Exs. 2016A-C.
`
`47. DUT 16 in the January 17, 2012 GDS file contains multiple instantiations of
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`the circuit structures described in the ’418 patent, some PMOS and some NMOS,
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`and is known internally within Qualcomm as “MP over OD.” EX2006, ¶¶4, 75-77;
`
`EX2060, ¶¶4, 38-41; EX2061, ¶2. The TEM images of DUT 16 prove that the
`
`claimed structures of the ’418 Patent were actually present in the QPTC20_1T
`
`samples that include DUT 16 and that were fabricated through Metal Layer M6 by
`
`June 28, 2012. The GDS layers that I map below for each claim element are also
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`found in the GDS images in EX2016C that were used to correlate physical
`
`structures in the QPTC20_1T samples that were imaged in EX2016B. See
`
`EX2063, ¶¶27-56 (describing the location of each of the structures I’ve mapped
`
`below in the context of EX2016B and EX2016C). Based on my review of these
`
`materials, all of the claimed structures described below in reference to EX2006 are
`
`also present in the TEM images in EX2016B and the GDS screenshots in
`
`EX2016C that Qualcomm’s FA Group used to generate the TEM images in
`
`EX2016B. Thus, DUT 16 and the corresponding claim structures discussed below
`
`are not only included in the original QPTC20_1T GDS file dated January 17, 2012,
`
`but they are also present in physical QPTC20_1T samples that were fabricated
`
`
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`through Metal Layer 6 by June 28, 2012. See EX2060, ¶¶4, 144-146; EX2061,
`
`¶¶4, 107-109; EX2062, ¶¶2; EX2063, ¶¶27-56; EX2018, 2/2. As detailed below,
`
`DUT 16 of the QPTC20_1T test chip embodies the invention disclosed in the ’418
`
`Patent.
`
`Elements [1.1], [12.1], and [17.1]1
`i.
`48. DUT 16 includes a circuit. Annotations of page 9 of EX2006 provided
`
`below label a circuit in white as the claimed circuit of claims 1 and 17. EX2006,
`
`9/21. The GDS file that includes DUT 16 contains hundreds of layers that
`
`correspond to a fabrication process/method for forming the circuit. Thus, the GDS
`
`file that includes DUT 16 provides a method for forming the circuit of claim 12.
`
`This same circuit is shown in FIG. 4B of the ’418 Patent.
`
`
`
`Annotated EX2006, 9/21
`
`APPLE-1001, FIG. 4B
`
`
`
`
`
`
`1 The element references (e.g., [1.1], [12.1], etc.) used herein correspond to the
`
`element references used by Petitioner in the Petition.
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`
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`Elements [1.2] and [12.2]
`ii.
`49. Layer 17 of DUT 16 includes a first gate layer arranged according to a gate
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`layer pitch between a second gate layer and a third gate layer. EX2006, 4/21, 9/21.
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`The gate layers are formed over a semiconductor substrate. EX2060, ¶¶72, 81-84;
`
`EX2061, ¶¶36, 45-48; EX2006, 4/21. Annotations of page 9 of EX2006 provided
`
`below label three gate layers in red as the claimed first, second, and third gate
`
`layers, respectively, of claims 1 and 12, and identify in orange the fixed gate pitch
`
`separating the three gate layers. EX2006, 4/21, 9/21. These same first, second,
`
`and third gate layer structures separated by a gate layer pitch are shown in
`
`annotated FIG. 4B of the ’418 Patent as elements 425, 415, and 410, respectively.
`
`
`
`
`
`
`
`EX2006, 12/21
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`3rd
`
`1st
`
`2nd
`
`3rd
`
`1st
`
`2nd
`
`gate
`pitch
`
`
`
`Annotated EX2006, 9/21
`
`
`
`Annotated APPLE-1001, FIG. 4B
`
`iii. Elements [1.3], [1.4], [12.3], and [12.4]
`50. Layer 84.5 of DUT 16 includes a first gate-directed local interconnect
`
`arranged between the first gate layer and the second gate layer and a second gate-
`
`directed local interconnect arranged between the first gate layer and the third gate
`
`layer. EX2006, 6-7/21, 9/21. Annotations of page 9 of EX2006 provided below
`
`label two MD2 interconnects in blue as the claimed first and second gate-directed
`
`local interconnects, respectively, of claims 1 and 12 arranged as recited in elements
`
`[1.3], [1.4], [12.3], and [12.4]. EX2006, 6-7/21, 9/21. These same first and second
`
`gate-directed local interconnects are shown in annotated FIG. 4B of the ’418 Patent
`
`as elements 435 and 440, respectively.
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`
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`EX2006, 12/21
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`
`
`2nd
`
`1st
`
`1st
`
`2nd
`
`Annotated EX2006, 9/21
`
`
`
`Annotated APPLE-1001, FIG. 4B
`
`
`
`
`
`iv. Elements [1.5] and [12.5]
`51. Layer 84.2 of DUT 16 includes a diffusion-directed local interconnect layer
`
`configured to couple the first gate layer to one of the first and second gate-directed
`
`local interconnects. EX2006, 8-9/21. Annotations of page 9 of EX2006 provided
`
`below label an MP interconnect in yellow as the claimed diffusion-directed local
`
`interconnect of claims 1 and 12 configured to couple the first gate layer (labeled in
`
`red) to the first gate-directed local interconnect (labeled in blue) as described in the
`
`’418 Patent, with the top and bottom boundaries of the footprint of the diffusion
`
`
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`24
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`Page