`
`In re Patent of:
`U.S. Patent No.:
`Issue Date:
`Appl. Serial No.:
`Filing Date:
`Title:
`
`Yasuharu Hosaka et al.
`9,298,057 Attorney Docket No.: 12732-1925IP1
`March 29, 2016
`13/939,323
`July 11, 2013
`DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING
`THE DISPLAY DEVICE
`
`DECLARATION OF Michael Lebby, Ph.D.
`
`I, Michael Lebby, Ph.D., of San Francisco, CA, declare that:
`
`QUALIFICATIONS AND BACKGROUND INFORMATION
`
`1.
`
`I am currently the CEO of Oculi LLC and the CEO & Director of
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`Lightwave Logic. Oculi LLC is my consulting company where I undertake my
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`expert witness work. Lightwave Logic is a technology company based in Denver,
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`Colorado that is developing optical polymers for fiber optic communications. I
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`have testified as an expert witness and consultant in patent and intellectual
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`property litigation as well as inter partes reviews and re-examination proceedings.
`
`My curriculum vitae is provided (as SEL2002).
`
`2.
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`I also serve as a Technical Expert/Consultant for the Photonics Unit of
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`the European Commission. My role is to advise the European Commission in
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`matters that are photonics technology based that have included for example:
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`displays, fiber optic communications, sensing, medical, and biological
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`applications.
`
`1
`
`SEL 2001
`Bluehouse v. SEL
`IPR2018-01405
`
`
`
`3.
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`I received a Bachelor of Electrical Engineering degree in 1984, a
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`Master of Business Administration in 1985, and a Doctorate degree in 1987, all
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`from University of Bradford in the United Kingdom. My Ph.D. thesis involved the
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`design and fabrication of both optoelectronic and electronic semiconductor
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`devices, and their associated characterization. In 2004, I was awarded a Doctor of
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`Engineering degree from University of Bradford for my technical contributions to
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`the field, with citation to “Technical Contributions to Optoelectronics.”
`
`4.
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`As described in my curriculum vitae (attached as SEL2002), I have
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`over 30 years of experience in the field of optoelectronics, photonics, and
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`electronic engineering including extensive experience in the research,
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`development, fabrication, and manufacture of semiconductor devices, organic
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`technology, and associated packaging for optical applications such as fiber optic
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`links, general lighting, displays, sensing, etc.
`
`5.
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`My career started in the late 1970s at the Ministry of Defense in UK
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`where I spent time at their R&D facility in Malvern (RSRE – Royal Signals and
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`Radar Establishment). I worked on semiconductor device design, fabrication, and
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`characterization. My research work in semiconductor device design then took me
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`to AT&T Bell Laboratories in 1985 where I pursued research in novel device
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`designs using III-V semiconductor material systems. The devices researched
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`became the subject of my Ph.D. thesis that was granted in 1987.
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`2
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`
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`6.
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`I moved to Motorola in 1989 to further develop my semiconductor
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`engineering and packaging skills and became a Research and Development
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`Manager for Motorola in the photonics division until I left the company in 1998.
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`During my time at Motorola, I worked on many electronic and photonic
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`technology projects that included optical interconnects, displays, LEDs, LCDs,
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`lasers, detectors, opto-couplers, integrated circuits (analog and digital), etc., as well
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`as the packaging and reliability of mobile prototypes. At that time, I was
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`particularly interested in miniature displays using a number of technologies such as
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`LEDs, lasers, LCDs, and organic LEDs. I also worked with driver and receiver
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`based integrated circuits. I collaborated with Motorola’s mobile division on new
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`and novel display prototypes, and patented a number of new concepts that include
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`an electronic book, electronic wallet, spectacle/eyeglass and binocular based
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`mobile phone designs. I also patented a new semiconductor laser that had potential
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`to be manufactured in high volume. This device was called a VCSEL (vertical
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`cavity surface emitting laser), and is now the basis for the highest volume
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`semiconductor laser today with its recent implementation into Apple’s new iPhone
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`Face ID system. I also initiated Motorola’s work in optical interconnect
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`(Optobus™) and was involved in the IC chip designs that this parallel interconnect
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`module utilized. During this period, I was one of Motorola’s most prolific
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`inventors, having over 150 issued utility patents as author or co-author. Many of
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`3
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`
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`the photonics prototypes were subjected to reliability and stress testing that
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`included humidity, temperature, optical, mechanical, and electrical evaluation.
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`7.
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`Between 1998 and 1999, I worked as the Director of Technology/ BD
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`(Fiber Optics) for Tyco Electronics (previously AMP). I joined Tyco Electronics
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`as a member of the Global Optoelectronics Division’s management team. There, I
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`was responsible for growing the optoelectronics business through external
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`interactions that include mergers, acquisitions, strategic alliances, and technical
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`strategic planning. Much of that work was photonics based that included designing
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`and characterizing photonics-based modules for customer qualification
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`specifications.
`
`8.
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`In 1999, I left Tyco and started employment at Intel. At Intel, I was
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`involved heavily in photonic technology and especially those that supported silicon
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`photonic device platforms. As a culmination of this work, I was one of Intel’s
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`founders of its silicon photonics division in the year 2000, and worked to set up a
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`design facility in South San Jose, California. The work looked at integrating
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`silicon FET electronics with optoelectronics onto the same silicon semiconductor
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`wafer. I was also part of Intel Capital’s optical investment team, and participated
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`on over 30 photonics investments into photonics that included displays and liquid
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`crystal on silicon (LCOS). Technologies invested included detectors, lasers,
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`LEDs, LCDs, and displays.
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`4
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`
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`9.
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`In 2001, I founded a fiber optics transceiver company called Ignis
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`Optics that developed and manufactured high speed fiber optic transceivers.
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`Included in the design were micro-controllers as well as standard integrated circuit
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`technology that was designed to both transmit and receive fiber optic data signals.
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`10.
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`In 2005, I took up employment with a trade association called OIDA
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`based in Washington DC. As head of this trade association, and with photonics
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`manufacturers that included fiber optics, display, sensing, defense, aerospace,
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`lighting, and automotive vendors as members, I was responsible in part for
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`industry-based technology roadmaps and implemented common industry roadmap
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`methodologies with common features such as “Red Brick Walls” and transferred
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`them into optoelectronics roadmaps for the industry where displays were featured.
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`11.
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`In 2010, I became the General Manager and CTO of Translucent, Inc.,
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`a high-tech start-up company which developed and manufactured silicon and rare
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`earth oxide based epitaxial semiconductor wafers. One of the key drivers at
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`Translucent was to develop a new and novel platform for the growth of GaN and
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`InGaN onto silicon for low cost LED as well as power FET manufacturing.
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`Translucent pioneered the deposition of single crystal rare earth oxides such as
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`Erbium Oxide (ErOx), Gadolinium Oxide (GdOx), Neodymium Oxide (NdOx),
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`etc., that when grown, single crystal layers of GaN/InGaN/AlN could be grown on
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`top of them. This allows a lattice-matched, and monolithic based wafer template to
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`5
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`
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`be manufactured for LED and FET fabrication. While at Translucent, I invented
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`various epitaxial semiconductor layer structures that utilized rare earth oxide
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`technology to improve the performance of LEDs and FETs. Other material growth
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`work at Translucent focused on the growth of Silicon Germanium (SiGe)
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`compounds with rare earth oxides, and various crystal orientation wafer substrates.
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`Electrical contacts to devices developed at Translucent included the use of ITO
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`(Indium Tin Oxide), Indium Oxide (IO), and other transparent conducting oxide
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`(TCO) compounds.
`
`12. As discussed in more detail in my curriculum vitae, I have continued
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`to work in the semiconductor, electronics, optoelectronics and packaging field
`
`throughout my career.
`
`13.
`
`Throughout my career I have also had an active role in a number of
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`technical, professional organizations, including, among others, IEEE Components,
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`Packaging, and Manufacturing Technology (CPMT), IEEE Electronic Components
`
`and Technology Conferences (ECTC); IEEE TC-10 (Technical Committee on
`
`Optoelectronics), and IEEE Optoelectronics Industry Development Association
`
`(OIDA). Through these organizations, I have consistently been a part of
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`committees, events, and workshops relating to semiconductor, optoelectronics,
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`electronics and packaging technology.
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`6
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`
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`14. My work has also led to over 200 utility patents in semiconductors,
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`electronics, and optoelectronics, and includes a number of patents relating to
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`photonics-based displays both from a technology platform perspective as well as a
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`packaging perspective. I am the author of more than 60 publications in the field of
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`optoelectronics.
`
`15.
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`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this declaration and could testify competently to them if asked to do so.
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`16. My compensation is in no way dependent upon or contingent upon the
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`opinions and testimony that I render during the course of this case. My findings
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`are based on my education, experience, and background in the fields discussed
`
`below.
`
`17.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the fields of
`
`electronics and photonics and my experience in working with others involved in
`
`those fields at companies such as the British Government, Motorola, AT&T Bell
`
`Labs, Intel, etc. In addition, I have analyzed the following publications and
`
`materials, in addition to other materials I cite in my declaration:
`
`
`
`
`
`
`
`IPR2018-01405 Petition for Inter Partes Review (“petition”)
`
`U.S. Patent No. 9,298,057 (“the ’057 patent”) (Ex. 1001)
`
`Declaration of Richard A. Flasck (Ex. 1003)
`
`7
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`
`
`
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`U.S. Patent Application Publication No. 2011/0109351 A1 to Shunpei
`
`Yamazaki et al. (“Yamazaki”) (Ex. 1004)
`
`
`
`U.S. Patent No. 8,169,558 B2 to Masateru Morimoto et al.
`
`(“Morimoto”) (Ex. 1005)
`
`
`
`John F. Wager et al., Transparent Electronics, Springer (2010)
`
`(SEL2004)
`
`
`
`U.S. Patent No. 6,809,390 to Takemoto Toda et al. (“Toda”)
`
`(SEL2005)
`
`
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`U.S. Patent No. 8,409,891 to Takeshi Kuriyagawa et al.
`
`(“Kuriyagawa”) (SEL2006)
`
`
`
`
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`U.S. Patent No. 8,487,308 to Noriaki Ikeda et al. (“Ikeda”) (SEL2007)
`
`S.M. Sze, Physics of Semiconductor Devices, Second Edition, John
`
`Wiley & Sons (1981) (“Sze”) (SEL2008)
`
`
`
`J.P. Colinge et al., Physics of Semiconductor Devices, Kluwer
`
`Academic Publishers (2003) (“Colinge”) (SEL2009)
`
`
`
`A Dictionary of Chemistry, 6th Ed., Oxford University Press (2008)
`
`(SEL2010)
`
`
`
`McGraw-Hill Dictionary of Scientific and Technical Terms, 6th Ed.
`
`McGraw-Hill (2003) (SEL2011)
`
`8
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`
`
`OVERVIEW OF CONCLUSIONS FORMED
`
`18.
`
`This expert Declaration explains the conclusions that I have formed
`
`based on my analysis. Based upon my knowledge and experience and my review
`
`of the IPR petition and the publications listed above, I do not believe that a
`
`POSITA would have been motivated to modify Yamazaki’s FIG. 11B embodiment
`
`to include an additional insulating layer from Yamazaki’s FIG. 15A embodiment
`
`as Mr. Flasck suggests.
`
`BACKGROUND KNOWLEDGE ONE OF SKILL IN THE ART WOULD
`HAVE HAD PRIOR TO THE PRIORITY DATE OF THE ’057 PATENT
`
`19.
`
`The technology in the ’057 patent at issue generally relates to a
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`semiconductor display device. More specifically, the ’057 patent relates to a
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`particular arrangement of semiconductor layers in both a pixel portion and a driver
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`circuit portion of a display circuit. The ’057 patent provides an arrangement of
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`inorganic and organic insulating films formed over a transistor in the pixel portion
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`and a transistor in the driver circuit portion of the device designed to prevent entry
`
`of gases and moisture into the transistors. See e.g., Ex. 1001 at 2:32-44, 7:32-41,
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`7:60-8:22. The arrangement of insulating films is particularly designed to allow
`
`gasses or moisture that are released from the organic insulating film by heating
`
`processes during fabrication of the semiconductor device to be dispersed into the
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`outside environment rather than being retained in the semiconductor structure. Id.
`
`9
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`
`
`20. Based upon my knowledge and experience in this field and my review
`
`of the ’057 patent and the references cited above, I believe that a person of
`
`ordinary skill in the art at the time of the invention (“POSITA” or “person of
`
`skill”) would have had at least a bachelor of science or engineering degree in
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`electrical engineering, semiconductor technology, physics, or a related field, and
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`either an advanced degree (such as a master’s degree) or an equivalent amount of
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`work experience, i.e., 2-3 years, in an area relating to semiconductor design and/or
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`fabrication, liquid crystal display (“LCD”) design or fabrication, electrical
`
`engineering, or a related technical field. Additional education might substitute for
`
`some of the experience and substantial experience might substitute for some of the
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`educational background. My analysis is thus based on the perspective of a
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`POSITA having at least this level of knowledge and skill in the time leading up to
`
`the ’057 patent. I have been informed that the priority date of the ’057 patent is
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`July 20, 2012, and I have applied this timeframe in my analysis as being the
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`relevant time of the ’057 patent.
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`21. Based on my experiences, I have a good understanding of the
`
`capabilities of a POSITA. Indeed, I have participated in organizations and worked
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`closely with many such persons over the course of my career. Furthermore, I have
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`hired a number of times engineers (electrical, mechanical, chemical/chemistry,
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`physics, computing, software, etc.) with Bachelors, Masters, and Doctoral degrees.
`
`10
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`
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`I have at times during the course of my career, hired engineers on behalf of my
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`employer who have demonstrated specific job experience that would count in place
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`of post-graduate education.
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`22.
`
`I am well qualified in the semiconductor and display technologies
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`related to the ’057 Patent and I was a person of at least ordinary skill in the art in
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`the ’057 timeframe.
`
`A POSITA Would Not Have Considered Yamazaki’s Pixel Electrode Layer
`4030 to be a “Metal Pixel Electrode”
`
`23.
`
`It is my opinion, that Yamazaki does not provide a rational basis upon
`
`which a POSITA would have concluded that pixel electrode layer 4030 was
`
`formed from metal. Yamazaki describes two classes of materials for use as pixel
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`electrode layer 4030, neither of which would have been considered to be metal by
`
`a POSITA. In paragraph 305, Yamazaki states that pixel electrode 4030 “can be
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`formed using a light-transmitting conductive material” and lists several indium
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`based conductive oxides and in paragraph 306, Yamazaki states, in the alternative,
`
`that “a conductive composition including a conductive high molecule (also referred
`
`to as a conductive polymer) can be used for pixel electrode layer 4030.” Ex. 1004
`
`at ¶¶ 305, 306. I have not found any reference in Yamazaki to pixel electrode 4030
`
`being formed from a metal, or even a metal alloy.
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`11
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`
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`24.
`
`The light-transmitting conductive materials that Yamazaki lists for use
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`as pixel electrode layer 4030 in paragraph 305 are commonly referred to as
`
`transparent conductive oxides (TCOs), conductive glasses, or conductive ceramics.
`
`See, e.g., SEL2004 at 2-3; SEL2008 at 819. For clarity, I will use the term TCO
`
`when referring to this class of materials throughout this declaration. A POSITA
`
`would not have considered these materials to be metals, nor would I expect any of
`
`the engineers that have worked for me to consider TCOs to be metals.
`
`25.
`
`For example, a POSITA would have understood that, among other
`
`things, metals are materials that have “free electrons” in a conduction energy band.
`
`As Colinge explains, free electrons in metals “can leave [an] atom and move in the
`
`crystal without receiving any energy.” SEL2009 at 16. In semiconductors and
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`insulators, however, an electron will not move freely unless it first receives
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`sufficient energy to “‘jump’ from [a] valence band into [a] conduction band.” Id.
`
`at 15. In order for this to occur, the electron must receive “a significant amount of
`
`energy (equal to Eg or higher [the band gap energy]).” Id. at 16. A POSITA
`
`would have understood that, like semiconductors and unlike metals, TCOs have
`
`energy band gaps for electrons to cross, and hence, while TCOs “are considered to
`
`be ‘good’ conductors from the perspective of a semiconductor, they are actually
`
`very poor conductors compared to metals.” SEL2004 at 2, see also 3.
`
`Importantly, the energy band gap is what gives the TCOs their transparency to
`
`12
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`
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`visible light. See Id. Consequently, it is my opinion that a POSITA would have
`
`viewed TCOs as being a class of materials distinct from metals, and if anything,
`
`more similar to semiconductors than metals.
`
`26. A POSITA also would not have considered the conductive polymer
`
`materials that Yamazaki lists for use as pixel electrode layer 4030 in paragraphs
`
`306 and 307 to be metals. Furthermore, a POSITA would have understood that
`
`polymers are not metals but plastic materials formed from chains of carbon and
`
`hydrogen. For instance, two scientific dictionaries, the Oxford Dictionary of
`
`Chemistry and the McGraw-Hill Dictionary of Scientific and Technical Terms,
`
`define conducting polymers as organic carbon chains or plastic materials that
`
`conduct electricity. SEL2010 at 138; SEL2011 at 459. From these definitions, a
`
`POSITA would clearly have understood that conductive polymers are not metals.
`
`Furthermore, as noted in Yamazaki itself, the electrical conductivity of conductive
`
`polymers can be explained by their pi (π) bonds. See e.g., Ex. 1004 at ¶307.
`
`Consequently, it is my opinion that a POSITA would have viewed conductive
`
`polymers as being a class of materials distinct from metals.
`
`27.
`
`Several examples from the academic and patent literature help to
`
`demonstrate the general industry understanding that TCOs and conductive
`
`polymers are different materials from metals. In addition, these examples support
`
`my opinion that a POSITA would have recognized the TCOs and conductive
`
`13
`
`
`
`polymers disclosed by Yamazaki as being two classes of electrically conductive
`
`materials that are distinct from metals and metal alloys. For one, Wager’s
`
`textbook, identifies “TCOs as an unusual class of materials” distinct from metals.
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`SEL2004 at 2. Wager further notes that TCOs have “low conductance . . .
`
`compared to metals.” Id. at 3. Wager also states that while TCOs “are considered
`
`to be ‘good’ conductors from the perspective of a semiconductor, they are actually
`
`very poor conductors compared to metals.” Id. at 2. Moreover, Sze’s Physics of
`
`Semiconductor Devices describes TCOs such as indium oxide and ITO as
`
`“conducting glasses.” SEL2008 at 819. Wager’s textbook and Sze’s textbook
`
`would clearly have taught a POSITA that neither conductive polymers nor TCOs
`
`are considered metals.
`
`28.
`
`In addition, the Toda, Kuriyagawa, and Ikeda patents also distinguish
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`“electrically conductive oxides” from metals and metal alloys. SEL2005 at 1:66-
`
`2:5; SEL2006 at 2:1-9; SEL2007 at 4:20-54. A POSITA reading these patents
`
`would have understood that the author’s intent was to distinguish electrically
`
`conductive oxides from metals.
`
`29.
`
`Similarly, Kuriyagawa notes that in some cases it is “preferable to use
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`the light transmitting conductive film such as ITO (Indium Tin Oxide)” over metal
`
`to resist corrosion. SEL2006 at 2:7-9. In other words, a POSITA would have
`
`14
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`
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`understood from Kuriyagawa that conductive oxides such as ITO are more
`
`corrosion resistant than metals.
`
`30.
`
`In his declaration, Mr. Flasck only states that a POSITA would be
`
`motivated to add the insulating layer 7035 to Yamazaki’s Fig. 11B embodiment to
`
`prevent reactions between an organic material and impurities introduced by a metal
`
`pixel electrode. Ex. 1003 at ¶64. However, Mr. Flasck’s statement is irrelevant
`
`because, as described above, a POSITA would have understood that Yamazaki’s
`
`pixel electrode 4030 is not metal. Furthermore, a POSITA would have understood
`
`that because Yamazaki’s pixel electrode 4030 is not a metal pixel electrode in
`
`contact with the organic material of insulating layer 4021, there is no reason to be
`
`concerned about impurities from a metal pixel electrode reacting with the organic
`
`material of insulating layer 4021.
`
`A POSITA Would Not Have Been Motivated to Add an Additional Insulating
`Layer to Protect Yamazaki’s Insulating Layer 4021 From Impurities and
`Would Not Have Been Concerned that Impurities From Pixel Electrode 4030
`Would “React” With Organic Material in Layer 4021
`
`31.
`
`In paragraph 298, Yamazaki states that in the FIG. 11B embodiment,
`
`“in order to reduce the surface roughness due to the transistor and to improve the
`
`reliability of the transistor, the transistors obtained in Embodiment 1 are covered
`
`with insulating layers (insulating layers 4020 and 4021) functioning as a protective
`
`film or a planarization insulating film.” Yamazaki continues to explain that a
`
`15
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`
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`“protective film is provided to prevent entry of contaminant impurities such as an
`
`organic substance, metal, and moisture existing in the air and is preferably a dense
`
`film” (emphasis added). Ex. 1004 at ¶298.
`
`32.
`
`In standard semiconductor manufacturing, it is typical to planarize the
`
`surface of a transistor so that multi-level interconnects can be patterned for
`
`electrical connection to the transistor devices. Having a planar surface allows
`
`metal layers, insulating layers, and the like to be deposited evenly across the chip,
`
`and while acting as a platform for photolithography to create, for example, vias,
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`trenches, multi-level interconnects, and various architectures to access the
`
`transistors easily. A POSITA would look at layer 4021 and see that it is a simple
`
`planarized layer of organic material. The function of 4021 is clearly only to
`
`planarize the chip and cover the transistor in a way that allows a planar platform
`
`for further multi-level interconnect. A POSITA would not see any other function
`
`to this layer. A POSITA would look at the thickness the layer needed to be and
`
`figure out how to spin coat the wafer with the organic material so that an adequate
`
`thickness for 4021 would be applied, cured, and patterned. Furthermore, a
`
`POSITA would have understood that adding an additional layer (such as the
`
`Petitioner’s proposed additional insulating layer) to a semiconductor design would
`
`require additional processing steps including additional layer formation, masking
`
`and patterning, and etching processes. For example, these steps would be required
`
`16
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`
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`in order to create a via in the Petitioner’s proposed new insulating layer through
`
`which pixel electrode 4030 can contact either the source or drain electrode of
`
`underlying transistor 4010. Each of these additional processes increases the
`
`fabrication time for a semiconductor device and increases the risk of contamination
`
`during fabrication. This additional processing time and risk of contamination
`
`reduces fabrication throughput of a semiconductor manufacturer and can also
`
`reduce the usable product yield if contamination or processing errors lead to
`
`increased defects in the semiconductor products. Given that the function of layer
`
`4021 is clearly only to planarize the chip, a POSITA would be dissuaded from
`
`introducing the additional processing steps required to add an additional insulating
`
`layer as suggested in the petition to protect this planarization layer from impurities.
`
`33.
`
`In fact, a POSITA would have recognized, as demonstrated by Toda,
`
`that a TCO film used to form pixel electrode 4030 would already serve as an
`
`additional layer to prevent metal impurities from dissolving into layer 4021.
`
`SEL2005 at 4:49-54, 11:1-4. Toda uses an Indium Tin Oxide (ITO) film (ITO is a
`
`common TCO) to prevent contamination of a liquid crystal or an
`
`“electroluminescent material” caused by “an impurity dissolv[ing] from [a] metal.”
`
`SEL2005 at 4:49-54. Toda applies the “ITO layer” over a layer of a silver,
`
`palladium, coper metal alloy (e.g., an APC (Ag (silver), Pd (palladium), and Cu
`
`(copper)) metal alloy) to prevent “the APC from corroding and peeling, while
`
`17
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`
`
`preventing an impurity from dissolving from the [APC layer] at the same time.”
`
`SEL2005 at 11:1-4. Toda demonstrates that TCOs, such as ITO (which is also one
`
`of the TCOs listed by Yamazaki for use in forming pixel electrode 4030), can be
`
`used as protective layers to prevent metal impurities from dissolving into other
`
`layers, such as a liquid crystal layer. A POSITA would have considered
`
`Yamazaki’s pixel electrode 4030 as an added barrier of protection against
`
`impurities, rather than a cause of impurities. Therefore, a POSITA would have
`
`understood that adding yet another protective layer would have been a waste of
`
`time and resources, because Yamazaki’s pixel electrode layer 4030 formed from a
`
`TCO could serve the same purpose.
`
`34. Yamazaki teaches that insulating layer 4021 “can be formed using a
`
`heat-resistant organic material such as an acrylic resin, polyimide, a
`
`benzocyclobutene-based resin, polyamide, or an epoxy resin.” Ex. 1004 at ¶302.
`
`A POSITA would not normally have been concerned with reactions between a
`
`TCO or a conductive polymer and one of these organic materials that Yamazaki
`
`uses to form insulating layer 4021, absent some unusual conditions.
`
`35. Having a TCO or conductive polymer in direct contact with an
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`organic material would not be considered an issue in the fabrication and processing
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`of transistor-based display devices. A POSITA would look at the process traveler
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`and first give thought to the temperature of each process. This is because the
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`organic material only has limited temperature capabilities to maintain its integrity.
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`For example, if the process traveler required an anneal stage further into the
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`process, or after the addition of the organic layer, and the anneal temperature is
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`ranging say 1000 degrees Celsius, then the integrity of the organic layer would be a
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`concern. In fact, it is the integrity of the organic layer that a POSITA would be
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`more concerned with than a directly contacted electrode such as TCO.
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`Furthermore, a POSITA would not be concerned with the TCO having the
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`characteristics of impurity emission unless, the TCO was to be subjected to
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`abnormal conditions such as abnormally high temperature cycles during the
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`fabrication process. Yamazaki provides no indication that fabrication or use of its
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`device would involve such abnormal conditions.
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`LEGAL PRINCIPLES
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`Anticipation
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`36.
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`I have been informed that a patent claim is invalid as anticipated
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`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
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`is found either explicitly or inherently in a single prior art reference. Under the
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`principles of inherency, if the prior art necessarily functions in accordance with, or
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`includes the claimed limitations, it anticipates.
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`37.
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`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
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`if the claimed invention was known or used by others in the U.S., or was patented
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`or published anywhere, before the applicant’s invention. I further have been
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`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
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`patented or published anywhere, or was in public use, on sale, or offered for sale in
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`this country, more than one year prior to the filing date of the patent application
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`(critical date). And a claim is invalid, as I have been informed, under 35 U.S.C. §
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`102(e), if an invention described by that claim was described in a U.S. patent
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`granted on an application for a patent by another that was filed in the U.S. before
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`the date of invention for such a claim.
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`Obviousness
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`38.
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`I have been informed that a patent claim is invalid as “obvious” under
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`35 U.S.C. § 103 in light of one or more prior art references if it would have been
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`obvious to a POSITA, taking into account (1) the scope and content of the prior art,
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`(2) the differences between the prior art and the claims, (3) the level of ordinary
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`skill in the art, and (4) any so called “secondary considerations” of non-
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`obviousness, which include: (i) “long felt need” for the claimed invention, (ii)
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`commercial success attributable to the claimed invention, (iii) unexpected results
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`of the claimed invention, and (iv) “copying” of the claimed invention by others.
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`For purposes of my analysis above and because I know of no indication from the
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`patent owner or others to the contrary, I have applied a date of July 20, 2012, as the
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`date of invention in my obviousness analyses, although in many cases the same
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`analysis would hold true even at an earlier time than July 20, 2012.
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`39.
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`I have been informed that a claim can be obvious in light of a single
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`prior art reference or multiple prior art references. To be obvious in light of a
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`single prior art reference or multiple prior art references, there must be a reason to
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`modify the single prior art reference, or combine two or more references, in order
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`to achieve the claimed invention. This reason may come from a teaching,
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`suggestion, or motivation to combine, or may come from the reference or
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`references themselves, the knowledge or “common sense” of one skilled in the art,
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`or from the nature of the problem to be solved, and may be explicit or implicit
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`from the prior art as a whole. I have been informed that the combination of
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`familiar elements according to known methods is likely to be obvious when it does
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`no more than yield predictable results. I also understand it is improper to rely on
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`hindsight in making the obviousness determination.
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`ADDITIONAL REMARKS
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`40.
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`I currently hold the opinions set expressed in this declaration. But my
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`analysis may continue, and I may acquire additional information and/or attain
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`supplemental insights that may result in added observations.
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`41.
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`I hereby declare that all statements made of my own knowledge are
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`true and that all statements made on information and belief are believed to be true.
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`I further declare that these statements were made with the knowledge that willful
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`false statements and the like so made are punishable by fine or imprisonment, or
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`both, under Section 1001 of the Title 18 of the United States Code and that such
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`willful false statements may jeopardize the validity of the application or any
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`patents issued thereon.
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`Dated:
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`By:
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`Michael Lebby, Ph.D.
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`Tuesday, December 4, 2018
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