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`_____________________________
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`_____________________________
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`BLUEHOUSE GLOBAL LTD.
`Petitioner
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`v.
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`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
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`
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`_____________________________
`
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`CASE IPR: 2018-01405
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`U.S. PATENT NO. 9,298,057 B2
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`_____________________________
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`PETITION FOR INTER PARTES REVIEW
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`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`I.
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`Table of Contents
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`INTRODUCTION……………………………………………………. 1
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)………………………1
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))…………….1
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))……………………..1
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))………….2
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))…………………2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))……………..2
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`IV.
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`V.
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`IDENTIFICATION OF CHALLENGES……………………………3
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`BACKGROUND………………………………………………………4
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`A.
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`Technology……………………………………………………...4
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`B.
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`The ‘057 Patent…………………………………………………5
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`C.
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`Prosecution History…………………………………………….6
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`VI. PERSON OF ORDINARY SKILL IN THE ART…………………..7
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`VII. CLAIM CONSTRUCTION…………………………………………..8
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED
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`CLAIM OF THE ’057 PATENT IS UNPAENTABLE……………..9
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`A. Challenge #1: Claims 1, 3-7, 9-12 and 14-19 are
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`obvious under pre-AIA 35 U.S.C. § 103(a) over
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`Yamazaki...……………………………………………………..10
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`ii
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`1.
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`Claim 1…………………………………………………...12
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`2.
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`Claim 3…………………………………………………...31
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`3.
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`Claim 4…………………………………………………...33
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`4.
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`Claim 5..…………………………………………………. 34
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`5.
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`Claim 6…..………………………………………………. 35
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`6.
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`Claim 7..…………………………………………………. 36
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`7.
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`Claim 9..…………………………………………………. 37
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`8.
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`Claim 10.…………………………………………………38
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`9.
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`Claim 11.…………………………………………………40
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`10. Claim 12.…………………………………………………43
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`11. Claim 14.…………………………………………………46
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`12. Claim 15.…………………………………………………46
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`13. Claim 16.…………………………………………………47
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`14. Claim 17.…………………………………………………47
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`15. Claim 18.…………………………………………………48
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`16. Claim 19.…………………………………………………48
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`B. Challenge #2: Claims 2 and 13 are obvious
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`under pre-AIA 35 U.S.C. § 103(a) over Yamazaki
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`in view of Morimoto…...………………………………………..49
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`Claim 2…………………………………………………...49
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`1.
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`iii
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`Claim 13…………………………………………………. 52
`2.
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`Claim 13 .......................................................... 52
`2.
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`IX. CONCLUSION………………………………………………………. 56
`IX. CONCLUSION ................................................................ 56
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`iv
`iV
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`List of Exhibits
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`Ex. 1001 United States Letters Patent No. 9,298,057 B2
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`Ex. 1002
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`Prosecution history of U.S. Patent No. 9,298,057 B2
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`Ex. 1003 Declaration of Richard A. Flasck
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`Ex. 1004 United States Patent Application Publication No. 2011/0109351 A1
`(“Yamazaki”)
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`Ex. 1005 United States Letters Patent No. 8,169,558 B2 (“Morimoto”)
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`v
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`I.
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`INTRODUCTION
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`
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`BlueHouse Global Ltd. (“Petitioner”) hereby petitions for inter partes
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`review of claims 1-7 and 9-19 (the “challenged claims”) of U.S. Patent No.
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`9,298,057 B2 (“the ‘057 Patent”) (Ex. 1001) under 35 U.S.C. §§ 311–319 and 37
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`C.F.R. § 42. According to the assignment information on the front of the ‘057
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`Patent, and the records of the United States Patent & Trademark Office (the
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`“USPTO”), the ‘057 Patent is assigned to, and therefore owned by, Semiconductor
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`Energy Laboratory Co., Ltd. (the “Patent Owner”). For the reasons provided in
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`detail below, the challenged claims should be found unpatentable and canceled.
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
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`The real party-in-interest in this matter is Petitioner BlueHouse Global Ltd.,
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`and its parent company, Caesar Global Fund.
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))
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`As of the filing date of this Petition, Petitioner is unaware of any matters
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`involving the ‘057 Patent pending in any United States court or administrative
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`agency.
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`Lead Counsel:
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`Ryan O. White (USPTO Reg. No. 45,541)
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`TAFT, STETTINIUS & HOLLISTER LLP
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`One Indiana Square, Suite 3500
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`Indianapolis, IN 46204
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`Tel: (317) 713-3455
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`Fax: (317) 713-3699
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`Email: rwhite@taftlaw.com
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`Backup Counsel:
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`Roshan P Shrestha (No. 71,277)
`TAFT, STETTINIUS & HOLLISTER LLP
`111 East Wacker Dr. Suite 2800
`Chicago, IL 60601
`Tel: (312) 527-4000
`Fax: (312) 966-8573
`Email: rshrestha@taftlaw.com
`
`
`Philip R. Bautista (pro hac vice
`authorization requested)
`TAFT, STETTINIUS & HOLLISTER LLP
`200 Public Square Suite 3500
`Cleveland, OH 44114-2302
`Tel: (216) 706-3957
`Fax: (216) 241-3707
`Email: pbautista@taftlaw.com
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`
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))
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`Please address all correspondence to Lead Counsel at the mailing address
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`shown above. Petitioner also consents to electronic service by email.
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`
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))
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`
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`Petitioner hereby certifies that: (1) the ‘057 Patent issued on March 29, 2016
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`and so is eligible for inter partes review; (2) Petitioner has not been served with a
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`complaint alleging infringement of any of the claims of the ‘057 patent and so is
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`2
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`therefore not barred or estopped from requesting inter partes review of the ‘057
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`Patent on the grounds identified herein; and (3) Petitioner has not filed a complaint
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`challenging the validity of the ‘057 Patent. This Petition is being filed in
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`accordance with 37 C.F.R. § 42.106(a).
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`
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`IV.
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`IDENTIFICATION OF CHALLENGES
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`Petitioner asks that the Board review the accompanying prior art and
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`analysis thereof, and the supporting evidence, institute a trial for Inter Partes
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`Review of claims 1-7 and 9-19 of the ‘057 Patent, and cancel those claims as
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`invalid under 35 U.S.C. § 102 or 35 U.S.C. § 103. More specifically, Petitioner
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`requests cancellation of claims 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
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`18 and 19 of the ‘057 Patent on the following grounds:
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`
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`Challenge #1: Claims 1, 3-7, 9-12 and 14-19 are obvious under pre-AIA 35
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`U.S.C. § 103(a) over United States Patent Application Publication No.
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`2011/0109351 A1 to Yamazaki et al. (“Yamazaki”; Ex. 1004). Yamazaki was
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`published on May 12, 2011 and so is prior art to the ‘057 Patent under pre-AIA 35
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`U.S.C. § 102(b).
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`
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`Challenge #2: Claims 2 and 13 are obvious under pre-AIA 35 U.S.C.
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`103(a) over Yamazaki in view of United States Patent No. 8,169,558 B2 to
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`3
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`Morimoto et al. (“Morimoto”; Ex. 1005). Morimoto issued on May 1, 2012 and is
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`therefore prior art to the ‘057 Patent under pre-AIA 35 U.S.C. § 102(b).
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`
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`V.
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`BACKGROUND
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`A.
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`Technology
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`Semiconductor devices are electronic components that exploit the electronic
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`properties of semiconductor materials, such as silicon. Semiconductor materials
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`are useful because their behavior can be easily manipulated by the addition of
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`impurities, known as doping. Current conduction in a semiconductor occurs via
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`mobile or “free” electrons and holes, collectively known as charge carriers. Doping
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`a semiconductor such as silicon with a small proportion of an atomic impurity,
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`such as phosphorus, greatly increases the number of free electrons or holes within
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`the semiconductor (a doped semiconductor containing excess holes is called “p-
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`type”; one containing excess free electrons is known as “n-type”).
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`A thin film transistor, or TFT, is an example of semiconductor device. TFTs
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`can be used as simple ON/OFF switches in a wide variety of electrical devices,
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`such as active-matrix LCD displays. Basically, a TFT consists of a semiconductor
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`and three electrodes: (i) the gate electrode; (ii) the source electrode; and (iii) the
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`drain electrode. The gate electrode must be insulated from the semiconductor by a
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`dielectric layer (or gate insulation layer), while the drain electrode and source
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`4
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`electrode must both directly contact the semiconductor. Because of this, TFTs
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`B.
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`The ‘057 Patent
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`According to the specification, the ‘057 Patent relates to a display device
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`using a liquid crystal panel or an organic EL panel. Ex. 1001 at 1:6-8.
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`5
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`Regarding specific display devices, that the specification of the ‘057
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`discloses that
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`One embodiment of the present invention is a display device including
`a pixel region where a plurality of pixels each including a pixel
`electrode and at least one first transistor electrically connected to the
`pixel electrode is arranged, a first substrate provided with a driver
`circuit region that is located outside and adjacent to the pixel region
`and includes at least one second transistor which supplies a signal to
`the first transistor included in each of the pixels in the pixel region, a
`second substrate provided to face the first substrate, a liquid crystal
`layer interposed between the first substrate and the second substrate, a
`first interlayer insulating film including an inorganic insulating
`material over the first transistor and the second transistor, a second
`interlayer insulating film including an organic insulating material over
`the first interlayer insulating film, and a third interlayer insulating film
`including an inorganic insulating material over the second interlayer
`insulating film. In the display device, the third interlayer insulating
`film is provided in part of an upper region of the pixel region, and an
`edge portion of the third interlayer insulating film is formed on an
`inner side than the driver circuit region.
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`Ex. 1001 at 2:45-65.
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`C.
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`Prosecution History
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`The ‘057 Patent issued from U.S. Patent Application No. 13/939,323 (“the
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`‘323 application”), which was filed on July 11, 2013. Ex. 1002 at 235. The ‘323
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`application claimed the benefit of the filing date of prior Japanese patent
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`application No. 2012-161344, which was filed on July 20, 2012. Id. at 246-247.
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`Neither of the references being relied upon herein was cited or considered
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`during the prosecution of the ‘057 Patent. Ex. 1003 at ¶ 31.
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`6
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`VI. PERSON OF ORDINARY SKILL IN THE ART
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`A United States patent is to be read and understood from the perspective of a
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`person of ordinary skill in the relevant art (technical field) at the time the invention
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`was made. Here, the relevant date is July 20, 2012, i.e. when the inventors named
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`on the ‘057 Patent filed the original Japanese patent application to the subject
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`matter now claimed in the ‘057 Patent and to which priority is claimed.
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`A person of ordinary skill in the art is a hypothetical person presumed to
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`know the relevant prior art. See, e.g., Gnosis S.p.A. v. South Alabama Med. Sci.
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`Found., IPR2013-00116, Final Written Decision (Paper 68) at 9. Such a person is
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`of ordinary creativity, not merely an automaton, and is capable of combining the
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`teachings of the prior art. See id., citing KSR Int’l Co. v. Teleflex Inc., 550 U.S.
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`398, 420-21 (2007). The factors that may be used to determine the level of skill of
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`a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`In this case, the ‘057 Patent is directed to improving the process of
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`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
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`in many display devices. Petitioner therefore submits that a person of ordinary
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`skill should have some at least some familiarity with the practical aspects of
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`fabricating TFTs. Ex. 1003 at ¶ 25. Accordingly, Petitioner submits that a person
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`of ordinary skill in the art of the ‘057 Patent as of July 20, 2012, would have had at
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`least a bachelor of science or engineering degree in electrical engineering,
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`semiconductor technology, physics, or a related field, and either an advanced
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`degree (such as a masters) or an equivalent amount of work experience, i.e. 2-3
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`years, in an area relating to semiconductor design and/or fabrication, liquid crystal
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`display (“LCD”) design or fabrication, electrical engineering, or a related technical
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`field. Id.
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`VII. CLAIM CONSTRUCTION
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`The following constructions of certain claim terms are proposed by
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`Petitioner using the “broadest reasonable interpretation” standard currently
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`applicable for inter partes review. See 37 C.F.R. § 42.100(b); Cuozzo Speed
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`Techs. v. Lee, 579 U.S. ___, ___, 136 S. Ct. 2131, 2134 (2016). If, however, the
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`“plain and ordinary meaning” standard was applicable, Petitioner would still
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`propose the same constructions for the same reasons as provided below.
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`1.
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`“over” (claims 1-7 and 9-19)
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`This term appears in all of the challenged claims, but is not expressly
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`defined in the specification of the ‘057 Patent. Nevertheless, in its broadest
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`8
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`reasonable interpretation, a word which expresses a direction, such as over, usually
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`indicates a direction based on the substrate surface when referring to where a layer
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`is provided over the surface of that substrate. Ex. 1003 at ¶ 33. Petitioner
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`therefore submits that the claim term over should be construed to mean “above.”
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`Id.
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`2.
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`“overlaps with” (claims 1-7 and 9-19)
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`This term appears in all of the challenged claims, but is not expressly
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`defined in the specification of the ‘057 Patent. When this term was added by
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`amendment, however, the Patent Owner provided an explanation of what was
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`intended by this term:
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`New claims 33, 35 and 37 recite that an edge of a first insulating film
`and the third insulating film are overlapped with each other. Thus, the
`second insulating film is surrounded by the first insulating film and
`the third insulating film, which are inorganic insulating films that
`suppress entry of hydrogen, moisture, or an organic component into
`the transistor.
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`Ex. 1002 at 82. Petitioner therefore submits that the claim term overlaps with
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`should be construed here to mean “in direct physical contact with.” Ex. 1003 at ¶
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`34.
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`9
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED CLAIM OF
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`THE ‘057 PATENT IS UNPAENTABLE
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`As discussed in detail below, the challenged claims are unpatentable over
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`the prior art.
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`
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`A. Challenge #1: Claims 1, 3-7, 9-12 and 14-19 are obvious under
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`pre-AIA 35 U.S.C. § 103(a) over Yamazaki
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`Yamazaki (Ex. 1004) was published on May 12, 2011. Since the application
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`from which the ‘057 Patent issued was first filed in the United States on July 11,
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`2013, Yamazaki qualifies as prior art against the ‘057 Patent under pre-AIA 35
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`U.S.C. § 102(b).
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`
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`“Obviousness” is when the claimed subject matter is not identically
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`described, but would have been obvious, as a whole, to a person of ordinary skill in
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`the art. 35 U.S.C. § 103(a); see KSR Int’l, Inc. v. Teleflex, Inc., 550 U.S. 398, 406–
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`07 (2007). A proper obviousness analysis requires the following steps: (1)
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`determining the scope and content of the prior art; (2) ascertaining the difference(s)
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`between the prior art and the claimed invention; (3) resolving the level of ordinary
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`skill in the art; and (4) evaluating the objective evidence relevant to obviousness, if
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`any. See, e.g., Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966); KSR, 550
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`U.S. at 404; Artic Cat Inc. v. Bombadier Recreational Prods., Inc., 876 F.3d 1350,
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`1358 (Fed. Cir. 2017).
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`10
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`When obviousness is based on information from a combination of sources, a
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`relevant factor is whether a person of ordinary skill in the art would have been
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`motivated to select and combine this information, and with a reasonable
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`expectation of achieving the desired result. See, e.g., Merck & Cie v. Gnosis
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`S.p.A., 808 F.3d 829, 833 (Fed. Cir. 2015), cert. denied, 137 S. Ct. 297 (2016).
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`Nevertheless, “[c]ombining two embodiments adjacent to one another in a prior art
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`patent does not require a leap of inventiveness.” Boston Scientific Scimed, Inc. v.
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`Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009); see also Paice LLC v. Ford
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`Motor Co., 681 F. App’x 904 (Fed. Cir. 2017) (“Like the combination of two side-
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`by-side embodiments in Boston Scientific, we view the combination of elements
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`from optimal and sub-optimal embodiments as a ‘predictable variation’ that does
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`not ‘require a leap of inventiveness.’”).
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`Claims 1, 3-7, 9-12 and 14-19 of the ‘057 Patent would have been obvious
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`to one of ordinary skill in the art at the time the claimed invention was made over
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`Yamazaki. Specifically, in at least FIGS. 11B and 15A and the accompanying text
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`in the specification, particularly relating to Embodiment 6 and Embodiment 8,
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`Yamazaki discloses display devices comprising a pixel region and a driver region.
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`Ex. 1003 at ¶ 36. These embodiments together teach each and every element of the
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`challenged claims, arranged in the same way as recited in those challenged claims.
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`Id.
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`11
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`1.
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`Claim 1
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`a.
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`The preamble
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`The preamble of claim 1 recites “[a] display device comprising . . ..” Ex
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`1001 at 31:21. To the extent that this preamble is deemed a limitation, this
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`limitation is expressly disclosed by Yamazaki. Ex 1003 at ¶ 37.
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`
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`Yamazaki discloses display devices having a pixel portion and a driver
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`portion. More specifically, Yamazaki discloses that
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`By manufacturing transistors described in Embodiment 1 and using
`the transistors for a pixel portion and driver circuits, a semiconductor
`device having a display function (also referred to as a display device)
`can be manufactured.
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`Ex. 1004 at ¶ 283.
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`
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`Referring to FIG. 11B, Yamazaki discloses that “[i]n this embodiment, the
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`appearance and a cross section of a liquid crystal display panel, which is one
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`embodiment of a semiconductor device, will be described with reference to FIGS.
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`11A1, 11A2, and 11B.” Id. at ¶ 287. Similarly, referring to FIG. 15A, Yamazaki
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`discloses that “[i]n this embodiment, an example of a light-emitting display device
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`will be described as a semiconductor device to which the transistors described in
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`Embodiment 1 are applied.” Id. at ¶ 324.
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`Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Yamazaki. Ex. 1003 at ¶ 40.
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`12
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`Petition for Inter Partes Review
`U.S. Patent No. 9,298,057
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`b.
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`a pixel portion
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`The first limitation of claim 1 of the ‘057 patent is a pixel portion. Ex. 1001
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`at 31:21-22. Yamazaki discloses devices having a pixel portion. Ex. 1003 at ¶ 41.
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`
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`Referring specifically to the device depicted in FIG. 11B, Yamazaki teaches
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`that
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`In this embodiment, the appearance and a cross section of a liquid
`crystal display panel, which is one embodiment of a semiconductor
`device, will be described with reference to FIGS. 11A1, 11A2, and
`11B. FIGS. 11A1 and 11A2 are plan views of panels, in which highly
`reliable transistors 4010 and 4011 . . . described in Embodiment 1 and
`a liquid crystal element 4013 are sealed between a first substrate 4001
`and a second substrate 4006 with a sealant 4005. . .. The sealant 4005
`is provided so as to surround a pixel portion 4002 and a scan line
`driver circuit 4004 which are provided over the first substrate 4001.
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`Ex. 1004 at ¶¶ 287-288 (emphasis added). Similarly, when referring to the device
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`shown in FIG. 15A, Yamazaki teaches that “FIG. 15A is a cross-sectional view of
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`a pixel in the case where the driving transistor 7011 is of an n-type and light is
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`emitted from a light-emitting element 7012 to a first electrode 7013 side.” Ex.
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`1004 at ¶ 339 (emphasis added).
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`The pixel portion of claim 1 comprises five specified elements arranged in a
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`particular order: (i) a first transistor; (ii) a first insulating film over the first
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`transistor; (iii) a second insulating film over the first insulating film; (iv) a third
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`insulating film covering the second insulating film; and (v) a first electrode over
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`the third insulating film, the first electrode being electrically connected to the first
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`transistor. Ex. 1001 at 31:22-30. Yamazaki discloses each of these elements, and
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`it would have been obvious to one of ordinary skill in the art to arrange those
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`elements as recited in the claim. Ex. 1003 at ¶ 43.
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`(i) a first transistor
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`The first element of the pixel portion limitation of claim is a first transistor.
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`Ex. 1001 at 31:23. Yamazaki discloses this element in FIG. 11B. Ex. 1003 at ¶ 44.
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`More specifically, referring to FIG. 11B, Yamazaki teaches that
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`The pixel portion 4002 and the scan line driver circuit 4004 provided
`over the first substrate 4001 include a plurality of transistors. FIG.
`11B illustrates the transistor 4010 included in the pixel portion
`4002 . . ..
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`Ex. 1004 at ¶ 290 (emphasis added).
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`Yamazaki therefore discloses that the pixel portion includes a first transistor,
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`i.e. Yamazaki identically discloses the first transistor element of the pixel portion
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`of claim 1. Ex. 1003 at ¶ 46.
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`(ii)
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`a first insulating film over the first transistor
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`The second element of the pixel portion is a first insulating film over the
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`first transistor. Ex. 1001 at 31:24. Yamazaki also discloses this element in FIG.
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`11B. Ex. 1003 at ¶ 47.
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`More specifically, referring to FIG. 11B, Yamazaki teaches that
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`FIG. 11B illustrates the transistor 4010 included in the pixel portion
`4002 and the transistor 4011 included in the scan line driver circuit
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`4004, as an example. Insulating layer[] 4020 [is] provided over the
`transistor 4010 . . ..
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`Ex. 1004 at ¶ 290 (emphasis added). Yamazaki’s insulating layer 4020
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`corresponds to the claimed first insulating film. Ex. 1003 at ¶ 48.
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`Yamazaki’s FIG. 11B is reproduced below:
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`As can be seen in FIG. 11B above, the insulating layer 4020 (the first insulating
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`layer) is above (over) transistor 4010 (the first transistor). Id. at ¶ 49.
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`Yamazaki therefore discloses that the pixel portion includes a first insulating
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`film over the first transistor, i.e. the first insulating film element of the pixel
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`portion of clam 1. Id. at ¶ 50.
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`(iii) a second insulating film over the first
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`insulating film
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`The third element of the pixel portion is a second insulating film over the
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`first insulating film. Ex. 1001 at 31:25. Yamazaki also discloses this element in
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`FIG. 11B. Ex. 1003 at ¶ 51.
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`More specifically, referring to FIG. 11B, Yamazaki teaches that “[i]nsulating
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`layers 4020 and 4041 [sic, 4021] are provided over the transistor 4010, and an
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`insulating layer 4021 is provided over the transistor 4011.” Ex. 1004 at ¶ 290.
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`Yamazaki’s insulating layer 4021 corresponds to the claimed second insulating
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`film. Ex. 1003 at ¶¶ 52-53.
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`Yamazaki’s FIG. 11B is reproduced below:
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`As can be seen in this FIG. 11B, insulating layer 4021 (the second insulating film)
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`is above (over) insulating layer 4020 (the first insulating film). Id. at ¶ 54.
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`Yamazaki therefore discloses that the pixel portion includes a second
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`insulating film over the first insulating film, i.e. the second insulating film element
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`of the pixel portion of clam 1. Id. at ¶ 55.
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`(iv) a third insulating film over the second
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`insulating film
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`The fourth element of the pixel portion is a third insulating film over the
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`second insulating film. Ex. 1001 at 31:26. Yamazaki discloses this element in FIG.
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`15A. Ex. 1003 at ¶ 56.
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`Referring to FIG. 15A, Yamazaki teaches that
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`Note that in FIG. 15A, light emitted from the light-emitting element
`7012 passes through a color filter layer 7033, an insulating layer 7032,
`an oxide insulating layer 7031, a gate insulating layer 7030, and a
`substrate 7010 and then is emitted.
`*
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`The color filter layer 7033 is covered with an overcoat layer 7034,
`and also covered with a protective insulating layer 7035.
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`Ex. 1004 at ¶¶ 348-350 (emphasis added). In this embodiment, overcoat layer
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`7034 corresponds to the claimed second insulating layer, and protective insulating
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`layer 7035 corresponds to the claimed third insulating layer. Ex. 1003 at ¶ 57.
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`More specifically, with respect to the second insulating layer, Yamazaki
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`teaches that the overcoat layer 7034 may be an acrylic resin. Ex. 1004 at ¶ 350
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`(“the overcoat layer 7034 is formed using a resin material such as an acrylic
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`resin”). Yamazaki further teaches that acrylic resins function as insulating layers.
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`Id. at ¶ 149 (“The planarization insulating layer can be formed of a heat-resistant
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`organic material, such as an acrylic resin . . ..”); Ex. 1003 at ¶ 58.
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`Yamazaki’s FIG. 15A is reproduced below:
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`As can be seen from FIG. 15A above, the protective insulating layer 7035 (the
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`third insulating layer) is above (over) the overcoat layer 7034 (the second
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`insulating layer). Ex. 1003 at ¶ 59.
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`As noted in section VI. above, a person of ordinary skill in the relevant art as
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`of July 20, 2012 would have had at least a bachelor of science or engineering
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`degree in electrical engineering, semiconductor technology, physics, or a related
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`field, and either an advanced degree (such as a masters) or an equivalent amount of
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`work experience, i.e. 2-3 years, in an area relating to semiconductor design and/or
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`fabrication, liquid crystal display (“LCD”) design or fabrication, electrical
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`engineering, or a related technical field. Id. at ¶ 60.
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`Both FIGS. 11B and 15A depict display devices that include a pixel portion
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`and a driver portion and that utilize the same transistor structure. Id. at ¶ 61. As
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`taught by Yamazaki:
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`By manufacturing transistors described in Embodiment 1 and using
`the transistors for a pixel portion and driver circuits, a semiconductor
`device having a display function (also referred to as a display device)
`can be manufactured.
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`Ex. 1004 at ¶ 283.
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`Referring specifically to FIG. 11B, Yamazaki discloses that “[i]n this
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`embodiment, the appearance and a cross section of a liquid crystal display panel,
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`which is one embodiment of a semiconductor device, will be described with
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`reference to FIGS. 11A1, 11A2, and 11B.” Id. at ¶ 287. Similarly, referring to
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`FIG. 15A, Yamazaki discloses that “[i]n this embodiment, an example of a light-
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`emitting display device will be described as a semiconductor device to which the
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`transistors described in Embodiment 1 are applied.” Id. at ¶ 324.
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`Moreover, Yamazaki discloses that insulating layer 4021 in FIG. 11A can be
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`made from an organic material, such as an acrylic resin or a polyimide. Id. at ¶
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`302. One skilled in the art would have recognized the potential for impurities from
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`the metal pixel electrode 4030 reacting with such an organic material and would
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`have sought to eliminate this possibility by placing an additonal insulating layer
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`(i.e. a third insulating film) made of a non-reactive material between the pixel
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`electrode 4030 and insulating layer 4021, i.e. on top of insulating layer 4021 (the
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`second insulating film). Ex. 1003 at ¶ 64.
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`A person of ordinary skill in the relevant art would therefore have been
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`motivated, at the time the invention claimed in claim 1 of the ‘057 Patent was
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`made, to combine Yamazaki’s FIGS. 11B and 15A and include a third insulating
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`film in the device shown in FIG. 11B with a reasonable expectation of success. Id.
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`at ¶ 65.
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`(v)
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`a first electrode over the third insulating
`film, the first electrode being electrically
`connected to the first transistor
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`The fifth element of the pixel portion of claim 1 is a first electrode over the
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`third insulating film, the first electrode being electrically connected to the first
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`transistor. Ex. 1001 at 31:28-30. Yamazaki discloses this element in FIG. 15A.
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`Ex. 1003 at ¶ 66.
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`Referring to FIG. 15A, Yamazaki teaches that
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`[T]he first electrode 7013 of the light-emitting element 7012 is formed
`over a conductive film 7017 having a light-transmitting property with
`respect to visible light which is electrically connected to a drain
`electrode layer of the driving transistor 7011 . . ..
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`Ex. 1004 at ¶ 339. Yamazaki’s first electrode 7013 corresponds to the claimed first
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`electrode and, as described above, protective insulating layer 7035 corresponds to
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`the claimed third insulating film. Ex. 1003 at ¶ 67. Transistor 7011 corresponds to
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`the claimed first transistor. Id.
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`Yamazaki’s FIG. 15A is reproduced below:
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`As can be seen in FIG. 15A above, the first electrode 7013 (the first electrode) is
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`above (over) the protective insulating layer 7035 (the third insulating layer) and
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`connected via conductive film 7017 (electrically connected) to the drain electrode
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`layer of transistor 7011 (the first transistor). Ex. 1003 at ¶ 68.
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`Yamazaki’s FIG. 11B is reproduced below:
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`As can be seen in FIG. 11B, pixel electrode 4030 (which corresponds to the first
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`electrode in this embodiment) is above (over) the insulating layer 4021 (the second
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`insulating film). Id. at ¶ 69. As described above, it would have been obvious for
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`one of ordinary skill in the art to include a third insulating film (as shown in FIG.
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`15A) in the structure depicted in FIG. 11B between the pixel electrode 4030 and
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`the insulating layer 4021. Id. This would necessarily result in the pixel electrode
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`4030 (the first electrode) being above (over) the protective insulating layer (the
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`third insulating film). Id
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`As noted in section VI. above, a person of ordinary skill in the relevant art as
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`of July 20, 2012 would have had at least a bachelor of science or engineering
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`degree in electrical engineering, semiconductor technology, physics, or a related
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`field, and either an advanced degree (such as a masters) or an equivalent amount of
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`work experience, i.e. 2-3 years, in an area relating to semiconductor design and/or
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`fabrication, liquid crystal display (“LCD”) design or fabrication, electrical
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`engineering, or a related technical field. Id. at ¶ 70.
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`Both FIGS. 11B and 15A depict display devices that utilize the same
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`transistor structure. Id. at