UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01405
`
`U.S. PATENT NO. 9,298,057 B2
`
`_____________________________
`
`
`DECLARATION OF RICHARD A. FLASCK
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 1 of 68
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`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01405
`
`U.S. PATENT NO. 9,298,057 B2
`
`_____________________________
`
`
`DECLARATION OF RICHARD A. FLASCK
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
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`I, Richard A. Flasck, declare as follows:
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`I.
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`INTRODUCTION
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`1.
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`I am over the age of twenty-one (21) and am competent to make this
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`Declaration.
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`2.
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`I am an independent consultant in liquid crystal display (“LCD”)
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`technology, including manufacturing processes and product design.
`
`A.
`
`Engagement
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`3.
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`I have been retained by counsel for BlueHouse Global Ltd. in the
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`above-captioned Inter Partes Review (“IPR”) matter as an independent technical
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`expert.
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`4.
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`As part of this engagement, I have been retained to review and
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`evaluate whether certain patents and publications disclose to a person of ordinary
`
`skill in the art (“POSA”) the subject matter of specific claims of United States
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`Patent No. 9,298,057 B2 (“the ‘057 Patent”) as of the time of the filing date of the
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`application from which the ‘057 Patent issued. I expect to testify regarding the
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`matters set forth in this declaration if asked to do so.
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`5.
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`I am being compensated on an hourly basis for my work performed in
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`connection with this case. I have received no additional compensation for my work
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`in this case, and my compensation does not depend upon the contents of this
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`report, any testimony I may provide, or the ultimate outcome of the case.
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`B.
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`Background and Qualifications
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`
`
`6.
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`I earned my Bachelor of Science degree in Physics from the
`
`University of Michigan in 1970. I subsequently earned my M.S. in Physics at
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`Oakland University in 1976.
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`
`
`7.
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`I have nearly fifty (50) years of experience in hi tech product
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`development, including all aspects of LCD systems and technologies, through
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`positions ranging from research and development to manufacturing at multiple
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`large and small technology companies. I have led engineering teams to develop
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`Liquid Crystal on Silicon (LCOS) microdisplay technology. I played a significant
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`part in the early development of amorphous silicon thin film transistor (TFT)
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`active matrix Liquid Crystal Displays (AMLCD), including designing the world’s
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`first amorphous silicon TFT LCD pilot line in 1986. I have experience in TFT
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`process and circuit design, data driver and gate driver design, scalers, video
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`circuits, backlighting, and inverter design. I also have a solid functional
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`background in all display technologies, their applications and associated process
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`and manufacturing technologies.
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`
`
`8.
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`I am an inventor or co-inventor of 26 patents, including patents on
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`various aspects of LCD technology, including TFT structure and fabrication. A list
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`of my patents is included in my curriculum vitae, a copy of which is attached
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`hereto as Appendix B.
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`
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`9.
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`A detailed description of my professional qualifications, including a
`
`listing of my specialties/expertise and professional activities, is contained in my
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`curriculum vitae, a copy of which is attached hereto as Appendix B.
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`C. Basis of My Opinions and Materials Considered
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`
`
`10.
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`In forming my opinions, I have relied upon my education, knowledge
`
`and experience with LCDs and related technologies, including manufacturing
`
`processes. I have also relied upon my education, knowledge and experience with
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`electronic design, mechanical design, and processes and materials for LCD
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`manufacture.
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`11. For this work, I reviewed and considered the following materials:
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`
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`U.S. Patent No. 8,9,298,057 B2 (“the ‘057 Patent”; Ex. 1001),
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`including the specification and claims;
`
`
`
`The prosecution history of United States Patent Application No.
`
`13/939,323 (“the ‘323 Application”), i.e., the prosecution history of the ‘057
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`Patent (Ex. 1002);
`
`
`
`
`
`
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`In forming my opinions, I have relied upon my education, knowledge and
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`experience with LCD technologies, including manufacturing processes and product
`
`design. I have also relied upon my education, knowledge and experience with
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`electronic design, mechanical design, and materials for LCDs and components
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`thereof.
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`
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`12.
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`I have also been asked to review the subject matter disclosed by
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`various patents and publications that are prior art to the ‘057 Patent, and have been
`
`further asked to compare the subject matter disclosed by those patents and
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`publications to claims 1-7 and 9-19 of the ‘057 Patent and determine whether those
`
`patents and printed publications taught the claimed subject matter to a POSA prior
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`to the earliest effective filing date of the ‘057 Patent, which I have been instructed
`
`to assume is July 20, 2012 for purposes of my analysis. The principal documents
`
`that I have analyzed with regard to their teachings of subject matter claimed in the
`
`‘057 Patent are listed below:
`
`
`
`United States Patent Application Publication No. 2011/0109351 A1
`
`(“Yamazaki”; Ex. 1004); and
`
`
`
`United States Patent No. 8,169,558 B2 (“Morimoto”; Ex. 1005).
`
`Additional documents that I have analyzed are provided on the list of Exhibits
`
`attached hereto as Appendix A.
`
`
`
`II.
`
`PATENT PRINCIPLES
`
`13.
`
`I am an engineer by trade, and the opinions I express in this
`
`declaration involve the application of my engineering knowledge and experience to
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`the evaluation of certain prior art with respect to the ‘057 Patent. I am not a lawyer
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`and have not been trained in the law of patents. Therefore, I have requested the
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`attorneys from Taft, Stettinius & Hollister, who represent BlueHouse Global, to
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`provide me with guidance as to the applicable patent law in this matter. The
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`paragraphs below express my understanding of how I must apply current legal
`
`principles related to patent validity to my analysis.
`
`14.
`
`It is my understanding that in determining whether a patent claim
`
`under inter partes review before the United States Patent Office (“PTO”) is
`
`anticipated or obvious in view of the prior art, the PTO must construe the claim by
`
`giving the claim its broadest reasonable interpretation consistent with the
`
`specification as the claim terms and specification would be understood by a POSA.
`
`It is my understanding that the broadest reasonable interpretation is the plain
`
`meaning, i.e., the ordinary and customary meaning, given to the term by a POSA at
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`the time of the invention, taking into account whatever guidance, such as through
`
`definitions, may be provided by the written description in the patent, without
`
`importing limitations from the specification. For the purposes of this review, I have
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`construed each claim term in accordance with its plain meaning, i.e., its ordinary
`
`and customary meaning under the required broadest reasonable interpretation.
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`It is my understanding that a claim is anticipated under 35 U.S.C. § 102 if each and
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`every limitation of the claim is disclosed in a single prior art reference, either
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`expressly or inherently. I understand inherent disclosure to mean that the claim
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`feature necessarily flows from the disclosure of the prior art reference. I understand
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`that a claim is unpatentable under 35 U.S.C. § 103 if the claimed subject matter as a
`
`whole would have been obvious to a POSA at the time of the alleged invention,
`
`which I have been instructed to treat at present as the earliest effective filing date of
`
`the ‘057Patent. I also understand that an obviousness analysis takes into account the
`
`scope and content of the prior art, the differences between the claimed subject
`
`matter and the prior art, and the level of ordinary skill in the art at the time of the
`
`invention. Finally, I understand that I must consider any known secondary evidence
`
`that might show nonobviousness of the application, such as long felt but unfulfilled
`
`need for the claimed invention, failure by others to come up with the claimed
`
`invention, commercial success of the claimed invention, praise of the invention by
`
`others in the field, unexpected results achieved by the invention, the taking of
`
`licenses under the patent by others, expressions of surprise by experts and those
`
`POSAs at the making of the invention, and the patentee proceeded contrary to the
`
`conventional wisdom of the prior art. But the secondary evidence must be tied
`
`specifically to claim features that are argued to be patentable, and not those already
`
`in the public domain. I appreciate that secondary considerations must be assessed
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`as part of the overall obviousness analysis (i.e., as opposed to analyzing the prior
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`art, reaching a tentative conclusion, and then assessing whether objective indicia
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`alter that conclusion).
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`15. Put another way, my understanding is that not all innovations are
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`patentable. Even if a claimed product or method is not explicitly described in its
`
`entirety in a single prior art reference, the patent claim will still be denied if the
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`claim would have been obvious to a POSA at the time of the patent application
`
`filing.
`
`16.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art if it falls within
`
`the field of the inventor’s endeavor. In addition, a reference is prior art if it is
`
`reasonably pertinent to the particular problem with which the inventor was
`
`involved. A reference is reasonably pertinent if it logically would have
`
`commended itself to an inventor’s attention in considering his problem. If a
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`reference relates to the same problem as the claimed invention, that supports use of
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`the reference as prior art in an obviousness analysis.
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`17. To assess the differences between prior art and the claimed subject
`
`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
`
`to be considered as a whole. This “as a whole” assessment requires showing that a
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`POSA at the time of invention, confronted by the same problems as the inventor
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`and with no knowledge of the claimed invention, would have selected the elements
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`from the prior art and combined them in the claimed manner.
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`18.
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`In determining whether the subject matter as a whole would have been
`
`considered obvious at the time that the patent application was filed, by a POSA, I
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`have been informed of several principles regarding the combination of elements of
`
`the prior art. First, a combination of familiar elements according to known methods
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`is likely to be obvious when it yields predictable results. Likewise, combinations
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`involving simple substitution of one known element for another to obtain
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`predictable results, a predictable use of prior art elements according to their
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`established functions, applying a known technique to a known device (method or
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`product) ready for improvement to yield predictable results, and choosing from a
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`finite number of identified, predictable solutions to solve a problem are likely to be
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`obvious. Thus, if a POSA can implement a “predictable variation” in a prior art
`
`device, and would see the benefit from doing so, such a variation would be obvious.
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`Also, when there is pressure to solve a problem and there are a finite number of
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`identifiable, predictable solutions, it would be reasonable for a POSA to pursue
`
`those options that fall within his or her technical grasp. If such a process leads to
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`the claimed invention, then the latter is not an innovation, but more the result of
`
`ordinary skill and common sense.
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`19.
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`I also understand that the “teaching, suggestion, or motivation” test is
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`a useful guide in establishing a rationale for combining elements of the prior art.
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`This test poses the question as to whether there is an explicit teaching, suggestion,
`
`or motivation in the prior art to combine prior art elements in a way that realizes
`
`the claimed invention. Though useful to the obviousness inquiry, I understand that
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`this test should not be treated as a rigid rule. It is not necessary to seek out precise
`
`teachings; it is permissible to consider the inferences and creative steps that a
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`POSA (who is considered to have an ordinary level of creativity and is not an
`
`“automaton”) would employ.
`
`20.
`
`It is my understanding that when interpreting the claims of the ‘057
`
`Patent I must do so based on the perspective of a POSA at the relevant priority
`
`date. My understanding is that the earliest priority date that is claimed by the ‘057
`
`Patent is July 20, 2012.
`
`
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`III. TECHNOLOGY BACKGROUND
`
`21. Semiconductor devices are electronic components that exploit the
`
`electronic properties of semiconductor materials, such as silicon. Semiconductor
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`materials are useful because their behavior can be easily manipulated by the
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`addition of impurities, known as doping. Current conduction in a semiconductor
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`occurs via mobile or “free” electrons and holes, collectively known as charge
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`carriers. Doping a semiconductor such as silicon with a small proportion of an
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`atomic impurity, such as phosphorus, greatly increases the number of free electrons
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`or holes within the semiconductor (a doped semiconductor containing excess holes
`
`is called “p-type”; one containing excess free electrons is known as “n-type”).
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`22. A thin film transistor, or TFT, is an example of semiconductor device.
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`TFTs can be used as simple ON/OFF switches in a wide variety of electrical
`
`devices, such as active-matrix LCD displays. Basically, a TFT consists of a
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`semiconductor and three electrodes: (i) the gate electrode; (ii) the source electrode;
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`and (iii) the drain electrode. The gate electrode must be insulated from the
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`semiconductor by a dielectric layer (or gate insulation layer), while the drain
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`electrode and source electrode must both directly contact the semiconductor.
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`Because of this, TFTs generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`
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`IV. PERSON OF ORDINARY SKILL IN THE ART
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`
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`23. A United States patent is to be read and understood from the
`
`perspective of a person of ordinary skill in the relevant art (technical field) at the
`
`time the invention was made. Here, the relevant date is July 20, 2012, i.e. when
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`the inventors named on the ‘057 Patent filed the original Japanese patent
`
`application to the subject matter now claimed in the ‘057 Patent and to which
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`priority is claimed.
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`
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`24.
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`It is my understanding that a person of ordinary skill in the art is a
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`hypothetical person presumed to know the relevant prior art. Such a person is of
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`ordinary creativity, not merely an automaton, and is capable of combining the
`
`teachings of the prior art. The factors that may be used to determine the level of
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`skill of a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`
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`25.
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`In this case, the ‘057 Patent is directed to improving the process of
`
`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
`
`in many display devices. A person of ordinary skill in the art should therefore
`
`have some at least some familiarity with the practical aspects of fabricating TFTs.
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`More specifically, a person of ordinary skill in the art of the ‘057Patent as of July
`
`20, 2012, would have had at least a bachelor of science or engineering degree in
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`electrical or mechanical engineering, semiconductor technology, display
`
`technology, physics, or a related field, and either an advanced degree (such as a
`
`masters) or an equivalent amount of work experience, i.e. 2-3 years, in an area
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`relating to semiconductor design and/or fabrication, liquid crystal display (“LCD”)
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`design or fabrication, electrical engineering, or a related technical field.
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`26. Based on my experience, I have an understanding of the capabilities
`
`of a POSA in the relevant field. I have supervised and directed many such persons
`
`over the course of my career. Further, I had those capabilities myself at the time
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`the ’057 Patent was effectively filed.
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`V. OVERVIEW OF THE ‘057 PATENT
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`27. The ‘057 Patent (Ex. 1001) is entitled “Display Device and Electronic
`
`Device Including the Display Device” and names Yasuhara Hosaka et al. as the
`
`inventors.
`
`28. According to the specification, the ‘057 Patent relates to a display
`
`device using a liquid crystal panel or a display device using an organic EL panel.
`
`Ex. 1001 at 1:6-8.
`
`
`
`29. Regarding specific display devices, that the specification of the ‘057
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`discloses that
`
`One embodiment of the present invention is a display device including
`a pixel region where a plurality of pixels each including a pixel
`electrode and at least one first transistor electrically connected to the
`pixel electrode is arranged, a first substrate provided with a driver
`circuit region that is located outside and adjacent to the pixel region
`and includes at least one second transistor which supplies a signal to
`the first transistor included in each of the pixels in the pixel region, a
`second substrate provided to face the first substrate, a liquid crystal
`layer interposed between the first substrate and the second substrate, a
`first interlayer insulating film including an inorganic insulating
`material over the first transistor and the second transistor, a second
`interlayer insulating film including an organic insulating material over
`the first interlayer insulating film, and a third interlayer insulating film
`including an inorganic insulating material over the second interlayer
`insulating film. In the display device, the third interlayer insulating
`film is provided in part of an upper region of the pixel region, and an
`edge portion of the third interlayer insulating film is formed on an
`inner side than the driver circuit region.
`
`
`Ex. 1001 at 2:45-65.
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`VI. PROSECUTION HISTORY
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`
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`30. The ‘057 Patent issued from U.S. Patent Application No. 13/939,323
`
`(“the ‘323 application”), which was filed on July 11, 2013. Ex. 1002 at 2366. The
`
`‘323 application claimed the benefit of the filing date of prior Japanese patent
`
`application No. 2012-161344, which was filed on July 20, 2012. Id. at 2201-2207.
`
`
`
`31. Neither of the references being relied upon herein was cited or
`
`considered during the prosecution of the ‘057 Patent.
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`
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`VII. CLAIM CONSTRUCTION
`
`32. Counsel for Petitioner has provided me with their proposals for the
`
`broadest reasonable interpretation (BRI) claim constructions for the terms listed
`
`below. I concur with those proposed constructions for the reasons explained below.
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`
`
`33.
`
`“over” (claims 1-7 and 9-19): This term appears in all of the
`
`challenged claims, but is not expressly defined in the specification of the ‘057
`
`Patent. Nevertheless, in its broadest reasonable interpretation, a word which
`
`expresses a direction, such as over, usually indicates a direction based on the
`
`substrate surface when referring to where a layer is provided over the surface of
`
`that substrate. The claim term over should be construed to mean “above.”
`
`
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`34.
`
`“overlaps with” (claims 1-7 and 9-19): This term appears in all of the
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`challenged claims, but is not expressly defined in the specification of the ‘057
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`Patent. In its broadest reasonable interpretation, the term overlaps with means
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`extends beyond the edge of. The claim term overlaps should be construed to mean
`
`“in direct physical contact with.”
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`
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`VIII. SUMMARY OF OPINIONS
`
`35. Based on my review of the ‘057 Patent, its prosecution history, and
`
`the patents and publications listed above, it is my opinion that the subject matter of
`
`claims 1-7 and 9-19 of the ‘057 Patent was, as of the effective filing date of the
`
`‘057 Patent, unpatentable as either anticipated or obvious in view of the various
`
`prior art references identified, the grounds for which are listed and explained
`
`below.
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`
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`IX. UNPATENTABILITY OF CLAIMS 1-7 AND 9-19
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`
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`A. Challenge #1: Claims 1, 3-7, 9-12 and 14-19 are obvious under
`
`pre-AIA 35 U.S.C. § 103(a) over Yamazaki
`
`36. Claims 1, 3-7, 9-12 and 14-19 of the ‘057 Patent would have been
`
`obvious to one of ordinary skill in the art at the time the claimed invention was
`
`made over Yamazaki. Specifically, in at least FIGS. 11B and 15A and the
`
`accompanying text in the specification, particularly relating to Embodiment 6 and
`
`Embodiment 8, Yamazaki discloses display devices comprising a pixel region and
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`a driver region. These embodiments together teach each and every element of the
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`challenged claims, arranged in the same way as recited in those challenged claims.
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`1.
`
`Claim 1
`
`
`
`a.
`
`The preamble
`
`37. The preamble of claim 1 recites “[a] display device comprising . . ..”
`
`Ex 1001 at 31:21. To the extent that this preamble is deemed a limitation, this
`
`limitation is expressly disclosed by Yamazaki.
`
`
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`38. Yamazaki discloses display devices having a pixel portion and a driver
`
`portion. More specifically, Yamazaki discloses that
`
`By manufacturing transistors described in Embodiment 1 and using
`the transistors for a pixel portion and driver circuits, a semiconductor
`device having a display function (also referred to as a display device)
`can be manufactured.
`
`Ex. 1004 at ¶ 283.
`
`
`
`39. Referring to FIG. 11B, Yamazaki discloses that “[i]n this embodiment,
`
`the appearance and a cross section of a liquid crystal display panel, which is one
`
`embodiment of a semiconductor device, will be described with reference to FIGS.
`
`11A1, 11A2, and 11B.” Id. at ¶ 287. Similarly, referring to FIG. 15A, Yamazaki
`
`discloses that “[i]n this embodiment, an example of a light-emitting display device
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`will be described as a semiconductor device to which the transistors described in
`
`Embodiment 1 are applied.” Id. at ¶ 324.
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`40. Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Yamazaki.
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`
`b.
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`a pixel portion
`
`41. The first limitation of claim 1 of the ‘057 patent is a pixel portion.
`
`Ex. 1001 at 31:21-22. Yamazaki discloses devices having a pixel portion.
`
`
`
`42. Referring specifically to the device depicted in FIG. 11B, Yamazaki
`
`teaches that
`
`In this embodiment, the appearance and a cross section of a liquid
`crystal display panel, which is one embodiment of a semiconductor
`device, will be described with reference to FIGS. 11A1, 11A2, and
`11B. FIGS. 11A1 and 11A2 are plan views of panels, in which highly
`reliable transistors 4010 and 4011. . . described in Embodiment 1 and
`a liquid crystal element 4013 are sealed between a first substrate 4001
`and a second substrate 4006 with a sealant 4005. . .. The sealant 4005
`is provided so as to surround a pixel portion 4002 and a scan line
`driver circuit 4004 which are provided over the first substrate 4001.
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`Ex. 1004 at ¶¶ 287-288 (emphasis added). Similarly, when referring to the device
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`shown in FIG. 15A, Yamazaki teaches that “FIG. 15A is a cross-sectional view of
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`a pixel in the case where the driving transistor 7011 is of an n-type and light is
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`emitted from a light-emitting element 7012 to a first electrode 7013 side.” Ex.
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`1004 at ¶ 339 (emphasis added).
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`43. The pixel portion of claim 1 comprises five specified elements
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`arranged in a particular order: (i) a first transistor; (ii) a first insulating film over
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`the first transistor; (iii) a second insulating film over the first insulating film; (iv) a
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 18 of 68
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`third insulating film covering the second insulating film; and (v) a first electrode
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`over the third insulating film, the first electrode being electrically connected to the
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`first transistor. Ex. 1001 at 31:22-30. Yamazaki discloses each of these elements,
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`and it would have been obvious to one of ordinary skill in the art to arrange those
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`elements as recited in the claim.
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`(i) a first transistor
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`44. The first element of the pixel portion limitation of claim is a first
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`transistor. Ex. 1001 at 31:23. Yamazaki discloses this element in FIG. 11B.
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`45. More specifically, referring to FIG. 11B, Yamazaki teaches that
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`The pixel portion 4002 and the scan line driver circuit 4004 provided
`over the first substrate 4001 include a plurality of transistors. FIG.
`11B illustrates the transistor 4010 included in the pixel portion
`4002. . ..
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`Ex. 1004 at ¶ 290 (emphasis added).
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`46. Yamazaki therefore discloses that the pixel portion includes a first
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`transistor.
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`(ii)
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`a first insulating film over the first transistor
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`47. The second element of the pixel portion is a first insulating film over
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`the first transistor. Ex. 1001 at 31:24. Yamazaki also discloses this element in
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`FIG. 11B.
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`48. More specifically, referring to FIG. 11B, Yamazaki teaches that
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 19 of 68
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`FIG. 11B illustrates the transistor 4010 included in the pixel portion
`4002 and the transistor 4011 included in the scan line driver circuit
`4004, as an example. Insulating layer[] 4020 [is] provided over the
`transistor 4010 . . ..
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`Ex. 1004 at ¶ 290 (emphasis added). Yamazaki’s insulating layer 4020
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`corresponds to the claimed first insulating film.
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`
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`49. Yamazaki’s FIG. 11B is reproduced below:
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`
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`As can be seen in FIG. 11B above, the insulating layer 4020 (the first insulating
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`film) is above (over) transistor 4010 (the first transistor).
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`
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`50. Yamazaki therefore discloses that the pixel portion includes a first
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`insulating film over the first transistor.
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 20 of 68
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`(iii) a second insulating film over the first
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`insulating film
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`51. The third element of the pixel portion is a second insulating film over
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`the first insulating film. Ex. 1001 at 31:25. Yamazaki also discloses this element in
`
`FIG. 11B.
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`
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`52. More specifically, referring to FIG. 11B, Yamazaki teaches that
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`“[i]nsulating layers 4020 and 4041 [sic, 4021] are provided over the transistor
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`4010, and an insulating layer 4021 is provided over the transistor 4011.” Ex. 1004
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`at ¶ 290. Yamazaki’s insulating layer 4021 corresponds to the claimed second
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`insulating film.
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`53. Although the text of Yamazaki initially refers to “[i]nsulating layers
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`4020 and 4041,” it is clear from the remainder of the text and from FIG. 11B that
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`the reference to “4041” is, in fact, a typographical error. One skilled in the art
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`would recognize this typographical error and understand that and the correct
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`numerical designation should be “4021.”
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`54. Yamazaki’s FIG. 11Bis reproduced below:
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 21 of 68
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`As can be seen in this FIG. 11B, insulating layer 4021(the second insulating film)
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`is above (over) insulating layer 4020 (the first insulating film).
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`55. Yamazaki therefore discloses that the pixel portion includes a second
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`insulating film over the first insulating film.
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`(iv) a third insulating film over the second
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`insulating film
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`56. The fourth element of the pixel portion is a third insulating film over
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`the second insulating film. Ex. 1001 at 31:26. Yamazaki discloses this element in
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`FIG. 15A.
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`57. Referring to FIG. 15A, Yamazaki teaches that
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`Note that in FIG. 15A, light emitted from the light-emitting element
`7012 passes through a color filter layer 7033, an insulating layer 7032,
`an oxide insulating layer 7031, a gate insulating layer 7030, and a
`substrate 7010 and then is emitted.
`*
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`*
`*
`The color filter layer 7033 is covered with an overcoat layer 7034,
`and also covered with a protective insulating layer 7035.
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 22 of 68
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`Ex. 1004 at ¶¶ 348-350 (emphasis added). In this embodiment, overcoat layer
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`7034 corresponds to the claimed second insulating layer, and protective insulating
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`layer 7035 corresponds to the claimed third insulating layer.
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`58. More specifically, with respect to the second insulating layer,
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`Yamazaki teaches that the overcoat layer 7034 may be an acrylic resin. Ex. 1004 at
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`¶ 350 (“the overcoat layer 7034 is formed using a resin material such as an acrylic
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`resin”). Yamazaki further teaches that acrylic resins function as insulating layers.
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`Id. at ¶ 149 (“The planarization insulating layer can be formed of a heat-resistant
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`organic material, such as an acrylic resin . . ..”).
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`59. Yamazaki’s FIG. 15A is reproduced below:
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`As can be seen from FIG. 15A above, the protective insulating layer 7035 (the
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`third insulating layer) is above (over) the overcoat layer 7034 (the second
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`insulating layer).
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 23 of 68
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`60. As noted in section IV. above, a person of ordinary skill in the
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`relevant art as of July 20, 2012 would have had at least a bachelor of science or
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`engineering degree in electrical engineering, semiconductor technology, physics,
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`or a related field, and either an advanced degree (such as a masters) or an
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`equivalent amount of work experience, i.e. 2-3 years, in an area relating to
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`semiconductor design and/or fabrication, liquid crystal display (“LCD”) design or
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`fabrication, electrical engineering, or a related technical field.
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`61. Both FIGS. 11B and 15A depict display devices that include a pixel
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`portion and a driver portion and that utilize the same transistor structure.
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`62. As taught by Yamazaki:
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`By manufacturing transistors described in Embodiment 1 and using
`the transistors for a pixel portion and driver circuits, a semiconductor
`device having a display function (also referred to as a display device)
`can be manufactured.
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`Ex. 1004 at ¶ 283.
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`
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`63. Referring specifically to FIG. 11B, Yamazaki discloses that “[i]n this
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`embodiment, the appearance and a cross section of a liquid crystal display panel,
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`which is one embodiment of a semiconductor device, will be described with
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`reference to FIGS. 11A1, 11A2, and 11B.” Id. at ¶ 287. Similarly, referring to
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`FIG. 15A, Yamazaki discloses that “[i]n this embodiment, an example of a light-
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`emitting display device will be described as a semiconductor device to which the
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`transistors described in Embodiment 1 are applied.” Id. at ¶ 324.
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`CORRECTED BLUEHOUSE GLOBAL LTD. EXHIBIT 1003
`Page 24 of 68
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`64. Moreover, Yamazaki discloses that insulating layer 4021 in FIG. 11A
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`can be made from an organic material, such as an acrylic resin or a polyimide. Id.
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`at ¶ 302. One skilled in the art would have recognized the potential for impurities
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`from the metal pixel electrode 4030 reacting with suc
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