UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01393
`
`U.S. PATENT NO.9,293,545 B2
`
`_____________________________
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01393
`
`U.S. PATENT NO.9,293,545 B2
`
`_____________________________
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`
`I.
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`Table of Contents
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`INTRODUCTION……………………………………………………. ...1
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)………………………...1
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))……………….1
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))……………………......1
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))……………2
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))…………………...2
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))……………….2
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`IV.
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`V.
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`IDENTIFICATION OF CHALLENGES……………………………...3
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`BACKGROUND………………………………………………………...4
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`A.
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`B.
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`C.
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`Technology………………………………………………………..4
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`The ‘545 Patent………………………………………………...…5
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`Prosecution History………………………………………………7
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`VI. PERSON OF ORDINARY SKILL IN THE ART…………………….8
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`VII. CLAIM CONSTRUCTION………………………………………….....9
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED
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`CLAIM OF THE ‘545 PATENT IS UNPATENTABLE………….......12
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`
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`A. Challenge #1: Claims 1, 5, 7-11, 15 and 17-20 are
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`
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`anticipated under pre-AIA 35 U.S.C. § 102(e) by
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`Toyota...............................................………………………..........12
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`ii
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`1.
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`2.
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`3.
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`4.
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`5.
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`6.
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`7.
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`8.
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`9.
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`Claim 1…………………………………………………....14
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`Claim 5…………………………………………………....25
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`Claim 7…………………………………………………....31
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`Claim 8…………………………………………………....32
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`Claim 9…………………………………………………....38
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`Claim 10…………………………………………………. .38
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`Claim 11…………………………………………………. .39
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`Claim 15…………………………………………………. .44
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`Claim 17…………………………………………………. .45
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`10. Claim 18…………………………………………………. .45
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`11. Claim 19…………………………………………………. .47
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`12. Claim 20…………………………………………………. .48
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`B. Challenge #2: Claims 3, 4, 13 and 14 are obvious
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`under pre-AIA 35 U.S.C. 103(a) over Toyota in view
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`of Akimoto……………………………………………………….48
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`1.
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`2.
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`Claim 3....………………………………………………...49
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`Claim 4…………………………………………………...52
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`3.
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`Claim 13………………………………………………….53
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`4.
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`Claim 14………………………………………………….54
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`iii
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`IX.
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`X. CONCLUSION…………………………………………………..…..56
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`INSTITUTION SHOULD NOT BE DENIED BASED
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`ON §325(d)…………………………………………………….55
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`iv
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`List of Exhibits
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`
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`Ex. 1001 United States Letters Patent No. 9,293,545 B2
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`Ex. 1002
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`Prosecution history of U.S. Patent No. 9,293,545 B2
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`Ex. 1003 Declaration of Richard A. Flasck
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`Ex. 1004 United States Patent Application Publication No. 2008/0299693 A1
`
`
`(“Toyota”)
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`Ex. 1005 United States Patent Application Publication No. 2007/0072439 A1
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`
` (“Akimoto”)
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`Ex. 1006 United States Patent Application Publication No. 2005/0173752 A1
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`(“Chung”)
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`
`
`v
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`
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`I.
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`
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`INTRODUCTION
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`BlueHouse Global Ltd. (“Petitioner”) hereby petitions for inter partes
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`review of claims 1, 3-5, 7-11, 13-15 and 17-20 (the “challenged claims”) of U.S.
`
`Patent No. 9,293,545 B2 (“the ‘545 Patent”; Ex. 1001) under 35 U.S.C. §§ 311–
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`319 and 37 C.F.R. § 42. According to the assignment information on the front of
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`the ‘545 Patent, and the records of the United States Patent & Trademark Office
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`(the “USPTO”), the ‘545 Patent is assigned to, and therefore owned by,
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`Semiconductor Energy Laboratory Co., Ltd. (the “Patent Owner”). For the reasons
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`provided in detail below, the challenged claims should be found unpatentable and
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`canceled.
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`
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)
`
`
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`
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
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`The real party-in-interest in this matter is Petitioner BlueHouse Global Ltd.
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`and its parent company, Caesar Global Fund.
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`
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`
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`B. Related Matters (37 C.F.R. § 42.8(b)(2))
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`As of the filing date of this Petition, Petitioner is unaware of any matters
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`involving the ‘545 Patent pending in any United States court or administrative
`
`agency
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`
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`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`
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`
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`Lead Counsel:
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`Ryan O. White (USPTO Reg. No. 45,541)
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`TAFT, STETTINIUS & HOLLISTER LLP
`
`One Indiana Square, Suite 3500
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`
`Indianapolis, IN 46204
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`
`
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`Tel: (317) 713-3455
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`Fax: (317) 713-3699
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`Email: rwhite@taftlaw.com
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`
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`Backup Counsel:
`
`
`Roshan P Shrestha (No. 71,277)
`TAFT, STETTINIUS & HOLLISTER LLP
`111 East Wacker Dr. Suite 2800
`Chicago, IL 60601
`Tel: (312) 527-4000
`Fax: (312) 966-8573
`Email: rshrestha@taftlaw.com
`
`
`Philip R. Bautista (pro hac vice
`authorization requested)
`TAFT, STETTINIUS & HOLLISTER LLP
`200 Public Square Suite 3500
`Cleveland, OH 44114-2302
`Tel: (216) 706-3957
`Fax: (216) 241-3707
`Email: pbautista@taftlaw.com
`
`
`
`
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`D.
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`Service Information (37 C.F.R. § 42.8(b)(4))
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`Please address all correspondence to Lead Counsel at the mailing address
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`shown above. Petitioner also consents to electronic service by email.
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`
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`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))
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`
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`Petitioner hereby certifies that: (1) the ‘545 Patent issued on March 22, 2016
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`and so is eligible for inter partes review; (2) Petitioner has not been served with a
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`complaint alleging infringement of any of the claims of the ‘545 patent and so is
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`
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`2
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`
`
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`therefore not barred or estopped from requesting inter partes review of the ‘545
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`Patent on the grounds identified herein; and (3) Petitioner has not filed a complaint
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`challenging the validity of the ‘545 Patent. This Petition is being filed in
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`accordance with 37 C.F.R. § 42.106(a).
`
`
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`IV.
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`IDENTIFICATION OF CHALLENGES
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`Petitioner asks that the Board review the accompanying prior art and
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`analysis thereof, and the supporting evidence, institute a trial for Inter Partes
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`Review of claims 1, 3-5, 7-11, 13-15 and 17-20 of the ‘545 Patent, and cancel those
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`claims as invalid under 35 U.S.C. § 102 or 35 U.S.C. § 103. More specifically,
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`Petitioner requests cancellation of claims 1, 3, 4, 5, 7, 8, 9, 10, 11, 13, 14, 15, 17,
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`18, 19 and 20 of the ‘545 Patent on the following grounds:
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`
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`Challenge #1: Claims 1, 5, 7-11, 15 and 17-20 are anticipated under pre-
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`AIA 35 U.S.C. § 102(e) by United States Patent Application Publication No.
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`2008/0299693 A1 to Toyota et al. (“Toyota”; Ex. 1004). Toyota was filed on May
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`30, 2008 and published on December 4, 2008. Toyota is therefore prior art to the
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`‘545 Patent under pre-AIA 35 U.S.C. § 102(e)(1).
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`
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`Challenge #2: Claims 3, 4, 13 and 14 are obvious under pre-AIA 35 U.S.C.
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`103(a) over Toyota in view of United States Patent Publication No. 2007/0072439
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`to Akimoto et al. (“Akimoto”; Ex. 1005). Akimoto was published on March 29,
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`
`
`3
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`
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`2007 and is therefore prior art to the ‘545 Patent under pre-AIA 35 U.S.C. §
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`102(b).
`
`
`
`V.
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`BACKGROUND
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`
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`
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`A.
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`Technology
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`Semiconductor devices are electronic components that exploit the electronic
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`properties of semiconductor materials, such as silicon. Semiconductor materials
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`are useful because their behavior can be easily manipulated by the addition of
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`impurities, known as doping. Current conduction in a semiconductor occurs via
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`mobile or “free” electrons and holes, collectively known as charge carriers. Doping
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`a semiconductor such as silicon with a small proportion of an atomic impurity,
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`such as phosphorus, greatly increases the number of free electrons or holes within
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`the semiconductor (a doped semiconductor containing excess holes is called “p-
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`type”; one containing excess free electrons is known as “n-type”).
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`
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`A thin film transistor, or TFT, is an example of semiconductor device. TFTs
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`can be used as simple ON/OFF switches in a wide variety of electrical devices,
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`such as active-matrix LCD displays. Basically, a TFT consists of a semiconductor
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`and three electrodes: (i) the gate electrode; (ii) the source electrode; and (iii) the
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`drain electrode. The gate electrode must be insulated from the semiconductor by a
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`dielectric layer (or gate insulation layer), while the drain electrode and source
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`4
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`electrode must both directly contact the semiconductor. Because of this, TFTs
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
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`generally have one of the following configurations:
`
`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`B.
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`The ‘545 Patent
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`According to the specification, the ‘545 Patent relates to display devices that
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`include an oxide semiconductor. Ex. 1001 at 1:6-7.
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`The specification discloses that
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`5
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`
`
`One embodiment of the present invention disclosed in this
`specification is a semiconductor device wherein a gate electrode is
`formed over a substrate having an insulating surface, an insulating
`layer is formed over the gate electrode, a source and drain electrodes
`are formed over the insulating layer, an oxide semiconductor layer is
`formed between their respective side surfaces of the source and drain
`electrodes, which face each other, so as to overlap with the gate
`electrode with the insulating layer interposed therebetween, and the
`angle formed between the surface of the substrate and the side surface
`of the source electrode and the angle formed between the surface of
`the substrate and the side surface of the drain electrode are each
`greater than or equal to 20° and less than 90°.
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`Ex. 1001 at 1:57-2:3.
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`
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`The specification further discloses that, with respect to the source and drain
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`electrodes,
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`The source electrode layer 405a and the drain electrode layer 405b
`each are a single layer or a stacked layer made of different metal
`materials. As a material of each of the source electrode layer 405a and
`the drain electrode layer 405b, a metal material (an element selected
`from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta),
`tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd),
`and scandium (Sc), or an alloy including the element as a component)
`is used.
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`Ex. 1001 at 11:21-29. The specification also discloses that
`
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`The two side surfaces of the electrodes which face each other with the
`oxide semiconductor layer 403 interposed therebetween each have a
`step, so that the distance from the top edge to the bottom edge of the
`electrode in the side surface of each electrode is increased, thereby
`increasing length L3 of a first electric-field relaxation region 406a and
`length L4 of a second electric-field relaxation region to relax the
`electric-field concentration.
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`Ex. 1001 at 12:13-20.
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`
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`6
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`
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`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`C.
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`Prosecution History
`
`The ‘545 Patent claims the benefit of the filing date of prior U.S. Patent
`
`
`
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`
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`Application No. 13/763,874 (“the ‘874 application”), which was filed on February
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`11, 2013 and subsequently issued as U.S. Patent No. 8,803,146. Ex. 1002 at 1422.
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`The ‘874 application claimed the benefit of the filing date of prior U.S. Patent
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`Application No. 12/613,769 (“the ‘769 application), which was filed on November
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`6, 2009 and subsequently issued as U.S. Patent No. 8,373,164. Id. The ‘769
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`application claimed the benefit of the filing date of prior U.S. Patent Application
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`No. 12/606,262 (“the ‘262 application”), which was filed on October 27, 2009 and
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`subsequently abandoned. Id. The ‘262 application claimed the benefit of the filing
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`date of Japanese application no. 2008-287187, which was filed on November 7,
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`2008. Id. at 1423.
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`
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`None of the claims presented in the ‘874 application was previously
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`presented in any prior application in this family. Ex. 1003 at ¶ 29.
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`
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`The primary reference relied upon herein, Toyota, and the secondary
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`reference, Chung, were not cited or considered during the prosecution of the ‘545
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`Patent. Id. at ¶ 30. The secondary reference relied on for Challenge #2, Akimoto,
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`however, was cited by the examiner during prosecution of the ‘874 application, but
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`only for the teaching of an oxide semiconductor film. Ex. 1002 at 1281-1282; Ex.
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`
`
`7
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`1003 at ¶ 30. Akimoto is not being relied upon for such a teaching in this Petition.
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`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`Ex. 1003 at ¶ 30.
`
`
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`VI. PERSON OF ORDINARY SKILL IN THE ART
`
`
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`A United States patent is to be read and understood from the perspective of a
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`person of ordinary skill in the relevant art (technical field) at the time the invention
`
`was made. Here, the relevant date is November 7, 2008, i.e. when the inventors
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`named on the ‘545 Patent filed the original Japanese patent application to the
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`subject matter now claimed in the ‘545 Patent and to which priority is claimed.
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`
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`A person of ordinary skill in the art is a hypothetical person presumed to
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`know the relevant prior art. See, e.g., Gnosis S.p.A. v. South Alabama Med. Sci.
`
`Found., IPR2013-00116, Final Written Decision (Paper 68) at 9. Such a person is
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`of ordinary creativity, not merely an automaton, and is capable of combining the
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`teachings of the prior art. See id., citing KSR Int’l Co. v. Teleflex Inc., 550 U.S.
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`398, 420-21 (2007). The factors that may be used to determine the level of skill of
`
`a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
`
`
`
`8
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`
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`In this case, the ‘545 Patent is directed to improving the process of
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`
`
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`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
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`in many display devices. Petitioner therefore submits that a person of ordinary
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`skill should have some at least some familiarity with the practical aspects of
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`fabricating TFTs. Ex. 1003 at ¶ 25. Accordingly, Petitioner submits that a person
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`of ordinary skill in the art of the ‘545 Patent as of November 7, 2008, would have
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`had at least a bachelor of science or engineering degree in electrical engineering,
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`semiconductor technology, physics, or a related field, and either an advanced
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`degree (such as a masters) or an equivalent amount of work experience, i.e. 2-3
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`years, in an area relating to semiconductor design and/or fabrication, liquid crystal
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`display (“LCD”) design or fabrication, electrical engineering, or a related technical
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`field. Id.
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`
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`VII. CLAIM CONSTRUCTION
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`
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`The following constructions of certain claim terms are proposed by
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`Petitioner using the “broadest reasonable interpretation” standard currently
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`applicable for inter partes review. See 37 C.F.R. § 42.100(b); Cuozzo Speed
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`Techs. v. Lee, 579 U.S. ___, ___, 136 S. Ct. 2131, 2134 (2016). If, however, the
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`“plain and ordinary meaning” standard was applicable, Petitioner would still
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`propose the same constructions for the same reasons as provided below.
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`
`
`9
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`1.
`
`“semiconductor device” (claims 1, 3-5, 7-11, 13-15 and 17-20)
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`This term appears in the preamble of all of the challenged claims. The
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`
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`specification of the ‘545 Patent exemplifies thin film transistors for use as
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`switching elements in a display device as illustrative examples of the disclosed and
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`claimed semiconductor devices. Ex. 1001 at 1:11-30. Petitioner therefore submits
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`that the claim term semiconductor device should be construed to mean “a device
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`that functions by utilizing semiconductor characteristics, such as a thin film
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`transistor.” Ex. 1003 at ¶ 32.
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`
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`
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`2.
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`“in contact with” (claims 1, 3-5, 7-11, 13-15 and 17-20)
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`This term appears in all of the challenged claims in the limitations regarding
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`the first metal film, second metal film and oxide semiconductor layer elements of
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`the claimed semiconductor device. The specification of the ‘545 Patent does not
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`define this term, but the FIGS. show that layers identified in the specification as
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`being “in contact with” one another (e.g. the first metal film and the gate insulating
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`layer; the second metal film and the oxide semiconductor layer) all appear to be
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`physically touching each other at one or more points. Ex. 1003 at ¶ 33. Petitioner
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`therefore submits that the claim term in contact with should be construed to mean
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`“physically touching.” Id.
`
`
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`10
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`
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`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`3.
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`“faces” (claims 1, 3-5, 7-11, 13-15 and 17-20)
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`This term appears in all of the challenged claims with respect to the first
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`metal film and second metal film elements. The specification of the ‘545 Patent
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`does not expressly define this term (indeed, it actually appears nowhere in the
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`entire specification of the ‘545 patent), but the FIGS. show that a surface which
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`“faces” another surface according to the claims (e.g. a side surface of the first
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`metal film and a side surface of the second metal film) appear to oppose one
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`another. Ex. 1003 at ¶ 34. Petitioner therefore submits that the claim term faces
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`should be construed to mean “opposes.” Id.
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`4.
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`“over” (claims 1, 3-5, 7-11, 13-15 and 17-20)
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`This term appears in all of the challenged claims. The specification of the
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`‘545 Patent defines this term, teaching “[i]In this specification, a word which
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`expresses a direction, such as ‘over’, ‘below’, ‘side’, ‘horizontal’, or ‘vertical’,
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`indicates a direction based on the substrate surface in the case where a device is
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`provided over the surface of the substrate.” Ex. 1001 at 6:29-32. Petitioner
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`therefore submits that the claim term over should be construed to mean “above.”
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`Ex. 1003 at ¶ 35.
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`11
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 9,293,545
`
`
`VIII. IDENTIFICATION OF HOW EACH CHALLENGED CLAIM OF
`
`THE ‘545 PATENT IS UNPAENTABLE
`
`
`
`As discussed in detail below, the challenged claims are unpatentable over
`
`the prior art.
`
`
`
`
`
`
`A. Challenge #1: Claims 1, 5, 7-11, 15 and 17-20 are anticipated
`
`under pre-AIA 35 U.S.C. § 102(e) by Toyota
`
`
`Toyota (Ex. 1004) was filed on May 30, 2008 and published on December 4,
`
`2008. Since the application from which the ‘545 Patent issued was first filed in the
`
`United States on October 27, 2009, Toyota qualifies as prior art against the ‘545
`
`Patent under pre-AIA 35 U.S.C. § 102(e)(1).
`
`
`
`“‘Anticipation’” in patent terms means that the claimed invention is not new;
`
`that is, the invention as claimed was already known.” Ericson Inc. v. Intellectual
`
`Ventures LLC, 890 F.3d 1336, 1338 (Fed. Cir. 2018). A finding of anticipation
`
`requires that every limitation of the claim is present in a single prior art reference.
`
`See, e.g., Blue Calypso, LLC v. Groupon, Inc., 815 F.3d 1331, 1341 (Fed. Cir.
`
`2016); In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009).
`
`
`
`Toyota anticipates each of claims 1, 5, 7-11, 15 and 17-20 of the ‘545 Patent.
`
`That is, “each and every element” of claims 1, 5, 7-11, 15 and 17-20 of the ‘545
`
`Patent is identically disclosed by Toyota, “arranged or combined in the same way
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`as in the claim.” Ericson 890 F.3d at 1346 (citing Blue Calypso, 815 F.3d at
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`1341). Specifically, in at least FIG. 8B and the accompanying text in the
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`specification, Toyota discloses a thin film transistor (for use in, e.g., a display
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`device) having all of the same layers that are recited in each of claims 1, 5, 7-11,
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`15 and 17-20 and those layers are arranged in the same order as required by those
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`claims. Ex. 1003 at ¶ 37.
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`Toyota’s FIG. 8B, showing a thin film transistor, is reproduced below:
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`where:
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`GT is the gate electrode (Ex. 1004 at ¶ 135);
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`DT(U) and DT(D) are each conductive layers that together form the drain
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`electrode (Id. at ¶ 136);
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`ST(U) and ST(D) are each conductive layers that together form the source
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`electrode (Id.); and
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`
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`GI is the gate insulating layer (Id. at ¶ 135).
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`The semiconductor layer PS is not labelled in this FIG. Ex. 1003 at ¶ 38. The
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`semiconductor layer PS, however, is the layer immediately above the gate
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`insulating layer GI and includes darkened portions to represent the doped regions
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`and a shaded portion to represent the channel region. Id.
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`U.S. Patent No. 9,293,545
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`1.
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`Claim 1
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`a.
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`The preamble
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`The preamble of claim 1 recites “[a] semiconductor device comprising . . ..”
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`Ex. 1001 at 43:21. To the extent that this preamble is deemed a limitation, this
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`limitation is expressly disclosed by Toyota. Ex. 1003 at ¶ 39.
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`The ‘545 Patent identifies thin film transistors a type of semiconductor
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`device within the scope of claim 1. Ex. 1003 at ¶ 40. More specifically, the ‘545
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`Patent states that
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`The present invention relates to a display device using an oxide
`semiconductor and a method for manufacturing the same. . .. As
`typically seen in liquid crystal display devices, a thin film transistor
`formed over a flat plate such as a glass substrate is manufactured
`using amorphous silicon or polycrystalline silicon.
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`Ex. 1001 at 1:6-13.
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`
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`Toyota also discloses thin-film transistors (“TFTs”) and, more specifically,
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`bottom gate TFTs. Ex. 1003 at ¶ 41. With reference to FIGS. 8A-8C, Toyota
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`teaches that “in the thin film transistor formed on the pixel, a so-called bottom gate
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`type thin film transistor, in which the gate electrode is located on the lower layer of
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`the semiconductor layer, is constituted.” Ex. 1004 at ¶¶ 134-135.
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`
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`Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Toyota. Ex. 1003 at ¶ 42.
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`b.
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`a glass substrate
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`The first element of the semiconductor device of claim 1 of the ‘545 Patent
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`
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`is a glass substrate. Ex. 1001 at col. 43:22. Toyota identically discloses this
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`element. Ex. 1003 at ¶ 43.
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`
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`Toyota discloses a TFT having a glass substrate. Ex. 1004 at ¶¶ 52, 135; Ex.
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`1003 at ¶ 44. Referring to FIG. 8B, Toyota teaches that
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`as shown in FIG. 8B, for example, in the formation region for the n-
`channel type thin film transistor NTFT, a structure in which the gate
`electrode GT, the insulating film (first insulating film) GI, the
`semiconductor layer PS, and the insulating film (second insulating
`film) IN are sequentially stacked is formed on a surface of the
`undercoat layer FL of the substrate SUB1.
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`Ex. 1004 at ¶ 135. Toyota further teaches that substrate SUB1 is made of glass,
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`i.e., “[i]n FIG. 2, a substrate SUB1 made of, for example, glass is shown.” Id. at ¶
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`52; Ex. 1003 at ¶ 44.
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`Toyota therefore identically discloses the glass substrate limitation of claim
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`1. Ex. 1003 at ¶ 45.
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`c.
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`a gate electrode . . .
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`
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`The second element of the semiconductor device of claim 1 is a gate
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`electrode over the glass substrate. Ex. 1001 at 43:23. Toyota identically discloses
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`this element, and in the same arrangement as recited in the claim. Ex. 1003 at ¶ 46.
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`15
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`Toyota discloses a TFT having a gate electrode over the glass substrate. Ex.
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`1004 at ¶¶ 52, 135; Ex. 1003 at ¶ 47. With reference to FIG. 8B, Toyota teaches
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`that “as shown in FIG. 8B, for example, in the formation region for the n-channel
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`type thin film transistor NTFT, . . . the gate electrode GT . . . is formed on a
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`surface of the undercoat layer FL of the substrate SUB1.” Ex. 1004 at ¶ 135.
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`Toyota’s FIG. 8B is reproduced below:
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`
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`As shown in FIG. 8B, the gate electrode GT is on the upper surface of the
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`undercoat layer FL which is, in turn, on the upper surface of the glass substrate
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`SUB1. Ex. 1003 at ¶ 48. The gate electrode GT is therefore over (above) the
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`glass substrate SUB1. Id.
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`
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`Toyota therefore identically discloses the gate electrode over the glass
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`substrate limitation of claim 1. Id. at ¶ 49.
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`d.
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`a gate insulating film . . .
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`The third element of claim 1 of the ‘545 Patent is a gate insulating film over
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`the gate electrode. Ex 1001 at 43:24. Toyota identically discloses this element,
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`and in the same arrangement as recited in the claim. Ex. 1003 at ¶ 50.
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`
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`Toyota discloses a TFT having a gate insulating film over the gate electrode.
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`Ex. 1004 at ¶ 135; Ex. 1003 at ¶ 51. Toyota teaches that “as shown in FIG. 8B, for
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`example, in the formation region for the n-channel type thin film transistor NTFT,
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`a structure in which the gate electrode GT [and] the insulating film (first insulating
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`film) GI . . . are sequentially stacked is formed on a surface of the undercoat layer
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`FL of the substrate SUB1.” Ex. 1004 at ¶ 135.
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`
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`Toyota’s FIG. 8B is reproduced below:
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`As shown in FIG. 8B, the gate insulating film GI is on the upper surface of the gate
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`electrode GT. Ex. 1003 at ¶ 52. The gate insulating film GI is therefore over
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`(above) the gate electrode GT. Id.
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`
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`Toyota therefore identically discloses the gate insulating film over the gate
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`electrode limitation of claim 1. Id. at ¶ 53.
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`U.S. Patent No. 9,293,545
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`e.
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`a first metal film and a second metal film . . .
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`The fourth element of the claimed semiconductor device is a first metal film
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`and a second metal film over the gate insulating film. Ex 1001 at 43:25-26. This
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`element is also disclosed by Toyota, and in the same arrangement as recited in the
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`claim. Ex. 1003 at ¶ 54.
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`
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`Toyota discloses a TFT having source and drain electrodes, each of which is
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`made of multiple layers of metal. Ex. 1004 at ¶ 136; Ex. 1003 at ¶ 55. Referring
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`to FIG. 8B, Toyota teaches that
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`in the same manner as shown in FIGS. 3A to 3C, the drain electrode
`DT is composed of a layered product of the lower drain electrode
`DT(D) and the upper drain electrode DT(U) . . . In the same manner,
`the source electrode ST is composed of a layered product of the lower
`source electrode ST(D) and the upper source electrode ST(U) . . ..
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`Ex. 1004 at ¶ 136.
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`
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`Toyota further teaches that “the drain electrode DT . . . has the two-layered
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`structure in which, for example, a conductive layer made of tungsten having a
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`thickness of about 30 nm and a conductive layer made of aluminum having a
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`thickness of about 500 nm are sequentially stacked.” Id. at ¶ 72. It is known by
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`those skilled in the art that both tungsten (W) and aluminum (Al) are metals. Ex.
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`1003 at ¶ 56.
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`
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`The source electrode therefore corresponds to the claimed first metal film
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`and the drain electrode corresponds to the claimed second metal film. Id. at ¶ 57.
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`18
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`Toyota’s FIG. 8B is reproduced below:
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`U.S. Patent No. 9,293,545
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`As shown in FIG. 8B, the lower layer of the drain electrode DT(D) and the lower
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`layer of the source electrode ST(D) are both on the upper surface of the
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`semiconductor layer (not labelled), and the semiconductor layer is on the upper
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`surface of the gate insulating film GI. Id. at ¶ 58. The drain electrode (the first
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`metal film) and the source electrode are therefore both above (over) the gate
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`insulating film GI. Id.
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`
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`Toyota therefore identically discloses the first metal film and a second metal
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`film over the gate insulating film limitation of claim 1. Id. at ¶ 59.
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`f.
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`an oxide semiconductor layer . . .
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`The fifth element of the semiconductor device of claim 1 is an oxide
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`semiconductor layer in contact with the first metal film and the second metal film.
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`Ex. 1001 at 43:28-29. Toyota identically discloses this element. Ex. 1003 at ¶ 60.
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`i.
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`an oxide semiconductor layer
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`The first feature of this claim element is an oxide semiconductor. Ex. 1001
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`at 43:28. Toyota identically discloses this feature. Ex. 1003 at ¶ 61.
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`
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`Toyota discloses a TFT having an oxide semiconductor layer. Ex. 1004 at ¶
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`135; Ex. 1003 at ¶ 62. More specifically, with reference to FIG. 8B, Toyota
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`teaches that “as shown in FIG. 8B, for example, . . . a structure in which the gate
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`electrode GT, the insulating film (first insulating film) GI [and] the semiconductor
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`layer PS . . . are sequentially stacked is formed on a surface of the undercoat layer
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`FL of the substrate SUB1.” Ex. 1004 at ¶ 135.
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`
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`Toyota further teaches that “[i]n each of the above-described embodiments, a
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`polysilicon layer is used as the semiconductor layer and further, an amorphous
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`silicon layer or microcrystalline silicon layer may be used. Further, a polysilicon
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`layer formed directly using a catalytic chemical vapor phase growth method or
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`reactive thermal CVD method may be used. Additionally, an oxide
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`semiconductor layer may be used.” Id. at ¶ 181 (emphasis added).
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`Toyota therefore identically discloses the oxide semiconductor layer feature
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`of this limitation. Ex. 1003 at ¶ 64.
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`. . . in contact with the first metal film and
`ii.
`the second metal film
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`
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`The second feature of this element is that the oxide semiconductor is in
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`contact with the first metal film and the second metal film. Ex. 1001 at 43:29.
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`Toyota identically discloses this feature. Ex. 1003 at ¶ 65.
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`Toyota discloses a TFT having an oxide semiconductor layer in contact with
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`the source electrode and the drain electrode (which correspond to the claimed first
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`metal film and second metal film, respectively, as described above in section
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`VIII.A.1.e.). Id. at ¶ 66.
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`Toyota’s FIG. 8B is reproduced below:
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`
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`
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`As shown in FIG. 8B, the lower layer of the drain electrode DT(D) and the lower
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`layer of the source electrode ST(D) are both on the upper surface of the oxide
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`semiconductor layer (not labelled, but on the upper surface of the gate insulating
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`21
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`film GI). Id. at ¶ 67. The drain electrode (the first metal film) and the source
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`electrode ST(D) are therefore both physically touching {in contact with) the oxide
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`semiconductor layer. Id.
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`
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`Toyota therefore also identically discloses the oxide semiconductor layer in
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`contact with the first metal film and second metal film feature of this limitation. Id.
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`at ¶ 68.
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`g.
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`the wherein clauses
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`The final two limitations of claim 1 of the ‘545 Patent are wherein clauses
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`relating to the first metal film and the second metal film. Ex. 1001 at 43:30-34.
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`Toyota identically discloses both of these features. Ex. 1003 at ¶ 69.
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`i.
`wherein a side surface of the first metal film
`faces a side surface of the second metal film
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`The first wherein clause requires that a side surface of the first metal film
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`faces a side surface of the second metal film. Ex. 1001 at 43:30-31. Toyota
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`identically discloses this feature. Ex. 1003 at ¶ 70.
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`As described in section VIII.A.1.e. above, Toyota’s source electrode
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`corresponds to the claimed first metal film and Toyota’s drain electrode
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`corresponds to the claimed second metal film. Id. at ¶ 71. Each of these metal
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`films comprises two metal layers, such as tungsten and aluminu
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