Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1006
`
`EX. 1006
`
`

`

`(19) United States
`(12) Patent Application Publication (io) Pub. No.: US 2005/0173752 Al
`Chung et al.
`(43) Pub. Date:
`Aug. 11,2005
`
`US 20050173752A1
`
`(54) OPTIC MASK AND MANUFACTURING
`METHOD OF THIN FILM TRANSISTOR
`ARRAY PANEL USING THE SAME
`
`(76)
`
`Inventors: Ui-Jin Chung, Suwon-si (KR);
`Myung-Koo Kang, Seoul (KR);
`Jae-Bok Lee, Seoul (KR)
`
`Correspondence Address:
`Hae Chan Park
`McGuire Woods LLP
`Suite 1800
`1750 Tysons Blvd.
`McLean, VA 22102 (US)
`
`(21) Appl. No.:
`
`11/029,011
`
`(22) Filed:
`
`Jan. 5, 2005
`
`(30)
`
`Foreign Application Priority Data
`
`Jan. 6, 2004
`
`(KR)
`
`Jan. 16, 2004
`
`(KR)
`
`10-2004-000547
`
`10-2004-003216
`
`Publication Classification
`
`Int. CI.7
`(51)
`(52) U.S. CI
`(57)
`
`ABSTRACT
`
`H01L 29/788
`257/315
`
`An optic mask for crystallizing amorphous silicon comprises
`a first slit region including a plurality of slits regularly
`arranged for defining incident region of laser beam, wherein
`the slits of the first slit region are formed to slope by a
`predetermined angle to the direction of transfer of the optic
`mask in crystallization process, and wherein the slits of the
`first slit region includes a first slit having a first length and
`a second slit having a second length which is longer than the
`first length.
`
`1?3 161 602 1,24 601 1751f
`
`110140 1 53 1 52
`
`154 152 1 55
`
`1 52
`
`157 152 150A 140 m
`
`150
`
`BLUEHOUSE EXHIBIT 1006
`Page 2 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 1 of 27
`
`US 2005/0173752 Al
`
`FIG.1
`
`161
`/
`
`162 163
`
`191
`^_
`
`H
`
`131
`
`1 7 1-
`
`124
`
`1 7 5^ l3
`
`150
`
`-190
`
`BLUEHOUSE EXHIBIT 1006
`Page 3 of 38
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`

`

`Patent Application Publication Aug. 11, 2005 Sheet 2 of 27
`
`US 2005/0173752 Al
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`Page 4 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 3 of 27
`
`US 2005/0173752 Al
`
`FIG. 3A
`
`NIB
`
`IIIB'
`
`150
`
`BLUEHOUSE EXHIBIT 1006
`Page 5 of 38
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`

`

`Patent Application Publication Aug. 11, 2005 Sheet 4 of 27
`
`US 2005/0173752 Al
`
`O
`
`m
`
`BLUEHOUSE EXHIBIT 1006
`Page 6 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 5 of 27
`
`US 2005/0173752 Al
`
`FIG. 4
`
`BLUEHOUSE EXHIBIT 1006
`Page 7 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 6 of 27
`
`US 2005/0173752 Al
`
`or
`
`CM
`
`BLUEHOUSE EXHIBIT 1006
`Page 8 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 7 of 27
`
`US 2005/0173752 Al
`
`V
`
`131
`
`FIG. 6A
`
`121
`
`VIB"
`
`\
`124
`
`133
`
`150
`
`BLUEHOUSE EXHIBIT 1006
`Page 9 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 8 of 27
`
`US 2005/0173752 Al
`
`o
`
`v0
`
`^
`
`J
`
`^
`
`BLUEHOUSE EXHIBIT 1006
`Page 10 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 9 of 27
`
`US 2005/0173752 Al
`
`BLUEHOUSE EXHIBIT 1006
`Page 11 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 10 of 27
`
`US 2005/0173752 Al
`
`FIG. 8A
`
`VI IB
`
`161
`
`162
`
`121
`
`B'
`VI
`
`131
`
`171-
`
`124
`
`175
`
`\
`133
`
`150
`
`BLUEHOUSE EXHIBIT 1006
`Page 12 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 11 of 27
`
`US 2005/0173752 Al
`
`BLUEHOUSE EXHIBIT 1006
`Page 13 of 38
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`

`

`Patent Application Publication Aug. 11, 2005 Sheet 12 of 27
`
`US 2005/0173752 Al
`
`FIG. 9A
`
`IXB
`
`IXB'
`
`1?1
`
`162 163
`
`1?1
`
`&
`
`131
`
`171-
`
`124
`
`175
`
`133
`
`150
`
`BLUEHOUSE EXHIBIT 1006
`Page 14 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 13 of 27
`
`US 2005/0173752 Al
`
`0}
`
`BLUEHOUSE EXHIBIT 1006
`Page 15 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 14 of 27
`
`US 2005/0173752 Al
`
`FIG. 10
`
`82 164 171a
`
`XI
`
`xf
`
`-171a
`
`163
`
`190
`161
`
`XI
`
`m-
`
`124
`
`121
`
`•?
`
`Vk
`
`162
`150 133
`
`131
`
`xr
`
`M
`
`163—""El
`
`-171b
`
`-190
`
`-171a
`
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`Page 16 of 38
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`

`

`Patent Application Publication Aug. 11, 2005 Sheet 15 of 27
`
`US 2005/0173752 Al
`
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`Page 17 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 16 of 27
`
`US 2005/0173752 Al
`
`FIG. 12A
`
`XI B'
`
`XI B"
`
`XIIB
`
`150
`
`XIIB'
`
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`Page 18 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 17 of 27
`
`US 2005/0173752 Al
`
`o
`
`o
`
`o
`-LO
`
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`Page 19 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 18 of 27
`
`US 2005/0173752 Al
`
`FIG. 13A
`
`171a
`
`XIIIB" J
`
`-171a
`
`XI IB'
`
`XIIIB
`
`124
`
`121
`_JL_
`
`/
`
`131
`
`133
`
`,150
`XIIIB
`
`—171a
`
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`Page 20 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 19 of 27
`
`US 2005/0173752 Al
`
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`Page 21 of 38
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`

`

`Patent Application Publication Aug. 11,2005 Sheet 20 of 27
`
`US 2005/0173752 Al
`
`^t-
`
`Ci
`£
`
`BLUEHOUSE EXHIBIT 1006
`Page 22 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 21 of 27
`
`US 2005/0173752 Al
`
`FIG. 15A
`
`164 171a
`
`XVB'
`
`XVB"
`
`- 1 7 1a
`
`163
`
`161
`
`/
`
`XVB
`4
`
`W
`
`124
`
`121
`
`162 1 \"
`150 133
`
`131
`
`XVB'
`
`-171b
`
`1 6 3 —^
`
`- 1 7 1a
`
`BLUEHOUSE EXHIBIT 1006
`Page 23 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 22 of 27
`
`US 2005/0173752 Al
`
`Ci s
`
`BLUEHOUSE EXHIBIT 1006
`Page 24 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 23 of 27
`
`US 2005/0173752 Al
`
`FIG. 16
`
`Laser beam
`
`210
`
`FIG. 1 7
`
`BLUEHOUSE EXHIBIT 1006
`Page 25 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 24 of 27
`
`US 2005/0173752 Al
`
`FIG. 18
`
`301 302
`
`Y
`
`300
`
`i
`
`i
`
`First scanning direction
`
`Second scanning direction
`
`J
`
`l
`
`FIG. 19
`
`212
`
`Horizontal
`illuminating area
`
`BLUEHOUSE EXHIBIT 1006
`Page 26 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 25 of 27
`
`US 2005/0173752 Al
`
`FIG. 20
`
`185
`145
`143 124 1.80 A | 175
`*
`
`140 153 154 110 155 150 1 30
`
`FIG. 21
`
`124—
`
`T
`
`152
`
`150
`
`153
`
`154
`
`BLUEHOUSE EXHIBIT 1006
`Page 27 of 38
`
`

`

`Patent Application Publication Aug. 11,2005 Sheet 26 of 27
`
`US 2005/0173752 Al
`
`FIG. 22A
`
`Sequential lateral solidification
`
`—r-
`
`110
`
`50
`
`FIG.22B
`
`— I-
`150
`10
`
`FIG.22C
`
`124
`
`- I-
`153 154 110 155 150
`
`40
`
`BLUEHOUSE EXHIBIT 1006
`Page 28 of 38
`
`

`

`Patent Application Publication Aug. 11, 2005 Sheet 27 of 27
`
`US 2005/0173752 Al
`
`FIG. 2 2D
`
`43
`
`12413015
`
`r^//////] ,
`
`V///A
`"1—
`153 154 110 155 150
`
`HO
`
`FIG. 22E
`
`143
`173 r1
`
`145
`124 130 S 175
`
`140
`
`153 154 110 155 150
`
`BLUEHOUSE EXHIBIT 1006
`Page 29 of 38
`
`

`

`US 2005/0173752 Al
`
`Aug. 11,2005
`
`OPTIC MASK AND MANUFACTURING METHOD
`OF THIN FILM TRANSISTOR ARRAY PANEL
`USING THE SAME
`
`CROSS REFERENCE
`[0001] This application claims the benefit of Korean
`Patent Application No. 10-2004-000547, filed on Jan. 6,
`2004 and Korean Patent Application No. 10-2004-003216,
`filed on Jan. 16, 2004, which is hereby incorporated by
`reference for all purposes as if fully set forth herein.
`
`[0002] 1. Field of the Invention
`[0003] The present invention relates to an optic mask for
`crystallizing amorphous silicon into poly crystalline silicon
`and a method for manufacturing a thin film transistor array
`panel using the same.
`[0004] 2. Description of the Related Art
`[0005] Generally, silicon is divided into amorphous silicon
`and crystalline silicon according to the state of crystal.
`Amorphous silicon is widely used in display having glasses
`whose melting point is low, since amorphous silicon film can
`be fabricated at a low temperature.
`[0006] However, the amorphous silicon film has low car(cid:173)
`rier mobility. It may be unsuitable for applying to a high
`quality driving circuit of display panels. Whereas, since
`polycrystalline silicon has prominent electric field effect
`mobility, high frequency operation, and low leakage current,
`high quality driving circuits require the polycrystalline sili(cid:173)
`con.
`
`[0007] Excimer
`laser annealing (ELA) and chamber
`annealing are typical methods for producing polycrystalline
`silicon. Recently, sequential lateral solidification (SLS) pro(cid:173)
`cess is proposed. The SLS technique utilizes a phenomenon
`that the silicon grains grow laterally to the boundary of a
`liquid region and a solid region.
`
`SUMMARY OF THE INVENTION
`
`[0008] The present invention provides an optic mask for
`crystallizing silicon that is enhancing the uniformity of
`characteristics of thin film transistors, and a method of
`manufacturing a thin film transistor array panel using the
`same.
`[0009] According to one aspect of the present invention,
`an optic mask for crystallizing amorphous silicon comprises
`a first slit region including a plurality of slits regularly
`arranged for defining incident region of laser beam, wherein
`the slits of the first slit region are inclined by a predeter(cid:173)
`mined angle to the direction of transfer of the optic mask in
`crystallization process, and wherein the slits of the first slit
`region includes a first slit having a first length and a second
`slit having a second length which is longer than the first
`length.
`
`[0010] Here, it is preferable that the second length is
`longer than the first length by the margin of misalignment of
`the optic mask.
`[0011] The optic mask may further comprises a second slit
`region including a plurality of slits regularly arranged for
`defining incident region of laser beam, wherein the slits of
`the first silt region are arranged to deviate from the slits of
`the second slit region.
`
`[0012] According to another aspect of the present inven(cid:173)
`tion, a method of manufacturing a thin film transistor
`comprises forming an amorphous silicon layer on an insu(cid:173)
`lating substrate, forming a polycrystalline silicon layer by
`irradiating a laser beam to the amorphous silicon layer
`through an optic mask that includes a first slit of a first length
`and a second slit of a second length and translating the laser
`beam and the optic mask, forming a semiconductor layer by
`patterning the poly silicon layer, forming a gate insulating
`layer over the semiconductor layer, forming a gate line on
`the gate insulating layer to overlap the semiconductor layer
`partially, forming a source region and a drain region by
`doping conductive impurities of high concentration on pre(cid:173)
`determined regions of the semiconductor layer, forming a
`first interlayer insulating layer over the gate line and the
`semiconductor layer, forming a data line including a source
`electrode connected with the source region and forming a
`drain electrode connected with the drain region, forming a
`second interlayer insulating layer on the data line and the
`drain electrode, and forming a pixel electrode on the second
`interlayer insulating layer to be connected with the drain
`electrode.
`
`[0013] According to another aspect of the present inven(cid:173)
`tion, a method of manufacturing a thin film transistor
`comprises the steps of: forming an amorphous silicon layer
`on an insulating substrate, forming a polycrystalline silicon
`layer by irradiating a laser beam to the amorphous silicon
`layer through an optic mask which includes a first slit of a
`first length and a second slit of a second length and trans(cid:173)
`lating the laser beam and the optic mask, forming a semi(cid:173)
`conductor layer by patterning the poly silicon layer, forming
`a gate insulating layer over the semiconductor layer, forming
`a data metal piece and a gate line that has a portion
`overlapping the semiconductor layer, forming a source
`region and a drain region by doping conductive impurities of
`high concentration on predetermined regions of the semi(cid:173)
`conductor layer, forming an interlayer insulating layer over
`the semiconductor layer, and forming a data connection part
`connected with the source region and the data metal piece,
`and a pixel electrode connected with the drain region.
`
`[0014] Here, the manufacturing method can further com(cid:173)
`prise forming LDD regions in the semiconductor layer by
`doping conductive impurities having a lower concentration
`compared to the source region and the drain region.
`
`[0015] The manufacturing method can further comprise
`forming a blocking layer between the insulating substrate
`and the semiconductor layer.
`
`[0016] At this time, the slits are formed to slope by as
`much as a predetermined angle to the direction of transfer of
`the optic mask.
`
`[0017] The optic mask includes a first slit region and a
`second slit region that individually include the first slit and
`the second slit, and wherein the slits of the first slit region
`and the slit of the second slit region are arranged to deviate
`from each other.
`
`[0018] The present invention provides an optic mask for
`crystallizing amorphous silicon comprises slits that are
`transparent area of laser beam and have curved boundary
`line.
`
`[0019] Here, the slits may have a shape of arc.
`
`BLUEHOUSE EXHIBIT 1006
`Page 30 of 38
`
`

`

`US 2005/0173752 Al
`
`Aug. 11,2005
`
`[0020] The present invention provides a method of manu(cid:173)
`facturing a thin film transistor comprising: forming an
`amorphous silicon layer on an insulating substrate; forming
`a polycrystalline silicon layer by crystallizing the amor(cid:173)
`phous silicon layer; forming a semiconductor layer by
`patterning the poly silicon layer; forming a gate insulating
`layer on the semiconductor layer; forming a gate electrode
`on the gate insulating layer to overlap the semiconductor
`layer partially; forming a source region and a drain region on
`both sides of the gate electrode to define a channel region
`therebetween; forming a first interlayer insulating layer on
`the gate electrode; forming a source and drain electrodes
`respectively connected to the source region and the drain
`region; forming a second interlayer insulating layer on the
`drain electrode; and forming a pixel electrode on the second
`interlayer insulating layer to be connected with the drain
`electrode, wherein the step of forming a polycrystalline
`silicon layer is performed by a SLS and grain groups formed
`by the SLS have boundaries deviating from the boundary of
`the channel region.
`
`[0021] Here, the SLS may be performed with using an
`optic mask having slits that are transparent area of laser
`beam and have curved boundary line. The slits may have a
`shape of arc. The mask may have two regions having a
`plurality of slits that are arranged in a row and the slits of the
`two regions are arranged to deviate from each other. The
`method may further includes a step of forming LDDs
`disposed between the channel region and the source and
`drain regions.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0022] FIG. 1 is a plan view of a TFT array panel
`according to an embodiment of the present invention.
`[0023] FIG. 2 is a cross-sectional view taken along the
`line II-II' of FIG. 1.
`[0024] FIG. 3A, FIG. 6A, FIG. 8A, and FIG. 9A are plan
`views showing intermediate steps to manufacture a TFT
`array panel according to an embodiment of the present
`invention.
`[0025] FIG. 3B is a cross-sectional view taken along the
`line VIB-VIB' of FIG. 3A.
`[0026] FIG. 4 and FIG. 5 are views showing crystalliza(cid:173)
`tion processes using an optic mask pattern according to the
`present invention.
`[0027] FIG. 6B is a cross-sectional view taken along the
`line VIB-VIB' of FIG. 6A.
`[0028] FIG. 7 is a cross-sectional view showing a subse(cid:173)
`quent step of FIG. 6B.
`[0029] FIG. 8B is a cross-sectional view taken along the
`line VIIIB-VIIIB' of FIG. 8A.
`[0030] FIG. 9B is a cross-sectional view taken along the
`line IXB-IXB' of FIG. 9A.
`[0031] FIG. 10 is a plan view of a TFT array panel
`according to another embodiment of the present invention.
`[0032] FIG. 11 is a cross-sectional view taken along the
`line XI-XI'-XI" of FIG. 10.
`[0033] FIG. 12A, FIG. 13A, and FIG. 15A are plan views
`showing intermediate steps to manufacture a TFT array
`panel according to another embodiment of the present
`invention.
`
`[0034] FIG. 12B is a cross-sectional view taken along the
`line XIIB-XIIB'-XIIB" of FIG. 12A.
`
`[0035] FIG. 13B is a cross-sectional view taken along the
`line XIIIB-XIIIB'-XIIIB" of FIG. 13A.
`
`[0036] FIG. 14 is a cross-sectional view showing a sub(cid:173)
`sequent step of FIG. 13B.
`
`[0037] FIG. 15B is a cross-sectional view taken along the
`line XVB-XVB'-XVB" of FIG. 15A.
`
`[0038] FIG. 16 is a view showing laser beam irradiation
`using a mask.
`
`[0039] FIG. 17 plane view of a mask according to an
`embodiment of the present invention.
`
`[0040] FIG. 18 illustrates processes of a sequential lateral
`solidification according to an embodiment of the present
`invention.
`
`[0041] FIG. 19 illustrates crystal grains of polysilicon
`crystallized by a sequential lateral solidification according to
`an embodiment of the present invention.
`
`[0042] FIG. 20 is a cross-sectional view of a polysilicon
`thin film transistor array panel according to an embodiment
`of the present invention.
`
`[0043] FIG. 21 illustrates structure of grain groups in a
`step of manufacturing process of a thin film transistor array
`panel according to an embodiment of the present invention.
`
`[0044] FIGS. 22A to 22E are cross-sectional views illus(cid:173)
`trating manufacturing process of a polysilicon thin film
`transistor array panel according to an embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0045] Preferred embodiments of the present invention
`will now be described hereinafter with reference to the
`accompanying drawings, in which preferred embodiments
`of the invention are shown. The present invention may,
`however, be embodied in different forms and should not be
`construed as being limited to the embodiments set forth
`herein. Rather, these embodiments are provided so that this
`disclosure will be thorough and complete, and will fully
`convey the scope of the invention to those skilled in the art.
`
`[0046] In the drawings, the thickness of the layers, films,
`and regions are exaggerated for clarity. Like numerals refer
`to like elements throughout. It will be understood that when
`an element such as a layer, film, region, or substrate is
`referred to as being "on" another element, it can be directly
`on the other element or intervening elements may also be
`present.
`
`[0047] Hereinafter, TFT array panels and methods of
`manufacturing the same according to preferred embodi(cid:173)
`ments of the present invention will be described with
`reference to the accompanying drawings.
`
`[0048] Optic masks for crystallization according to the
`preferred embodiments of the present invention include first
`slits having a first length and second slits having a second
`length. This will be described in the description of manu(cid:173)
`facturing methods of a TFT array panel.
`
`BLUEHOUSE EXHIBIT 1006
`Page 31 of 38
`
`

`

`US 2005/0173752 Al
`
`Aug. 11,2005
`
`[0049] Embodiment 1>
`[0050] Referring to FIG. 1 and FIG. 2, a blocking layer
`111 made of silicon oxide, etc. is formed on a transparent
`insulating substrate 110. A semiconductor layer 150 is
`formed on the blocking layer 111 and includes a source
`region 153 and a drain region 155 which are doped with
`impurities, and a channel region 154 which is made of
`intrinsic semiconductor and is interposed between the source
`region 153 and the drain region 155. The semiconductor
`layer 150 further comprises lightly doped drain (LDD)
`regions 152 formed between the source region 153 and the
`channel region 154, and between the drain region 155 and
`the channel region 154.
`
`[0051] The LDD regions 152 prevent leakage current and
`a "punch through" phenomenon. The source region 153 and
`the drain region 155 are doped with conductive impurities of
`high concentration, whereas the LDD regions 152 are doped
`with conductive impurities of low concentration.
`
`[0052] The conductive impurities are either P-type or
`N-type. Boron (B) or gallium (Ga) may be used as the P-type
`and phosphorus (P) or arsenic (As) can be used as the
`N-type.
`
`[0053] A gate insulating layer 140 made of silicon nitride
`(SiNx) or silicon oxide (Si02) is formed on the semicon(cid:173)
`ductor layer 150. A gate line 121 extending in a transverse
`direction is formed on the gate insulating layer 140. A
`portion of the gate line 121 extends to the semiconductor
`layer 150 and overlaps the channel region 154 to form a gate
`electrode 124. The LDD regions 152 can be overlapped with
`the gate electrode 124.
`
`[0054] Also, a storage electrode line 131 is formed in
`parallel with the gate line 121. The storage electrode line 131
`and the gate line 121 are made of the same material on the
`same layer. A portion of the storage electrode line 131
`overlaps the semiconductor layer 150 to form a storage
`electrode 133. The potion of the semiconductor layer 150
`overlapped with the storage electrode 133 becomes a storage
`electrode region 157. An end of the gate line 121 can be
`formed wider than the rest of the gate line 121 to connect
`with the exterior circuitry (not shown).
`
`[0055] A first interlayer insulating layer 601 is formed on
`the gate insulating layer 140, the gate line 121, and the
`storage electrode line 131. The first interlayer insulating
`layer 601 includes a first contact hole 161 and a second
`contact hole 162 through which the source region 153 and
`the drain region 155 are exposed, respectively.
`
`[0056] A data line 171 is formed on the first interlayer
`insulating layer 601. When a pair of the data lines 171 in
`parallel and a pair of the gate lines 121 in parallel are
`intersected, a pixel region is defined therein. The portion of
`the data line 171 is connected with the source region 153
`through the first contact hole 161 to form a source electrode
`173 of TFT. An end of the data line 171 may be formed
`wider than the rest of the data line 171 to connect with the
`exterior circuitry.
`
`[0057] A drain electrode 175 is formed on the same layer
`as the data line 171, having a predetermined distance from
`the source electrode 173. The drain electrode 175 is con(cid:173)
`nected with the drain region 155 through the second contact
`hole 162.
`
`[0058] A second interlayer insulating layer 602 is formed
`on the first interlayer insulating layer 601, the drain elec(cid:173)
`trode 175, and the data line 171. The second interlayer
`insulating layer 602 includes a third contact hole 163
`through which the drain electrode 175 is exposed.
`
`[0059] A pixel electrode 190 is formed on the second
`interlayer insulating layer 602 and is connected with the
`drain electrode 175 through the third contact hole 163.
`
`[0060] Hereinafter, a method of manufacturing the above-
`mentioned TFT array panel will be described with reference
`to FIG. 3A through 9A, along with the above-referenced
`FIG. 1 and FIG. 2.
`
`[0061] As shown in FIG. 3A and FIG. 3B, a blocking
`layer 111 is formed on a transparent insulating substrate 110.
`The transparent insulating substrate 110 can be made of
`glass, quartz, sapphire, etc. The blocking layer 111 is formed
`by depositing silicon oxide (Si02) or silicon nitride (SiNx)
`with about 1000A thick. Then, clean the surface to remove
`impurities such as natural oxide layer from the blocking
`layer 111.
`
`[0062] An intrinsic amorphous silicon layer is formed with
`the range of 400A to 1200A thick by a chemical vapor
`deposition (CVD), etc.
`
`[0063] Next, the amorphous silicon layer is crystallized by
`the sequential lateral solidification (SLS) process to form a
`poly crystalline silicon layer. The poly crystalline silicon
`layer is patterned by a photolithography using an optic mask
`to form a semiconductor layer 150.
`
`[0064] The details of the crystallization process are
`described with reference to FIG. 4 and FIG. 5.
`
`[0065] FIG. 4 is a plan view showing arrangement of slits
`in an optic mask according to an embodiment of the present
`invention and FIG. 5 is a plan view showing the transfer
`state of optic masks according to an embodiment of the
`present invention.
`
`[0066] To poly-crystallize the amorphous silicon, an optic
`mask having a regular pattern, as shown in FIG. 4, is
`arranged on the amorphous silicon layer. The optic mask of
`FIG. 4 includes two regions A and B having the same
`pattern. Each region includes a plurality of slits which are
`arranged in a row and have a regular distance therebetween.
`The slits are passages of laser beams. Here, the slits of the
`regions A and B are arranged to deviate from each other and
`to slope by a predetermined angle to the transfer direction of
`the optic mask in the crystallization process.
`
`In the poly crystalline silicon TFT, the character(cid:173)
`[0067]
`istics of the TFT depends on the grain size and the boundary
`position of the grains of the silicon. Because the grain length
`of the silicon grain is similar to or a little less than the
`channel distance of the TFT, when the silicon boundary is
`parallel to the channel direction, some TFT may include one
`silicon grain boundary in the channel, some TFT may
`include two silicon grain boundary in the channel, and some
`TFT may include no silicon grain boundary in the channel.
`In this case, the TFT characteristics may not be uniform
`through the whole display area. If the boundary of the silicon
`grain is inclined at a certain angle to the TFT channel, the
`characteristics of the TFT will be much more uniform
`through the whole display area.
`
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`

`US 2005/0173752 Al
`
`Aug. 11,2005
`
`[0068] To make the silicon grain boundary to be inclined
`from the TFT channel, the TFT channel can be inclined from
`the display when the grain boundary is parallel to the
`display. Another solution is crystallizing the silicon to an
`inclined direction from the display when the TFT channel is
`parallel to the display. To do this, inclining the substrate
`from the photo mask transferring direction is one way,
`inclining the photo mask pattern from the mask transferring
`direction is another way.
`[0069]
`It is preferable that the uppermost slit SI which is
`provided at the uppermost portion of each region A and B is
`longer than the other slits S2 which are provided in the rest
`portion of each region A and B. The uppermost slit SI may
`be provided more than one in each region A and B. It is also
`preferable that the more inclined the slit from the transfer
`direction of the mask, the more of the uppermost slit SI.
`[0070] Through the slits SI and S2 arranged in the optic
`mask, a laser beam is irradiated to the amorphous silicon
`layer, so that laser-irradiated amorphous silicon changes into
`liquid state while non-irradiated amorphous silicon remains
`in solid state. Accordingly, the crystallization begins from
`the border of the solid and liquid, and grains are vertically
`grown to the border of the solid and liquid.
`[0071] Next, as shown in FIG. 5, a laser beam is irradiated
`to crystallize the amorphous silicon layer while the optic
`mask is horizontally transferred. The grains grow until the
`grains meet each other. After completing a horizontal trans(cid:173)
`lation and laser irradiation, the optic mask is vertically
`translated and another horizontal translation and laser irra(cid:173)
`diation in the opposite direction is successively performed to
`crystallize the amorphous silicon layer. That is, the optic
`mask is transferred in zigzag fashions to crystallize the
`amorphous silicon layer. Transfer of the optic mask and laser
`irradiation are performed through the entire amorphous
`silicon layer.
`[0072] When one silt SI disposed at the uppermost portion
`is longer than the other slits S2, the amorphous silicon
`positioned at the border portions Q of shots can be com(cid:173)
`pletely crystallized even when misalignment is occurred in
`the transferring optic mask.
`[0073] Here, it is preferable that the uppermost slit SI is
`longer than the other slits S2 by the margin of misalignment
`of the mask. In this embodiment, the uppermost slit SI is
`longer than the other slits S2 by 3 fan to 4 fan. Also
`preferably, the number of the uppermost slit SI can be plural
`depending on the slope angle of the slits SI and S2.
`[0074] As shown in FIGS. 6A and 6B, insulating material
`such as SiNx, Si02, etc. is deposited on the semiconductor
`layer 150 by CVD process to form a gate insulating layer
`140. Subsequently, a metal layer is deposited on the gate
`insulating layer 140 as a single layer or multi layers. The
`metal layer is made of at least one of silver (Ag), copper
`(Cu), titanium (Ti), aluminum (Al), tungsten (W), molyb(cid:173)
`denum (Mo), and alloy thereof.
`[0075] After forming the metal layer, a photoresist layer is
`deposited on the metal layer, and etched using a photo mask
`to form a photoresist pattern. The metal layer is etched by
`wet etching or dry etching to form a gate line 121 and a
`storage electrode line 131. At this time, the metal layer is
`over-etched in order that the gate line 121 and the storage
`electrode 131 have narrower widths than that of the photo(cid:173)
`resist pattern.
`
`[0076] The gate line 121 and the storage electrode 131
`have tapered lateral sides, so that the gate line 121 and the
`storage line 131 can be adhered more tightly with the
`overlying layer. In addition, it is possible to omit the storage
`electrode 131 if storage capacitance is sufficient without the
`storage electrode 131.
`
`[0077] Then, the semiconductor layer 150 is heavily
`doped with conductive impurities using a mask of the
`photoresist pattern to form a source region 153 and a drain
`region 155.
`
`[0078] Subsequently, as shown in FIG. 7, the semicon(cid:173)
`ductor layer 150 is lightly doped with conductive impurities
`using a mask of the gate line 121 and the storage electrode
`131 after the photoresist pattern is removed, thereby com(cid:173)
`pleting the semiconductor layer 150 having LDD regions
`152. Here, if the gate line 121 is not made of a material
`having high thermostability and high chemical property,
`such as titanium (Ti), the impurities can be doped after
`forming another photoresist pattern to reduce damage of
`interconnections.
`
`In the above, the LDD regions 152 are formed by
`[0079]
`using the photoresist pattern, but it can be formed without
`photoresist pattern if the metal layers having different etch(cid:173)
`ing ratios are provided or a pair of spacers is formed to each
`sidewall of the gate line 121.
`
`[0080] Additionally, since the semiconductor layer 150,
`the storage electrode line 131, and the storage electrode 133
`are different in width and length, portions of the semicon(cid:173)
`ductor layer 150 are not covered with the storage electrode
`line 131 and the storage electrode 133. The uncovered
`portions 150A also have the impurities and are adjacent to
`the storage electrode region 157. The uncovered portions
`150A are separated from the drain region 155.
`
`[0081] Next, as shown in FIG. 8A and FIG. 8B, a first
`interlayer insulating layer 601 is formed on the entire
`substrate 110, and then etched to form a first contact hole
`161 and a second contact hole 162 where the source region
`153 and the drain region 155 are respectively exposed.
`
`[0082] The first interlayer insulating layer 601 can be
`made of an organic material having prominent planarization
`property and photosensitivity, an insulating material having
`low dielectric constant such as a-Si:C:0 and a-Si:0:F, which
`are formed by plasma enhanced chemical vapor deposition
`(PECVD), or an inorganic material such as SiNx, etc.
`
`[0083] Next, a metal layer made of tungsten (W), titanium
`(Ti), aluminum (Al), or alloy thereof is deposited on the first
`interlayer insulating layer 601 as a single layer or multi
`layers. The metal layer is then patterned by photo etching
`process to form a data line 171 including a source electrode
`173 which is connected with the source region 153 through
`the contact hole 161, and to form a drain electrode 175
`which is connected with the drain region 155 through the
`contact hole 162.
`
`[0084] The data line 171 and the drain electrode 175 have
`tapered lateral sides, so that the data line 171 and the drain
`electrode 175 can be adhered more tightly with the overlying
`layer.
`
`[0085] As shown in FIG. 9A and FIG. 9B, a second
`interlayer insulating layer 602 is formed to cover the data
`line 171 and the drain electrode 175. Then, the second
`
`BLUEHOUSE EXHIBIT 1006
`Page 33 of 38
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`

`US 2005/0173752 Al
`
`Aug. 11,2005
`
`interlayer insulating layer 602 is patterned by photo etching
`process to form a third contact hole 163 through which the
`drain electrode 175 is exposed. The second interlayer insu(cid:173)
`lating layer 602 can be made of the same material as the first
`interlayer insulating layer 601.
`[0086] Next, as shown in FIG. 1 and FIG. 2, a transparent
`conductive material such is as indium zinc oxide (IZO),