Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1003
`
`EX. 1003
`
`
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1003
`
`EX. 1003
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01393
`
`U.S. PATENT NO.9,293,545 B2
`
`_____________________________
`
`
`DECLARATION OF RICHARD A. FLASCK
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`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
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`BLUEHOUSE EXHIBIT 1003
`Page 2 of 75
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`I, Richard A. Flasck, declare as follows:
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`
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`I.
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`INTRODUCTION
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`1.
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`I am over the age of twenty-one (21) and am competent to make this
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`Declaration.
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`2.
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`I am an independent consultant in liquid crystal display (“LCD”)
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`technology, including manufacturing processes and product design.
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`A. Engagement
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`3.
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`I have been retained by counsel for BlueHouse Global Ltd. in the
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`above-captioned Inter Partes Review (“IPR”) matter as an independent technical
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`expert.
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`4.
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`As part of this engagement, I have been retained to review and
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`evaluate whether certain patents and publications disclose to a person of ordinary
`
`skill in the art (“POSA”) the subject matter of specific claims of United States
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`Patent No. 9,293,545 B2 (“the ‘545 Patent”) as of the time of the filing date of the
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`application from which the ‘545 Patent issued. I expect to testify regarding the
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`matters set forth in this declaration if asked to do so.
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`5.
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`I am being compensated on an hourly basis for my work performed in
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`connection with this case. I have received no additional compensation for my work
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`in this case, and my compensation does not depend upon the contents of this
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`report, any testimony I may provide, or the ultimate outcome of the case.
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`B.
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`6.
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`Background and Qualifications
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`I earned my Bachelor of Science degree in Physics from the
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`University of Michigan in 1970. I subsequently earned my M.S. in Physics at
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`Oakland University in 1976.
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`7.
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`I have nearly fifty (50) years of experience in hi tech product
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`development, including all aspects of LCD systems and technologies, through
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`positions ranging from research and development to manufacturing at multiple
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`large and small technology companies. I have led engineering teams to develop
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`Liquid Crystal on Silicon (LCOS) microdisplay technology. I played a significant
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`part in the early development of amorphous silicon thin film transistor (TFT)
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`active matrix Liquid Crystal Displays (AMLCD), including designing the world’s
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`first amorphous silicon TFT LCD pilot line in 1986. I have experience in TFT
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`process and circuit design, data driver and gate driver design, scalers, video
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`circuits, backlighting, and inverter design. I also have a solid functional
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`background in all display technologies, their applications and associated process
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`and manufacturing technologies.
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`8.
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`I am an inventor or co-inventor of 26 patents, including patents on
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`various aspects of LCD technology, including TFT structure and fabrication. A list
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`3
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`of my patents is included in my curriculum vitae, a copy of which is attached
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`hereto as Appendix B.
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`9.
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`A detailed description of my professional qualifications, including a
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`listing of my specialties/expertise and professional activities, is contained in my
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`curriculum vitae, a copy of which is attached hereto as Appendix B.
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`C. Basis of My Opinions and Materials Considered
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`10.
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`In forming my opinions, I have relied upon my education, knowledge
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`and experience with LCDs and related technologies, including manufacturing
`
`processes. I have also relied upon my education, knowledge and experience with
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`electronic design, mechanical design, and processes and materials for LCD
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`manufacture.
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`11. For this work, I reviewed and considered the following materials:
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` U.S. Patent No. 9,293,545 B2 (“the ‘545 Patent”; Ex. 1001), including
`
`the specification and claims; and
`
` The prosecution history of United States Patent Application No.
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`14/451,680(“the ‘680 Application”), i.e., the prosecution history of
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`the ‘545 Patent (Ex. 1002);
`
`In forming my opinions, I have relied upon my education, knowledge and
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`experience with LCD technologies, including manufacturing processes and product
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`design. I have also relied upon my education, knowledge and experience with
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`
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`4
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`electronic design, mechanical design, and materials for LCDs and components
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`thereof.
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`
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`12.
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`I have also been asked to review the subject matter disclosed by
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`various patents and publications that are prior art to the ‘545 Patent, and have been
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`further asked to compare the subject matter disclosed by those patents and
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`publications to claims 1, 3-5, 7-11, 13-15 and 17-20 of the ‘545 Patent and
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`determine whether those patents and printed publications taught the claimed
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`subject matter to a POSA prior to the earliest effective filing date of the ‘545
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`Patent, which I have been instructed to assume is November 7, 2008 for purposes
`
`of my analysis. The principal documents that I have analyzed with regard to their
`
`teachings of subject matter claimed in the ‘545 Patent are listed below:
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`
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`United States Patent Application Publication No. 2008/0299693 A1 to
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`Toyota et al. (“Toyota”; Ex. 1004); and
`
`
`
`
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`United States Patent Application Publication No. 2007/0072439 A1 to
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`Akimoto et al. (“Akimoto”; Ex. 1005).
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`Additional documents that I have analyzed are provided on the list of Exhibits
`
`attached hereto as Appendix A.
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`
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`
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`5
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`II.
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`PATENT PRINCIPLES
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`13.
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`I am an engineer by trade, and the opinions I express in this
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`declaration involve the application of my engineering knowledge and experience to
`
`the evaluation of certain prior art with respect to the ‘545 Patent. I am not a lawyer
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`and have not been trained in the law of patents. Therefore, I have requested the
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`attorneys from Taft, Stettinius & Hollister, who represent BlueHouse Global, to
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`provide me with guidance as to the applicable patent law in this matter. The
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`paragraphs below express my understanding of how I must apply current legal
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`principles related to patent validity to my analysis.
`
`14.
`
`It is my understanding that in determining whether a patent claim
`
`under inter partes review before the United States Patent Office (PTO) is
`
`anticipated or obvious in view of the prior art, the PTO must construe the claim by
`
`giving the claim its broadest reasonable interpretation consistent with the
`
`specification as the claim terms and specification would be understood by a POSA.
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`It is my understanding that the broadest reasonable interpretation is the plain
`
`meaning, i.e., the ordinary and customary meaning, given to the term by a POSA at
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`the time of the invention, taking into account whatever guidance, such as through
`
`definitions, may be provided by the written description in the patent, without
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`importing limitations from the specification. For the purposes of this review, I have
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`construed each claim term in accordance with its plain meaning, i.e., its ordinary
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`and customary meaning under the required broadest reasonable interpretation.
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`It is my understanding that a claim is anticipated under 35 U.S.C. § 102 if each and
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`every limitation of the claim is disclosed in a single prior art reference, either
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`expressly or inherently. I understand inherent disclosure to mean that the claim
`
`feature necessarily flows from the disclosure of the prior art reference. I understand
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`that a claim is unpatentable under 35 U.S.C. § 103 if the claimed subject matter as a
`
`whole would have been obvious to a POSA at the time of the alleged invention,
`
`which I have been instructed to treat at present as the earliest effective filing date of
`
`the ‘545 Patent. I also understand that an obviousness analysis takes into account
`
`the scope and content of the prior art, the differences between the claimed subject
`
`matter and the prior art, and the level of ordinary skill in the art at the time of the
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`invention. Finally, I understand that I must consider any known secondary evidence
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`that might show nonobviousness of the application, such as long felt but unfulfilled
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`need for the claimed invention, failure by others to come up with the claimed
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`invention, commercial success of the claimed invention, praise of the invention by
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`others in the field, unexpected results achieved by the invention, the taking of
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`licenses under the patent by others, expressions of surprise by experts and those
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`POSAs at the making of the invention, and the patentee proceeded contrary to the
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`conventional wisdom of the prior art. But the secondary evidence must be tied
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`
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`7
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`specifically to claim features that are argued to be patentable, and not those already
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`in the public domain. I appreciate that secondary considerations must be assessed
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`as part of the overall obviousness analysis (i.e., as opposed to analyzing the prior
`
`art, reaching a tentative conclusion, and then assessing whether objective indicia
`
`alter that conclusion).
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`15. Put another way, my understanding is that not all innovations are
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`patentable. Even if a claimed product or method is not explicitly described in its
`
`entirety in a single prior art reference, the patent claim will still be denied if the
`
`claim would have been obvious to a POSA at the time of the patent application
`
`filing.
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`16.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art if it falls within
`
`the field of the inventor’s endeavor. In addition, a reference is prior art if it is
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`reasonably pertinent to the particular problem with which the inventor was
`
`involved. A reference is reasonably pertinent if it logically would have
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`commended itself to an inventor’s attention in considering his problem. If a
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`reference relates to the same problem as the claimed invention, that supports use of
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`the reference as prior art in an obviousness analysis.
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`17. To assess the differences between prior art and the claimed subject
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`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
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`
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`to be considered as a whole. This “as a whole” assessment requires showing that a
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`POSA at the time of invention, confronted by the same problems as the inventor
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`and with no knowledge of the claimed invention, would have selected the elements
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`from the prior art and combined them in the claimed manner.
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`18.
`
`In determining whether the subject matter as a whole would have been
`
`considered obvious at the time that the patent application was filed, by a POSA, I
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`have been informed of several principles regarding the combination of elements of
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`the prior art. First, a combination of familiar elements according to known methods
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`is likely to be obvious when it yields predictable results. Likewise, combinations
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`involving simple substitution of one known element for another to obtain
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`predictable results, a predictable use of prior art elements according to their
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`established functions, applying a known technique to a known device (method or
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`product) ready for improvement to yield predictable results, and choosing from a
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`finite number of identified, predictable solutions to solve a problem are likely to be
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`obvious. Thus, if a POSA can implement a “predictable variation” in a prior art
`
`device, and would see the benefit from doing so, such a variation would be obvious.
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`Also, when there is pressure to solve a problem and there are a finite number of
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`identifiable, predictable solutions, it would be reasonable for a POSA to pursue
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`those options that fall within his or her technical grasp. If such a process leads to
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`the claimed invention, then the latter is not an innovation, but more the result of
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`ordinary skill and common sense.
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`19.
`
`I also understand that the “teaching, suggestion, or motivation” test is
`
`a useful guide in establishing a rationale for combining elements of the prior art.
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`This test poses the question as to whether there is an explicit teaching, suggestion,
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`or motivation in the prior art to combine prior art elements in a way that realizes
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`the claimed invention. Though useful to the obviousness inquiry, I understand that
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`this test should not be treated as a rigid rule. It is not necessary to seek out precise
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`teachings; it is permissible to consider the inferences and creative steps that a
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`POSA (who is considered to have an ordinary level of creativity and is not an
`
`“automaton”) would employ.
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`20.
`
`It is my understanding that when interpreting the claims of the ‘545
`
`Patent I must do so based on the perspective of a POSA at the relevant priority
`
`date. My understanding is that the earliest priority date that is claimed by the ‘545
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`Patent is November 7, 2008.
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`
`
`III. TECHNOLOGY BACKGROUND
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`21. Semiconductor devices are electronic components that exploit the
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`electronic properties of semiconductor materials, such as silicon. Semiconductor
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`materials are useful because their behavior can be easily manipulated by the
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`addition of impurities, known as doping. Current conduction in a semiconductor
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`occurs via mobile or “free” electrons and holes, collectively known as charge
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`carriers. Doping a semiconductor such as silicon with a small proportion of an
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`atomic impurity, such as phosphorus, greatly increases the number of free electrons
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`or holes within the semiconductor (a doped semiconductor containing excess holes
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`is called “p-type”; one containing excess free electrons is known as “n-type”).
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`22. A thin film transistor, or TFT, is an example of semiconductor device.
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`TFTs can be used as simple ON/OFF switches in a wide variety of electrical
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`devices, such as active-matrix LCD displays. Basically, a TFT consists of a
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`semiconductor and three electrodes: (i) the gate electrode; (ii) the source electrode;
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`and (iii) the drain electrode. The gate electrode must be insulated from the
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`semiconductor by a dielectric layer (or gate insulation layer), while the drain
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`electrode and source electrode must both directly contact the semiconductor.
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`Because of this, TFTs generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being one the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`
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`
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`IV. PERSON OF ORDINARY SKILL IN THE ART
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`
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`23. A United States patent is to be read and understood from the
`
`perspective of a person of ordinary skill in the relevant art (technical field) at the
`
`time the invention was made. Here, the relevant date is November 7, 2008, i.e.
`
`when the inventors named on the ‘545 Patent filed the original Japanese patent
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`application to the subject matter now claimed in the ‘545 Patent and to which
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`priority is claimed.
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`
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`24.
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`It is my understanding that a person of ordinary skill in the art is a
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`hypothetical person presumed to know the relevant prior art. Such a person is of
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`ordinary creativity, not merely an automaton, and is capable of combining the
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`teachings of the prior art. The factors that may be used to determine the level of
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`skill of a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
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`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`
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`25.
`
`In this case, the ‘545 Patent is directed to the structure of a
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`semiconductor device, such as the thin film transistors (“TFTs”) found in many
`
`display devices. A person of ordinary skill in the art should therefore have some at
`
`least some familiarity with the practical aspects of TFT structure and fabrication.
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`More specifically, a person of ordinary skill in the art of the ‘545 Patent as of
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`November 7, 2008, would have had at least a bachelor of science or engineering
`
`degree in electrical or mechanical engineering, semiconductor technology, display
`
`technology, physics, or a related field, and either an advanced degree (such as a
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`masters) or an equivalent amount of work experience, i.e. 2-3 years, in an area
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`relating to semiconductor design and/or fabrication, liquid crystal display (“LCD”)
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`design or fabrication, electrical engineering, or a related technical field.
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`26. Based on my experience, I have an understanding of the capabilities
`
`of a POSA in the relevant field. I have supervised and directed many such persons
`
`over the course of my career. Further, I had those capabilities myself at the time
`
`the ‘545 Patent was effectively filed.
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`
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`V. OVERVIEW OF THE ‘545 PATENT
`
`27. The ‘545 Patent (Ex. 1001) is entitled “Semiconductor Device” and
`
`names Shunpei Yamazaki et al. as the inventors.
`
`
`
`
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`28. According to the specification, the ‘545 Patent relates to display
`
`devices that include an oxide semiconductor. Ex. 1001 at 1:6-7. The specification
`
`discloses that
`
`One embodiment of the present invention disclosed in this
`specification is a semiconductor device wherein a gate electrode is
`formed over a substrate having an insulating surface, an insulating
`layer is formed over the gate electrode, a source and drain electrodes
`are formed over the insulating layer, an oxide semiconductor layer is
`formed between their respective side surfaces of the source and drain
`electrodes, which face each other, so as to overlap with the gate
`electrode with the insulating layer interposed therebetween, and the
`angle formed between the surface of the substrate and the side surface
`of the source electrode and the angle formed between the surface of
`the substrate and the side surface of the drain electrode are each
`greater than or equal to 20° and less than 90°.
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`Ex. 1001 at 1:57-2:3. The specification further discloses that, with respect to the
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`source and drain electrodes,
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`The source electrode layer 405a and the drain electrode layer 405b
`each are a single layer or a stacked layer made of different metal
`materials. As a material of each of the source electrode layer 405a and
`the drain electrode layer 405b, a metal material (an element selected
`from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta),
`tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd),
`and scandium (Sc), or an alloy including the element as a component)
`is used.
`
`Ex. 1001 at 11:21-29. The specification also discloses that
`
`
`The two side surfaces of the electrodes which face each other with the
`oxide semiconductor layer 403 interposed therebetween each have a
`step, so that the distance from the top edge to the bottom edge of the
`electrode in the side surface of each electrode is increased, thereby
`increasing length L3 of a first electric-field relaxation region 406a and
`length L4 of a second electric-field relaxation region to relax the
`electric-field concentration.
`
`Ex. 1001 at 12:13-20.
`
`
`VI. PROSECUTION HISTORY OF THE ‘545 PATENT
`
`
`
`29. The ‘545 Patent claims the benefit of the filing date of prior U.S.
`
`Patent Application No. 13/763,874 (“the ‘874 application”), which was filed on
`
`February 11, 2013 and subsequently issued as U.S. Patent No. 8,803,146. Ex.
`
`1002 at 1422. The ‘874 application claimed the benefit of the filing date of prior
`
`U.S. Patent Application No. 12/613,769 (“the ‘769 application), which was filed
`
`on November 6, 2009 and subsequently issued as U.S. Patent No. 8,373,164. Id.
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`The ‘769 application claimed the benefit of the filing date of prior U.S. Patent
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`Application No. 12/606,262 (“the ‘262 application”), which was filed on October
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`27, 2009 and subsequently abandoned. Id. The ‘262 application claimed the
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`benefit of the filing date of Japanese application no. 2008-287187, which was filed
`
`on November 7, 2008. Id. at 1423. None of the claims presented in the ‘874
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`application or issued in the ‘545 patent, however, was previously presented in any
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`prior application in this family.
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`
`
`30. The primary reference relied upon herein, Toyota, was not cited or
`
`considered during the prosecution of the ‘545 Patent. The secondary reference,
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`Akimoto, however, was cited by the examiner during prosecution of the ‘874
`
`application, but only for the teaching of an oxide semiconductor film. Akimoto is
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`not being relied upon for such a teaching here.
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`
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`VII. CLAIM CONSTRUCTION
`
`31. Counsel for Petitioner has provided me with their proposals for the
`
`broadest reasonable interpretation (BRI) claim constructions for the terms listed
`
`below. I concur with those proposed constructions for the reasons explained below.
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`
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`32.
`
`“semiconductor device” (claims 1, 3-5, 7-11, 13-15 and 17-20): This
`
`term appears in the preamble of all of the challenged claims. The specification of
`
`the ‘545 Patent exemplifies thin film transistors for use as switching elements in a
`
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`display device as illustrative examples of the disclosed and claimed semiconductor
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`devices. Ex. 1001 at 1:11-30. The claim term semiconductor device should be
`
`construed to mean “a device that functions by utilizing semiconductor
`
`characteristics, such as a thin film transistor.”
`
`
`
`33.
`
`“in contact with” (claims 1, 3-5, 7-11, 13-15 and 17-20): This term
`
`appears in all of the challenged claims in the limitations regarding the first metal
`
`film, second metal film and oxide semiconductor layer elements of the claimed
`
`semiconductor device. The specification of the ‘545 Patent does not define this
`
`term, but the FIGS. show that layers identified in the specification as being “in
`
`contact with” one another (e.g. the first metal film and the gate insulating layer; the
`
`second metal film and the oxide semiconductor layer) all appear to be physically
`
`touching each other at one or more points. The claim term in contact with should
`
`be construed to mean “physically touching.”
`
`
`
`34.
`
`“faces” (claims 1, 3-5, 7-11, 13-15 and 17-20): This term appears in
`
`all of the challenged claims with respect to the first metal film and second metal
`
`film elements. The specification of the ‘545 Patent does not expressly define this
`
`term (it actually appears nowhere in the entire specification of the ‘545 patent), but
`
`the FIGS. show that a surface which “faces” another surface according to the
`
`claims (e.g. a side surface of the first metal film and a side surface of the second
`
`
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`metal film) appear to oppose one another. The claim term faces should be
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`construed to mean “opposes.” Id.
`
`
`
`35.
`
`“over” (claims 1, 3-5, 7-11, 13-15 and 17-20): This term appears in
`
`all of the challenged claims. The specification of the ‘545 Patent defines this term,
`
`teaching “[i]In this specification, a word which expresses a direction, such as
`
`‘over’, ‘below’, ‘side’, ‘horizontal’, or ‘vertical’, indicates a direction based on the
`
`substrate surface in the case where a device is provided over the surface of the
`
`substrate.” Ex. 1001 at 6:29-32. The claim term over should be construed to mean
`
`“above.”
`
`
`
`VIII. SUMMARY OF OPINIONS
`
`36. Based on my review of the ‘545 Patent, its prosecution history, and
`
`the patents and publications listed above, it is my opinion that the subject matter of
`
`claims 1, 3-5, 7-11, 13-15 and 17-20 of the ‘545 Patent was, as of the effective
`
`filing date of the ‘545 Patent, unpatentable as either anticipated or obvious in view
`
`of the various prior art references identified, the grounds for which are listed and
`
`explained below.
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`
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`IX. UNPATENTABILITY OF CLAIMS 1, 3-5, 7-11, 13-15 and 17-20
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`
`
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`
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`A. Challenge #1: Claims 1, 5, 7-11, 15 and 17-20 are anticipated
`
`under pre-AIA 35 U.S.C. § 102(e) by Toyota
`
`37. Toyota anticipates each of claims 1, 5, 7-11, 15 and 17-20of the ‘545
`
`Patent. That is, “each and every element” of claims 1, 5, 7-11, 15 and 17-20of the
`
`‘545 Patent is identically disclosed by Toyota, “arranged or combined in the same
`
`way as in the claim.” Specifically, in at least FIG. 8B and the accompanying text
`
`in the specification, Toyota discloses a thin film transistor (for use in, e.g., a
`
`display device) having all of the same layers that are recited in each of claims 1, 5,
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`7-11, 15 and 17-20and those layers are arranged in the same order as required by
`
`those claims.
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`
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`38. Toyota’s FIG. 8B, showing a thin film transistor, is reproduced below:
`
`where:
`
`
`
`
`
`GT is the gate electrode (Ex. 1004 at ¶ 135);
`
`DT(U) and DT(D) are each conductive layers that together form the drain
`
`electrode (Id. at ¶ 136);
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`
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`19
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`BLUEHOUSE EXHIBIT 1003
`Page 20 of 75
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`ST(U) and ST(D) are each conductive layers that together form the source
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`electrode (Id.); and
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`
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`GI is the gate insulating layer (Id. at ¶ 135).
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`The semiconductor layer PS is not labeled in this FIG. The semiconductor layer
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`PS, however, is the layer immediately above the gate insulating layer GI and
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`includes darkened portions to represent the doped regions and a shaded portion to
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`represent the channel region.
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`
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`
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`
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`1.
`
`
`
`Claim 1
`
`a.
`
`The preamble
`
`39. The preamble of claim 1 recites “[a] semiconductor device comprising
`
`. . ..” Ex. 1001 at 43:21. To the extent that this preamble is deemed a limitation,
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`this limitation is expressly disclosed by Toyota.
`
`
`
`40. The ‘545 Patent identifies thin film transistors a type of
`
`semiconductor device within the scope of claim 1. More specifically, the ‘545
`
`Patent states that
`
`The present invention relates to a display device using an oxide
`semiconductor and a method for manufacturing the same. . .. As
`typically seen in liquid crystal display devices, a thin film transistor
`formed over a flat plate such as a glass substrate is manufactured
`using amorphous silicon or polycrystalline silicon.
`
`Ex. 1001 at 1:6-13.
`
`
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`20
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`BLUEHOUSE EXHIBIT 1003
`Page 21 of 75
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`
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`
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`41. Toyota also discloses thin-film transistors (“TFTs”) and, more
`
`specifically, bottom gate TFTs. With reference to FIGS. 8A-8C, Toyota teaches
`
`that “in the thin film transistor formed on the pixel, a so-called bottom gate type
`
`thin film transistor, in which the gate electrode is located on the lower layer of the
`
`semiconductor layer, is constituted.” Ex. 1004 at ¶¶ 134-135.
`
`
`
`42. Accordingly, to the extent the preamble is limiting, this limitation is
`
`identically disclosed by Toyota.
`
`
`
`
`
`
`
`
`
`b.
`
`a glass substrate
`
`43. The first element of the semiconductor device of claim 1 of the ‘545
`
`Patent is a glass substrate. Ex. 1001 at col. 43:22. Toyota identically discloses this
`
`element.
`
`
`
`44. Toyota discloses a TFT having a glass substrate. Ex. 1004 at ¶¶ 52,
`
`135. Referring to FIG. 8B, Toyota teaches that
`
`as shown in FIG. 8B, for example, in the formation region for the n-
`channel type thin film transistor NTFT, a structure in which the gate
`electrode GT, the insulating film (first insulating film) GI, the
`semiconductor layer PS, and the insulating film (second insulating
`film) IN are sequentially stacked is formed on a surface of the
`undercoat layer FL of the substrate SUB1.
`
`Ex. 1004 at ¶ 135. Toyota further teaches that substrate SUB1 is made of glass,
`
`i.e., “[i]n FIG. 2, a substrate SUB1 made of, for example, glass is shown.” Id. at ¶
`
`52.
`
`
`
`
`
`45. Toyota therefore identically discloses a glass substrate.
`
`21
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`BLUEHOUSE EXHIBIT 1003
`Page 22 of 75
`
`
`
`
`
`
`
`
`
`c.
`
`a gate electrode . . .
`
`
`
`46. The second element of the semiconductor device of claim 1 is a gate
`
`electrode over the glass substrate. Ex. 1001 at 43:23. Toyota identically discloses
`
`this element, and in the same arrangement as recited in the claim.
`
`
`
`47. Toyota discloses a TFT having a gate electrode over the glass
`
`substrate. Ex. 1004 at ¶¶ 52, 135. With reference to FIG. 8B, Toyota teaches that
`
`“as shown in FIG. 8B, for example, in the formation region for the n-channel type
`
`thin film transistor NTFT, . . . the gate electrode GT . . . is formed on a surface of
`
`the undercoat layer FL of the substrate SUB1.” Ex. 1004 at ¶ 135.
`
`48. Toyota’s FIG. 8B is reproduced below:
`
`
`
`
`
`As shown in FIG. 8B, the gate electrode GT is on the upper surface of the
`
`undercoat layer FL which is, in turn, on the upper surface of the glass substrate
`
`SUB1. The gate electrode GT is therefore over (above) the glass substrate SUB1.
`
`
`
`49. Toyota therefore identically discloses a gate electrode over the glass
`
`substrate.
`
`
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`22
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`BLUEHOUSE EXHIBIT 1003
`Page 23 of 75
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`
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`
`
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`d.
`
`a gate insulating film . . .
`
`50. The third element of claim 1 of the ‘545 Patent is a gate insulating
`
`film over the gate electrode. Ex 1001 at 43:24. Toyota identically discloses this
`
`element, and in the same arrangement as recited in the claim.
`
`
`
`51. Toyota discloses a TFT having a gate insulating film over the gate
`
`electrode. Ex. 1004 at ¶ 135. Toyota teaches that “as shown in FIG. 8B, for
`
`example, in the formation region for the n-channel type thin film transistor NTFT,
`
`a structure in which the gate electrode GT [and] the insulating film (first insulating
`
`film) GI . . . are sequentially stacked is formed on a surface of the undercoat layer
`
`FL of the substrate SUB1.” Ex. 1004 at ¶ 135.
`
`
`
`52. Toyota’s FIG. 8B is reproduced below:
`
`As shown in FIG. 8B, the gate insulating film GI is on the upper surface of the gate
`
`electrode GT. The gate insulating film GI is therefore over (above) the gate
`
`electrode GT. Id.
`
`
`
`53. Toyota therefore identically discloses a gate insulating film over the
`
`gate electrode.
`
`
`
`23
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`BLUEHOUSE EXHIBIT 1003
`Page 24 of 75
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`
`
`
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`
`
`
`
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`e.
`
`a first metal film and a second metal film . . .
`
`
`
`
`
`54. The fourth element of the claimed semiconductor device is a first
`
`metal film and a second metal film over the gate insulating film. Ex 1001 at 43:25-
`
`26. This element is also disclosed by Toyota, and in the same arrangement as
`
`recited in the claim.
`
`
`
`55. Toyota discloses a TFT having source and drain electrodes, each of
`
`which is made of multiple layers of metal. Ex. 1004 at ¶ 136. Referring to FIG.
`
`8B, Toyota teaches that
`
`in the same manner as shown in FIGS. 3A to 3C, the drain electrode
`DT is composed of a layered product of the lower drain electrode
`DT(D) and the upper drain electrode DT(U) . . . In the same manner,
`the source electrode ST is composed of a layered product of the lower
`source electrode ST(D) and the upper source electrode ST(U) . . ..
`
`Ex. 1004 at ¶ 136.
`
`
`
`56. Toyota further teaches that “the drain electrode DT . . . has the two-
`
`layered structure in which, for example, a conductive layer made of tungsten
`
`having a thickness of about 30 nm and a conductive layer made of aluminum
`
`having a thickness of about 500 nm are sequentially stacked.” Id. at ¶ 72. It is
`
`known by those skilled in the art that both tungsten (W) and aluminum (Al) are
`
`metals.
`
`
`
`57. The source electrode therefore corresponds to the claimed first metal
`
`film and the drain electrode corresponds to the claimed second metal film.
`
`
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`24
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`BLUEHOUSE EXHIBIT 1003
`Page 25 of 75
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`
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`58. An annotated version of Toyota’s FIG. 8B is reproduced below:
`
`
`
`As shown in FIG. 8B, the lower layer of the drain electrode DT(D) and the lower
`
`layer of the source electrode ST(D) are both on the upper surface of the
`
`semiconductor layer (not labeled), and the semic
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