`
`In re Patent of:
`U.S. Patent No.:
`Issue Date:
`Appl. Serial No.:
`Filing Date:
`Title:
`
`Shunpei Yamazaki et al.
`9,293,545 Attorney Docket No.: 12732-1924IP1
`March 22, 2016
`14/451,680
`August 5, 2014
`SEMICONDUCTOR DEVICE
`
`DECLARATION OF Michael Lebby, Ph.D.
`
`I, Michael Lebby, Ph.D., of San Francisco, CA, declare that:
`
`QUALIFICATIONS AND BACKGROUND INFORMATION
`
`1.
`
`I am currently the CEO of Oculi LLC and the CEO & Director of
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`Lightwave Logic. Oculi LLC is my consulting company where I undertake my
`
`expert witness work. Lightwave Logic is a technology company based in Denver,
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`Colorado that is developing optical polymers for fiber optic communications. I
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`have testified as an expert witness and consultant in patent and intellectual
`
`property litigation as well as inter partes reviews and re-examination proceedings.
`
`My curriculum vitae is provided (as SEL2002).
`
`2.
`
`I also serve as a Technical Expert/Consultant for the Photonics Unit of
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`the European Commission. My role is to advise the European Commission in
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`matters that are photonics technology based that have included for example:
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`displays, fiber optic communications, sensing, medical, and biological
`
`applications.
`
`1
`
`SEL 2001
`Bluehouse v. SEL
`IPR2018-01393
`
`
`
`3.
`
`I received a Bachelor of Electrical Engineering degree in 1984, a
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`Master of Business Administration in 1985, and a Doctorate degree in 1987, all
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`from University of Bradford in the United Kingdom. My Ph.D. thesis involved the
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`design and fabrication of both optoelectronic and electronic semiconductor
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`devices, and their associated characterization. In 2004, I was awarded a Doctor of
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`Engineering degree from University of Bradford for my technical contributions to
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`the field, with citation to “Technical Contributions to Optoelectronics.”
`
`4.
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`As described in my curriculum vitae (attached as SEL2002), I have
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`over 30 years of experience in the field of optoelectronics, photonics, and
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`electronic engineering including extensive experience in the research,
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`development, fabrication, and manufacture of semiconductor devices, organic
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`technology, and associated packaging for optical applications such as fiber optic
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`links, general lighting, displays, sensing, etc.
`
`5.
`
`My career started in the late 1970s at the Ministry of Defense in UK
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`where I spent time at their R&D facility in Malvern (RSRE – Royal Signals and
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`Radar Establishment). I worked on semiconductor device design, fabrication, and
`
`characterization. My research work in semiconductor device design then took me
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`to AT&T Bell Laboratories in 1985 where I pursued research in novel device
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`designs using III-V semiconductor material systems. The devices researched
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`became the subject of my Ph.D. thesis that was granted in 1987.
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`2
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`
`
`6.
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`I moved to Motorola in 1989 to further develop my semiconductor
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`engineering and packaging skills and became a Research and Development
`
`Manager for Motorola in the photonics division until I left the company in 1998.
`
`During my time at Motorola, I worked on many electronic and photonic
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`technology projects that included optical interconnects, displays, LEDs, LCDs,
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`lasers, detectors, opto-couplers, integrated circuits (analog and digital), etc., as well
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`as the packaging and reliability of mobile prototypes. At that time, I was
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`particularly interested in miniature displays using a number of technologies such as
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`LEDs, lasers, LCDs, and organic LEDs. I also worked with driver and receiver
`
`based integrated circuits. I collaborated with Motorola’s mobile division on new
`
`and novel display prototypes, and patented a number of new concepts that include
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`an electronic book, electronic wallet, spectacle/eyeglass and binocular based
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`mobile phone designs. I also patented a new semiconductor laser that had potential
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`to be manufactured in high volume. This device was called a VCSEL (vertical
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`cavity surface emitting laser), and is now the basis for the highest volume
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`semiconductor laser today with its recent implementation into Apple’s new iPhone
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`Face ID system. I also initiated Motorola’s work in optical interconnect
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`(Optobus™) and was involved in the IC chip designs that this parallel interconnect
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`module utilized. During this period, I was one of Motorola’s most prolific
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`inventors, having over 150 issued utility patents as inventor or co-inventor. Many
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`3
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`
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`of the photonics prototypes were subjected to reliability and stress testing that
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`included humidity, temperature, optical, mechanical, and electrical evaluation.
`
`7.
`
`Between 1998 and 1999, I worked as the Director of Technology/ BD
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`(Fiber Optics) for Tyco Electronics (previously AMP). I joined Tyco Electronics
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`as a member of the Global Optoelectronics Division’s management team. There, I
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`was responsible for growing the optoelectronics business through external
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`interactions that include mergers, acquisitions, strategic alliances, and technical
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`strategic planning. Much of that work was photonics based that included designing
`
`and characterizing photonics-based modules for customer qualification
`
`specifications.
`
`8.
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`In 1999, I left Tyco and started employment at Intel. At Intel, I was
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`involved heavily in photonic technology and especially those that supported silicon
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`photonic device platforms. As a culmination of this work, I was one of Intel’s
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`founders of its silicon photonics division in the year 2000, and worked to set up a
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`design facility in South San Jose, California. The work looked at integrating
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`silicon FET electronics with optoelectronics onto the same silicon semiconductor
`
`wafer. I was also part of Intel Capital’s optical investment team, and participated
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`on over 30 photonics investments into photonics that included displays and liquid
`
`crystal on silicon (LCOS). Technologies invested included detectors, lasers,
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`LEDs, LCDs, and displays.
`
`4
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`
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`9.
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`In 2001, I founded a fiber optics transceiver company called Ignis
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`Optics that developed and manufactured high speed fiber optic transceivers.
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`Included in the design were micro-controllers as well as standard integrated circuit
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`technology that was designed to both transmit and receive fiber optic data signals.
`
`10.
`
`In 2005, I took up employment with a trade association called OIDA
`
`based in Washington DC. As the head of this trade association, and with photonics
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`manufacturers that included fiber optics, display, sensing, defense, aerospace,
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`lighting, and automotive vendors as members, I was responsible in part for
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`industry-based technology roadmaps and implemented common industry roadmap
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`methodologies with common features such as “Red Brick Walls” and transferred
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`them into optoelectronics roadmaps for the industry where displays were featured.
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`11.
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`In 2010, I became the General Manager and CTO of Translucent, Inc.,
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`a high-tech start-up company which developed and manufactured silicon and rare
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`earth oxide based epitaxial semiconductor wafers. One of the key drivers at
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`Translucent was to develop a new and novel platform for the growth of GaN and
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`InGaN onto silicon for low cost LED as well as power FET manufacturing.
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`Translucent pioneered the deposition of single crystal rare earth oxides such as
`
`Erbium Oxide (ErOx), Gadolinium Oxide (GdOx), Neodymium Oxide (NdOx),
`
`etc., that when grown, single crystal layers of GaN/InGaN/AlN could be grown on
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`top of them. This allows a lattice-matched, and monolithic based wafer template to
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`5
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`
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`be manufactured for LED and FET fabrication. While at Translucent, I invented
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`various epitaxial semiconductor layer structures that utilized rare earth oxide
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`technology to improve the performance of LEDs and FETs. Other material growth
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`work at Translucent focused on the growth of Silicon Germanium (SiGe)
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`compounds with rare earth oxides, and various crystal orientation wafer substrates.
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`Electrical contacts to devices developed at Translucent included the use of ITO
`
`(Indium Tin Oxide), Indium Oxide (IO), and other transparent conducting oxide
`
`(TCO) compounds.
`
`12. As discussed in more detail in my curriculum vitae, I have continued
`
`to work in the semiconductor, electronics, optoelectronics and packaging field
`
`throughout my career.
`
`13.
`
`Throughout my career I have also had an active role in a number of
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`technical, professional organizations, including, among others, IEEE Components,
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`Packaging, and Manufacturing Technology (CPMT), IEEE Electronic Components
`
`and Technology Conferences (ECTC); IEEE TC-10 (Technical Committee on
`
`Optoelectronics), and IEEE Optoelectronics Industry Development Association
`
`(OIDA). Through these organizations, I have consistently been a part of
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`committees, events, and workshops relating to semiconductor, optoelectronics,
`
`electronics and packaging technology.
`
`6
`
`
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`14. My work has also led to over 200 utility patents in semiconductors,
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`electronics, and optoelectronics, and includes a number of patents relating to
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`photonics-based displays both from a technology platform perspective as well as a
`
`packaging perspective. I am the author of more than 60 publications in the field of
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`optoelectronics.
`
`15.
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this declaration and could testify competently to them if asked to do so.
`
`16. My compensation is in no way dependent upon or contingent upon the
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`opinions and testimony that I render during the course of this case. My findings
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`are based on my education, experience, and background in the fields discussed
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`below.
`
`17.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the fields of
`
`electronics and photonics and my experience in working with others involved in
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`those fields at companies such as the British Government, Motorola, AT&T Bell
`
`Labs, Intel, etc. In addition, I have analyzed the following publications and
`
`materials, in addition to other materials I cite in my declaration:
`
`
`
`
`
`
`
`IPR2018-01393 Petition for Inter Partes Review (“petition”)
`
`U.S. Patent No. 9,293,545 (“the ’545 patent”) (Ex. 1001)
`
`Declaration of Richard A. Flasck (Ex. 1003)
`
`7
`
`
`
`
`
`United States Patent Application Publication No. 2008/0299693 to
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`Toyota et al. (“Toyota”) (Ex. 1004)
`
`
`
`United States Patent Application Publication No. 2007/0072439 to
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`Akimoto et al. (“Akimoto”) (Ex. 1005)
`
`
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`United States Patent Application Publication No. 2005/0173752 to
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`Chung et al. (“Chung”) (Ex. 1006)
`
`BACKGROUND KNOWLEDGE ONE OF SKILL IN THE ART WOULD
`HAVE HAD PRIOR TO THE PRIORITY DATE OF THE ’545 PATENT
`
`Brief Overview of the ’545 Patent
`
`18.
`
`Flat-panel displays such as those used in televisions and smartphones
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`can include semiconductor devices such as thin-film transistors (TFTs). A TFT is
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`a field-effect transistor (FET) formed by depositing a thin film of a semiconductor
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`over an insulating substrate such as glass. The semiconductor used in a TFT can
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`include a silicon semiconductor or an oxide semiconductor.
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`19.
`
`Semiconductors can be classified according to the polarity of their
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`majority charge carriers into two different types: n-type and p-type. N-type
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`semiconductors have majority carriers with negative charge (electrons). P-type
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`semiconductors have majority carriers with positive charge (holes). The majority
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`carrier type of a silicon semiconductor is controlled by doping the semiconductor
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`with impurity atoms. Impurity atoms act as either donors or acceptors and change
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`the electron and hole concentrations of the silicon semiconductor.
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`8
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`
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`20.
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`In a silicon semiconductor, impurity doping is used to increase the
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`number of electrons or holes in the silicon semiconductor. For example, a p-type
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`silicon semiconductor is formed when silicon is doped with acceptors, such as
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`boron (B) atoms, so that the majority carriers are holes. An n-type semiconductor
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`is formed when silicon is doped with donors, such as phosphorus (P) atoms, so that
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`the majority carriers are electrons. The semiconductor layer of a transistor can
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`include an n-type silicon semiconductor, a p-type silicon semiconductor, or both.
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`In addition, an ohmic contact of a metal to the semiconductor can be created by
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`heavily doping regions of a silicon semiconductor. Silicon semiconductors can be
`
`used to form complementary metal-oxide-semiconductor (CMOS) transistors.
`
`21.
`
`The ’545 patent generally relates to a semiconductor device having,
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`among other layers, an oxide semiconductor layer. Ex. 1001 at 1:44-56, 2:37-43,
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`3:13-26, 11:13-15. An oxide semiconductor exhibits different characteristics from
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`a silicon semiconductor. For example, an oxide semiconductor is difficult to dope
`
`with impurities to control the majority carrier type or to create metal-
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`semiconductor ohmic contacts. Currently, a transistor with favorable
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`characteristics can be formed using an n-type oxide semiconductor, but is difficult
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`to form using a p-type oxide semiconductor. Therefore, CMOS transistors may be
`
`difficult to form using an oxide semiconductor.
`
`9
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`
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`22. A conventional TFT may exhibit electric field intensity concentrated
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`in the oxide semiconductor layer at and near either the boundary separating the
`
`source electrode from the channel formation region of the oxide semiconductor
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`layer or the boundary separating the drain electrode from the channel formation
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`region of the oxide semiconductor layer, a representation of which is shown in the
`
`figure below.
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`In practice, an upper part of an area where the electric field concentration occurs
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`may be narrower than a lower part of the area where the electric field concentration
`
`occurs, a representation of which is shown in the figure below.
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`The increased concentration of charge carriers induced at the location of the
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`concentrated electric field intensity can affect movement of the charge carriers in
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`the channel formation region and cause deterioration of the TFT’s switching
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`characteristics and transistor performance.
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`23.
`
`To address these problems, I understand that Patent Owner developed
`
`a bottom-gate TFT having an oxide semiconductor layer where the two side
`
`10
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`
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`surfaces of the source and drain electrodes, which face each other, each have a
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`tapered portion so that the distance from the top to the bottom of the side surface of
`
`each electrode is increased. Ex. 1001 at 3:34-45, 12:13-20. The inventors of the
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`’545 patent advanced the state of the art using such a configuration for a bottom-
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`gate TFT having an oxide semiconductor layer, which provides the capability to
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`relax electric field concentration in the oxide semiconductor layer and suppress
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`deterioration of the TFT’s switching characteristics. Ex. 1001 at 1:38-43, 2:63-
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`3:12, 3:34-59, 6:38-48, 10:5-54, 12:13-20. The ’545 patent discloses that a TFT
`
`with such a configuration may allow the region of the oxide semiconductor layer at
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`and near either the boundary separating the source electrode from the channel
`
`formation region of the oxide semiconductor layer or the boundary separating the
`
`drain electrode from the channel formation region of the oxide semiconductor layer
`
`to function as an electric-field relaxation region that relaxes the electric field
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`concentration. Ex. 1001 at 3:9-12.
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`24.
`
`FIG. 2 of the ’545 patent shows an example of a TFT with such a
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`configuration. FIG. 2 of the ’545 patent is reproduced below. FIG. 2 has been
`
`annotated to highlight the source electrode (red layer), the drain electrode (blue
`
`layer), and the oxide semiconductor (purple layer).
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`11
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`
`
`’545 Patent (Ex. 1001), FIG. 2 (annotated)
`
`For the transistor shown above, a bottom portion of the side surface of the source
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`electrode is tapered such that the angle formed between the surface of the substrate
`
`and the bottom portion of the side surface of the source electrode is different from
`
`the angle formed between the surface of the substrate and the top portion of the
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`side surface of the source electrode. Ex.1001 at 4:30-34. In addition, a bottom
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`portion of the side surface of the drain electrode is tapered such that the angle
`
`formed between the surface of the substrate and the bottom portion of the side
`
`surface of the drain electrode is different from the angle formed between the
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`surface of the substrate and the top portion of the side surface of the drain
`
`electrode. Ex. 1001 at 4:34-39.
`
`12
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`
`
`Person of Ordinary Skill in the Art
`
`25. Based upon my knowledge and experience in this field and my review
`
`of the ’545 patent and the references cited above, I believe that a person of
`
`ordinary skill in the art at the time of the invention (“POSITA” or “person of
`
`skill”) would have had at least a bachelor of science or engineering degree in
`
`electrical engineering, semiconductor technology, physics, or a related field, and
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`either an advanced degree (such as a master’s degree) or an equivalent amount of
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`work experience, i.e., 2-3 years, in an area relating to semiconductor design and/or
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`fabrication, liquid crystal display (“LCD”) design or fabrication, electrical
`
`engineering, or a related technical field. Additional education might substitute for
`
`some of the experience and substantial experience might substitute for some of the
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`educational background. My analysis is thus based on the perspective of a
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`POSITA having at least this level of knowledge and skill in the time leading up to
`
`the ’545 patent. I have been informed that the priority date of the ’545 patent is
`
`November 7, 2008, and I have applied this timeframe in my analysis as being the
`
`relevant time of the ’545 patent.
`
`26. Based on my experiences, I have a good understanding of the
`
`capabilities of a POSITA. Indeed, I have participated in organizations and worked
`
`closely with many such persons over the course of my career. Furthermore, I have
`
`hired a number of times engineers (electrical, mechanical, chemical/chemistry,
`
`13
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`
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`physics, computing, software, etc.) with Bachelors, Masters, and Doctoral degrees.
`
`I have at times during the course of my career, hired engineers on behalf of my
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`employer who have demonstrated specific job experience that would count in place
`
`of post-graduate education. I am well qualified in the semiconductor technologies
`
`related to the ’545 patent, and I was a person of at least ordinary skill in the art in
`
`the ’545 timeframe.
`
`OVERVIEW OF CONCLUSIONS FORMED
`
`A POSITA Would Not Have Been Motivated to Combine Toyota and Akimoto
`to Eliminate the Extraneous Portion of Toyota’s Insulating Film Between the
`Gate Insulating Film and the Lower Layers of the Source and Drain
`Electrodes
`
`27.
`
`This expert Declaration explains the conclusions that I have formed
`
`based on my analysis. Based upon my knowledge and experience and my review
`
`of the IPR petition and the publications listed above, I believe that the proposed
`
`combination of Toyota and Akimoto fails to disclose a semiconductor device
`
`where “the first metal film and the second metal film are in contact with the gate
`
`insulating film” as recited in claims 3 and 13.
`
`28.
`
`Toyota describes a CMOS circuit including an n-channel type thin
`
`film transistor (NTFT) complementarily connected to a p-channel type thin film
`
`transistor (PTFT). Ex. 1004 at [0004], [0054]. Toyota’s FIG. 8B shows a bottom
`
`gate NTFT:
`
`14
`
`
`
`Toyota (Ex. 1004), FIG. 8B
`
`29. Akimoto describes a TFT that includes an oxide semiconductor film
`
`as a channel region. Ex. 1005 at [0014], [0071], [0120]. Akimoto’s FIG. 5C
`
`shows a bottom gate TFT:
`
`Akimoto (Ex. 1005), FIG. 5C
`
`30.
`
`Toyota describes an example of interconnected devices, e.g., a NTFT
`
`interconnected with a capacitance element Cstg. Ex. 1004 at [0070]-[0071]. In
`
`this example, Toyota discloses that a layer of insulating film IN, between the lower
`
`layers of the source/drain electrodes and the gate insulating film GI, is used for
`
`formation of the capacitance element Cstg:
`
`15
`
`
`
`The source electrode ST is formed on the insulating film IN so
`
`as to overlap the electrode CT of the capacitance signal line CL as well
`
`as is formed to extend toward the central side of the pixel region. A
`
`portion of the source electrode ST overlapping the electrode CT is
`
`formed as the capacitance element Cstg using the insulating films
`
`IN and GI as a dielectric film. Further, a portion corresponding to an
`
`end of the extended portion of the source electrode ST serves as a
`
`connection portion to the after-mentioned pixel electrode PX.
`
`Ex. 1004 at [0071] (emphasis added). Toyota’s Fig. 8A (reproduced and annotated
`
`below) shows that a capacitance element Cstg is formed by the overlapping of a
`
`portion of the source electrode ST (green) and the electrode CT (blue):
`
`capacitance element Cstg
`
`alleged “first metal film”
`
`alleged “second
`metal film”
`
`Toyota (Ex. 1004), FIG. 8A (annotated)
`
`16
`
`
`
`Toyota’s Fig. 8B (reproduced and annotated below) shows that layers of insulating
`
`films IN and GI are used as the capacitance element’s dielectric film:
`
`alleged “first metal film”
`
`alleged “second metal
`film”
`
`alleged “extraneous portion”
`
`alleged “gate insulating film”
`
`Toyota (Ex. 1004), FIG. 8B (annotated)
`
`31.
`
`I understand that Petitioner has asserted that a POSITA would have
`
`been motivated to combine Toyota and Akimoto to “eliminate the extraneous
`
`portion of the insulating film IN between the gate insulating film GI and the lower
`
`layers of the source electrode ST(D) and drain electrode DT(D), such that the film
`
`and these layers would now be in contact with one another.” Pet. at 51 (emphasis
`
`added). A POSITA reviewing the above disclosure of Toyota regarding the use of
`
`the layer of the insulating film IN between the source electrode and the gate
`
`insulating film GI as part of the dielectric film of the capacitance element Cstg
`
`would not have been led to Petitioner’s proposed modification. The layer of
`
`17
`
`
`
`insulating film IN is necessary to form the capacitance element Cstg, and thus its
`
`removal would compromise the Cstg structure used in Toyota’s device. The
`
`presence of the layer of insulating film IN between the source electrode and the
`
`gate insulating film GI would prevent at least the source electrode ST (alleged to
`
`correspond to the recited first metal film) from being “in contact with the gate
`
`insulating film.” This is a requirement of claims 3 and 13.
`
`32.
`
`For these reasons, the combination of Toyota and Akimoto does not
`
`teach a semiconductor device where “the first metal film and the second metal film
`
`are in contact with the gate insulating film” and a person of skill would have
`
`readily recognized this fact upon reviewing Toyota and Akimoto. Based upon my
`
`knowledge and experience in this field and my review of Toyota in view of
`
`Akimoto, this proposed combination of references would not provide this
`
`requirement of claims 3 and 13.
`
`LEGAL PRINCIPLES
`
`Anticipation
`
`33.
`
`I have been informed that a patent claim is invalid as anticipated
`
`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
`
`is found either explicitly or inherently in a single prior art reference. Under the
`
`principles of inherency, if the prior art necessarily functions in accordance with, or
`
`includes the claimed limitations, it anticipates.
`
`18
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`
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`34.
`
`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
`
`if the claimed invention was known or used by others in the U.S., or was patented
`
`or published anywhere, before the applicant’s invention. I further have been
`
`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
`
`patented or published anywhere, or was in public use, on sale, or offered for sale in
`
`this country, more than one year prior to the filing date of the patent application
`
`(critical date). And a claim is invalid, as I have been informed, under 35 U.S.C. §
`
`102(e), if an invention described by that claim was described in a U.S. patent
`
`granted on an application for a patent by another that was filed in the U.S. before
`
`the date of invention for such a claim.
`
`Obviousness
`
`35.
`
`I have been informed that a patent claim is invalid as “obvious” under
`
`35 U.S.C. § 103 in light of one or more prior art references if it would have been
`
`obvious to a POSITA, taking into account (1) the scope and content of the prior art,
`
`(2) the differences between the prior art and the claims, (3) the level of ordinary
`
`skill in the art, and (4) any so called “secondary considerations” of non-
`
`obviousness, which include: (i) “long felt need” for the claimed invention, (ii)
`
`commercial success attributable to the claimed invention, (iii) unexpected results
`
`of the claimed invention, and (iv) “copying” of the claimed invention by others.
`
`For purposes of my analysis above and because I know of no indication from the
`
`19
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`
`
`patent owner or others to the contrary, I have applied a date of November 7, 2008,
`
`as the date of invention in my obviousness analyses, although in many cases the
`
`same analysis would hold true even at an earlier time than November 7, 2008.
`
`36.
`
`I have been informed that a claim can be obvious in light of a single
`
`prior art reference or multiple prior art references. To be obvious in light of a
`
`single prior art reference or multiple prior art references, there must be a reason to
`
`modify the single prior art reference, or combine two or more references, in order
`
`to achieve the claimed invention. This reason may come from a teaching,
`
`suggestion, or motivation to combine, or may come from the reference or
`
`references themselves, the knowledge or “common sense” of one skilled in the art,
`
`or from the nature of the problem to be solved, and may be explicit or implicit
`
`from the prior art as a whole. I have been informed that the combination of
`
`familiar elements according to known methods is likely to be obvious when it does
`
`no more than yield predictable results. I also understand it is improper to rely on
`
`hindsight in making the obviousness determination.
`
`ADDITIONAL REMARKS
`
`37.
`
`I currently hold the opinions set expressed in this declaration. But my
`
`analysis may continue, and I may acquire additional information and/or attain
`
`supplemental insights that may result in added observations.
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`20
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`38.
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`I hereby declare that all statements made of my own knowledge are
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`true and that all statements made on information and belief are believed to be true.
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`I further declare that these statements were made with the knowledge that willful
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`false statements and the like so made are punishable by fine or imprisonment, or
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`both, under Section 1001 of the Title 18 of the United States Code and that such
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`willful false statements may jeopardize the validity of the application or any
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`patents issued thereon.
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`Dated:
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`By:
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`Michael Lebby, Ph.D.
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`21
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`Thursday, November 29, 2018
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