`Petitioner Bluehouse Global Ltd.
`
`Ex. 1004
`Ex. 1004
`
`
`
`(i9) United States
`(12) Patent Application Publication
`Toyota et al.
`
`US 20080299693A1
`
`(io) Pub. No.: US 2008/0299693 Al
`(43) Pub. Date: Dec. 4, 2008
`
`(54) MANUFACTURING METHOD FOR DISPLAY
`DEVICE
`
`(75) Inventors:
`
`Yoshiaki Toyota, Hachioji (JP);
`Takeshi Sato, Kokubunji (JP)
`
`Correspondence Address:
`Stanley P. Fisher
`Reed Smith Hazel & Thomas LLP
`Suite 1400, 3110 Fairview Park Drive
`Falls Church, VA 22042-4503 (US)
`
`(73) Assignee:
`
`Hitachi Displays, Ltd.
`
`(21) Appl.No.:
`
`12/155,204
`
`(22) Filed:
`
`May 30, 2008
`
`(30) Foreign Application Priority Data
`
`May 31, 2007 (JP) 2007-144957
`
`Publication Classification
`
`(51) Int. CI.
`H01L 33/00 (2006.01)
`(52) U.S. CI 438/34; 257/E33.053
`ABSTRACT
`(57)
`
`A manufacturing method for a display device having a first
`conductive type thin film transistor and a second conductive
`type thin film transistor, comprising the steps of: in formation
`regions for a first conductive type thin film transistor and a
`second conductive type thin film transistor forming a semi-
`conductor layer, a first insulating film covering the semicon-
`ductor layer and a gate electrode disposed on the first insu-
`lating film so as to intersect the semiconductor layer, on
`substrate having first conductive type impurity regions on
`both outer sides of a channel region of the semiconductor
`layer below the gate electrode forming a second insulating
`film, in the second insulating film and the first insulating film
`forming a contact hole for a drain electrode and a source
`electrode, in the formation region for the second conductive
`type thin film transistor forming electrodes and a second
`conductive type impurity region.
`
`PAS
`
`SUB1 GT
`
`SUB1
`
`SUB1
`
`BLUEHOUSE EXHIBIT 1004
`Page 2 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 1 of 11 US 2008/0299693 Al
`
`CM
`
`FIG.1B
`PAS
`
`DT(U)
`DT(D)
`
`PTFT
`
`PAS
`
`FIG.1C
`
`JT(U)
`JT(D)
`
`JT(U) DT(U)
`
`JT(D) DT(D
`IN
`
`SD
`
`SUB1
`
`<NTFT>
`
`CH PS
`SUB1
`
`<PTFT>
`
`BLUEHOUSE EXHIBIT 1004
`Page 3 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 2 of 11 US 2008/0299693 Al
`
`FIG2
`
`SUB1
`
`BLUEHOUSE EXHIBIT 1004
`Page 4 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 3 of 11 US 2008/0299693 Al
`
`FIG.3A
`DT PS
`
`GT-
`
`DL-
`
`GL
`Cstg
`
`CT
`ST
`
`CL
`
`TH
`
`PX
`
`FIG.3C
`PX PAS
`
`SUB1
`
`<NTFT>
`
`SUB1
`
`<PX>
`
`BLUEHOUSE EXHIBIT 1004
`Page 5 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 4 of 11 US 2008/0299693 Al
`
`<NTFT>
`
`<PTFT>
`
`<PX>
`
`GI ps
`
`GI 1
`
`PS
`
`GI
`
`FIG.4A
`
`SUB1 FL SUB1 FL SUB1 FL
`
`FRG
`
`GT FRG GT
`
`GI
`
`FIG.4B
`
`y\.
`
`AO X
`
`GI
`
`AO
`
`SUB1 FL SUB1 FL SUB1 FL
`
`GT AO
`GI ^VAO GI \ GT
`|\| /| I (n + )
`
`?(n+\)rrMy(n,+) (ntl)
`
`GI
`
`FIG.4C
`
`FIG.4D
`
`SUB1 FL SUB1 FL SUB1 FL
`
`GI
`
`SUB1 FL SUB1
`
`SUB1 FL
`
`BLUEHOUSE EXHIBIT 1004
`Page 6 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 5 of 11 US 2008/0299693 Al
`
`<NTFT>
`
`GI GT IN
`
`<PTFT>
`GI GT IN
`
`<PX>
`
`GI IN
`
`FIG.5A
`
`SUB1 FL SUB1 FL SUB1 FL
`
`GI
`FIG.5B ^
`(n + )
`
`FIG.5C
`
`CNL2
`CNL1 \ GT
`
`CNL2 nT CNL2 „ TN
`CNLK N T CNL1\ ) GI IN
`
`SUB1
`
`SUB1
`
`BLUEHOUSE EXHIBIT 1004
`Page 7 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 6 of 11 US 2008/0299693 Al
`
`FIG.6A
`
`FRG
`
`<NTFT>
`
`<PTFT>
`
`FRG
`
`FRG
`
`FIG.6B
`
`SUB1
`
`<PX>
`FRG
`
`CNL2
`CNL1
`
`"" ""'rrrrrwrrfn
`
`FRG CNL2
`' CNL1
`PAS
`
`1
`
`CH
`
`(n + ) CH (n + )
`
`IN FL
`
`FIG.6C C^L1 ?T CNL2 /NL2 /GT
`
`r-^ r-v V r-i r^ CNL1 /
`
`CNL2
`
`CNL1
`
`FIG.6D
`
`SUB1
`
`(p + )
`
`GI IN
`
`BLUEHOUSE EXHIBIT 1004
`Page 8 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 7 of 11 US 2008/0299693 Al
`
`<NTFT>
`
`<PTFT>
`
`FRG _K|1 i FRG
`CNL2NCNU GT
`
`FRG
`
`^m
`
`~-r FRG
`
`T ^
`
`<PX>
`
`FRG
`
`FIG.7A
`
`SUB1
`
`CNL2 CNL1
`
`^
`PS
`
`GI IN
`
`CNL2 CNL1 iN
`
`FIG.7B
`
`SUB1
`
`FIG.7C
`
`FIG.7D
`
`(p + )
`
`CNL2
`
`CNL1 IN
`
`PX
`
`PAS
`
`a/
`
`BLUEHOUSE EXHIBIT 1004
`Page 9 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 8 of 11 US 2008/0299693 Al
`
`FIG.8A
`
`GL
`
`DL GT
`
`FIG.8C
`
`DT(U)
`DT(D)
`
`SUB1
`
`<NTFT>
`
`BLUEHOUSE EXHIBIT 1004
`Page 10 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 9 of 11 US 2008/0299693 Al
`
`FIG.9A
`GT
`
`CM PS
`
`TH
`
`DT
`
`CM
`
`••••1-8
`b
`
`TH
`
`NTFT
`
`TH
`
`JT
`
`-TH
`
`m*
`
`m J c
`
`ST
`
`CNL
`
`PTFT
`
`TH
`
`FIG.9C
`CNL(U)
`IN PAS
`CNL(D)
`
`PAS
`
`JT(D) DT(D)
`
`/ DDrT CH PS FL
`SUB1 GT hl-
`
`<NTFT>
`
`<PTFT>
`
`BLUEHOUSE EXHIBIT 1004
`Page 11 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 10 of 11 US 2008/0299693 Al
`
`<NTFT> <PTFT>
`
`<PX>
`
`FIG.10A
`
`f
`
`SUB1
`
`z
`
`+
`
`FL SUB1
`
`GI FL
`^ f-
`$
`-/-
`FL SUB1
`
`IN
`TH'^ JH
`(n + ).TH ( (n + )Ti_| , .w'H ( ,m
`
`IN GI
`
`FIG.10B
`
`f
`
`SUB1 GT
`
`GT
`
`•^
`
`SUB1
`
`CNL1 'N CNL2
`CNL1 CNL2
`, / '(' ( (""^ CNL1 CNL2
`
`FIG.10C
`
`2^
`
`X
`
`-f-
`GT FL SUB1
`
`+
`
`G1 SUB1
`
`CNL2
`
`IN
`FRG ^ CNL2 FRG FRG FRG
`
`CNL2
`
`FRG
`
`FRG
`
`t FL
`+ CNL2
`
`CNL1
`
`»>/»,ii»>//»i>j>ii,r>»jj*i,i/>ijjnr7i7*
`
`(n + ) GT (n + )
`
`FIG.10D
`
`FIG.10E
`
`CNL1
`
`CNL1 CNL2
`IN TH >> ZT -TH CNL2 CNL1
`
`4- X
`
`V/JWJ&JW/SSWJTMA
`
`IN
`^
`
`^m
`
`SUB1 GT GI (n + ) FL (n + ) SUB1 GI
`
`BLUEHOUSE EXHIBIT 1004
`Page 12 of 24
`
`
`
`Patent Application Publication Dec. 4, 2008 Sheet 11 of 11 US 2008/0299693 Al
`
`<NTFT>
`
`<PTFT>
`
`<PX>
`
`CNL1
`
`CNL2
`
`CNL1 CNL2
`
`CNL2
`
`CNL1
`
`7ZZZZZZZZ2Z2ZZZZZ, rJ&JA
`
`SUB1 GT GI (p + ) IN GT (p+) SUB1 IN
`
`+-
`
`FIG.11A
`
`CNL1 CNL2 CNL2 CNL1
`
`FIG.11B
`
`/Z
`
`-^
`(n_) (p-) (n-) SUB1 (p-) IN (P-)
`
`FIG.11C
`
`CNL2 ^1 CNL1
`
`zzzzzzzzzzzzzzzzz
`
`PAS
`
`PX
`
`I
`
`•iiiiiiiuinhi
`HlllllllllllllllllllA
`
`SUB1 GT
`
`SUB1
`
`ST SUB1
`
`BLUEHOUSE EXHIBIT 1004
`Page 13 of 24
`
`
`
`US 2008/0299693 Al
`
`Dec. 4, 2008
`
`MANUFACTURING METHOD FOR DISPLAY
`DEVICE
`
`INCORPORATION BY REFERENCE
`
`[0001] The present application claims priority from Japa-
`nese application JP2007-144957 filed on May 31, 2007, the
`content of which is hereby incorporated by reference into this
`application.
`
`BACKGROUND OF THE INVENTION
`
`[0002] The present invention relates to a manufacturing
`method for a display device. More particularly, the present
`invention relates to a manufacturing method for a display
`device including a substrate having formed thereon an
`n-channel type thin film transistor and a p-channel type thin
`film transistor.
`[0003] A so-called active matrix type display device has a
`structure in which a plurality of matrix-arranged pixels are
`provided on its display so as to sequentially select each pixel
`column by turning on a thin film transistor provided in each
`pixel of the pixel column by scanning signals supplied via a
`gate signal line and so as to supply video signals to each of the
`pixel electrodes PX via the drain signal line DL connected in
`common to the pixels of another pixel column corresponding
`to the respective pixels of the pixel column in conformity with
`this selection timing.
`[0004] Further, on a substrate having formed thereon the
`display, a circuit (scanning signal drive circuit) that supplies
`scanning signals to each of the gate signal lines and a circuit
`(video signal drive circuit) that supplies video signals to each
`of the drain signal lines are formed in the vicinity of the
`display. Any of these circuits are constituted of a plurality of
`CMOS circuits. The CMOS circuit is a circuit formed by
`complementarily connecting an n-channel type transistor and
`a p-channel type transistor to each other.
`[0005] In this case, there is known a circuit having a struc-
`ture in which each transistor of each of the circuits formed in
`the vicinity of the display is formed by a pair of thin film
`transistors and is formed along with the formation of each of
`the pixels.
`[0006] The display device having such a structure is dis-
`closed, for example, in Japanese Unexamined Patent Appli-
`cation Publication No. 2006-186397.
`
`SUMMARY OF THE INVENTION
`
`[0007] However, when forming the CMOS transistor in a
`display device having the above-described structure, it is
`necessary to dope n-type impurities in a semiconductor layer
`of one thin film transistor to form source and drain regions
`and to dope p-type impurities in a semiconductor layer of the
`other thin film transistor to form source and drain regions.
`[0008] In this case, there is adopted a method of forming
`source and drain regions in the semiconductor layer of one
`thin film transistor, then covering the one thin film transistor
`with a mask made of a photoresist film and doping impurities
`in the semiconductor layer of the other thin film transistor.
`[0009] Therefore, it is inescapable that a photolithographic
`process for forming the mask is required and the number of
`man-hours for manufacture increases.
`[0010] Accordingly, it is an object of the present invention
`to provide a manufacturing method for a display device in
`which the photolithographic process is reduced.
`
`[0011] A summary of representative aspects of the inven-
`tion disclosed in the present application will be described in
`brief as follows:
`[0012] (1) A manufacturing method for a display device
`according to the present invention, for example, including
`a substrate having formed thereon a first conductive type
`thin film transistor and a second conductive type thin film
`transistor, the method comprising the steps of:
`[0013] preparing a substrate having respective formation
`regions for a first conductive type thin film transistor and a
`second conductive type thin film transistor, in which a semi-
`conductor layer, a first insulating film covering the semicon-
`ductor layer, and a gate electrode disposed on the first insu-
`lating film so as to intersect the semiconductor layer are
`formed and first conductive type impurity regions are formed
`on both outer sides of a channel region of the semiconductor
`layer below the gate electrode;
`[0014] forming a second insulating film on the substrate so
`as to also cover the gate electrode, and forming in the second
`insulating film and the first insulating film a contact hole used
`for connection between a drain electrode and a source elec-
`trode, the contact hole being formed so as not to expose the
`gate electrode in the formation region for the first conductive
`type thin film transistor and so as to partially expose each side
`of the gate electrode intersecting the semiconductor layer in
`the formation region for the second conductive type thin film
`transistor;
`[0015] forming the drain electrode and the source electrode
`using a multilayer conductive layer including an upper con-
`ductive layer and a lower conductive layer an outline of which
`protrudes outward from that of the upper conductive layer, the
`drain electrode and the source electrode being formed so as to
`cover each of the contact holes in the formation region for the
`first conductive type thin film transistor and so as to cover a
`portion of each of the contact holes facing the gate electrode
`in the formation region for the second conductive type thin
`film transistor; and
`[0016] forming by doping second conductive type impuri-
`ties a second conductive type impurity region in the semicon-
`ductor layer having a portion having formed thereon none of
`the electrodes and having a portion having formed thereon
`only the lower conductive layer in each of the contact holes in
`the formation region for the second conductive type thin film
`transistor.
`[0017] (2) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (1), characterized in that the
`semiconductor layer is made of poly silicon.
`[0018] (3) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (1), characterized in that the
`first conductive type impurity regions formed on both outer
`sides of a channel region of the semiconductor layer below
`the gate electrode include low concentration first conduc-
`tive type impurity regions formed on both outer sides of the
`channel region and high concentration first conductive type
`impurity regions formed on an outer side of the respective
`low concentration first conductive type impurity regions.
`[0019] (4) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premi se of the constitution (1), characterized in that each of
`the drain electrode and the source electrode is formed by
`etching using as a mask a photoresist film formed on a
`surface of a layered product including the lower conductive
`
`BLUEHOUSE EXHIBIT 1004
`Page 14 of 24
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`
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`US 2008/0299693 Al
`
`Dec. 4, 2008
`
`layer and the upper conductive layer, and the upper con-
`ductive layer is etched larger than the lower conductive
`layer by side etching with respect to the mask.
`[0020] (5) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (1), characterized in that the
`gate electrode and the lower conductive layer are made of
`the same material.
`[0021] (6) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (5), characterized in that the
`gate electrode and the lower conductive layer are made of
`tungsten or a tungsten alloy.
`[0022] (7) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (1), characterized in that a
`plurality of pixels are formed on the substrate, and each of
`the pixels has a thin film transistor turned-on by scanning
`signals from a gate signal line and a pixel electrode to
`which video signals from a drain signal line are supplied
`via the turned-on thin film transistor, the thin film transistor
`being one thin film transistor of the first conductive type
`thin film transistor and the second conductive type thin film
`transistor.
`[0023] (8) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (7), characterized in that a
`scanning signal drive circuit that supplies scanning signals
`to each of the gate signal lines and a video signal drive
`circuit that supplies video signals to each of the drain signal
`lines are formed on the substrate; and
`[0024] the scanning signal drive circuit and the video signal
`drive circuit have the first conductive type thin film transistor
`and the second conductive type thin film transistor.
`[0025] (9) A manufacturing method for a display device
`according to the present invention, for example, including
`a substrate having formed thereon a first conductive type
`thin film transistor and a second conductive type thin film
`transistor, the method comprising the steps of:
`[0026] preparing a substrate having respective formation
`regions for a first conductive type thin film transistor and a
`second conductive type thin film transistor, in which a gate
`electrode, a first insulating film covering the gate electrode,
`and a semiconductor layer disposed on the first insulating film
`so as to intersect the gate electrode are formed;
`[0027] forming a second insulating film on the substrate so
`as to also cover the semiconductor layer, and forming in the
`second insulating film a contact hole used for connection
`between a drain electrode and a source electrode;
`[0028] forming a first conductive type impurity region in
`the semiconductor layer by doping a first conductive type
`impurity using the second insulating film as a mask;
`[0029] forming a multilayer conductive layer including an
`upper conductive layer and a lower conductive layer an out-
`line of which protrudes outward from that of the upper con-
`ductive layer, on the second insulating film above the gate
`electrode in the formation region for the second conductive
`type thin film transistor, and forming the drain electrode and
`the source electrode using the multilayer conductive layer so
`as to cover each of the contact holes in the formation region
`for the first conductive type thin film transistor and so as to
`cover a portion of each of the contact holes facing the gate
`electrode in the formation region for the second conductive
`type thin film transistor;
`
`[0030] forming by doping a second conductive type impu-
`rity of high concentration a second conductive type impurity
`region in the semiconductor layer having a portion having
`formed thereon none of the electrodes and having a portion
`having formed thereon only the lower conductive layer in
`each of the contact holes in the formation region for the
`second conductive type thin film transistor; and
`[0031] forming in the semiconductor layer a channel region
`with second conductive type impurities by doping second
`conductive type impurities of low concentration through the
`drain electrode and the source electrode of the first conductive
`type thin film transistor.
`[0032] (10) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (9), characterized in that the
`multilayer conductive layer formed on the second insulat-
`ing film above the gate electrode in the formation region for
`the second conductive type thin film transistor is formed
`such that a side portion of the lower conducive layer inter-
`secting the semiconductor layer is formed on an inner side
`of a corresponding sidewall surface of the second insulat-
`ing film; and
`[0033] the second conductive type impurity of low concen-
`tration is doped to form respective second conductive type
`regions on both outer sides of the channel region of the
`semiconductor layer.
`[0034] (11) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (9), characterized in that a
`plurality of pixels are formed on the substrate, and each of
`the pixels has a thin film transistor turned-on by scanning
`signals from a gate signal line and a pixel electrode to
`which video signals from a drain signal line are supplied
`via the turned-on thin film transistor, the thin film transistor
`being one thin film transistor of the first conductive type
`thin film transistor and the second conductive type thin film
`transistor.
`[0035] (12) The manufacturing method for a display device
`according to the present invention is, for example, on the
`premise of the constitution (11), characterized in that a
`scanning signal drive circuit that supplies scanning signals
`to each of the gate signal lines and a video signal drive
`circuit that supplies video signals to each of the drain signal
`lines are formed on the substrate; and
`[0036] the scanning signal drive circuit and the video signal
`drive circuit have the first conductive type thin film transistor
`and the second conductive type thin film transistor.
`[0037] Here, the present invention is not limited to the
`above-mentioned constitutions, and various modifications
`are conceivable without departing from the technical concept
`of the invention.
`[0038] According to the manufacturing method for the thus
`constituted display device, the photolithographic process can
`be reduced.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0039] FIGS. 1A to 1C are block diagrams showing one
`embodiment of a CMOS transistor formed in a display device
`to which a manufacturing method for a display device accord-
`ing to the present invention is applied;
`[0040] FIG. 2 is an equivalent circuit diagram showing the
`entire display device to which the manufacturing method for
`a display device according to the present invention is applied;
`
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`Dec. 4, 2008
`
`[0041] FIGS. 3A to 3C are block diagrams showing one
`embodiment of pixels of the display device to which the
`manufacturing method for a display device according to the
`present invention is applied;
`[0042] FIGS. 4A to 4D are step views showing one embodi-
`ment of the manufacturing method for a display device
`according to the present invention, and FIGS. 5A to 5C and
`6A to 6D are views showing the whole steps;
`[0043] FIGS. 5A to 5C are step views showing one embodi-
`ment of the manufacturing method for a display device
`according to the present invention, and FIGS. 4A to 4D and
`6A to 6D are views showing the whole steps;
`[0044] FIGS. 6A to 6D are step views showing one embodi-
`ment of the manufacturing method for a display device
`according to the present invention, and FIGS. 4A to 4D and
`5A to 5C are views showing the whole steps;
`[0045] FIGS. 7A to 7D are step views showing another
`embodiment of a manufacturing method for a display device
`according to the present invention;
`[0046] FIGS. 8A to 8C are block diagrams showing another
`embodiment of pixels of a display device to which a manu-
`facturing method for a display device according to the present
`invention is applied;
`[0047] FIGS. 9A to 9C are block diagrams showing another
`embodiment of a CMOS transistor formed in the display
`device to which the manufacturing method for a display
`device according to the present invention is applied;
`[0048] FIGS. 10A to 10E are step views showing another
`embodiment of the manufacturing method for a display
`device according to the present invention;
`[0049] FIGS. HA to 11C are step views showing another
`embodiment of the manufacturing method for a display
`device according to the present invention; and FIGS. 10A to
`10E and FIGS. HA to HE are views showing the whole
`steps.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`[0050] Preferred embodiments of a display device accord-
`ing to the present invention will be described below with
`reference to the figures.
`
`First Embodiment
`
`<Entire Equivalent Circuit>
`[0051] FIG. 2 is an equivalent circuit diagram showing, as
`a liquid crystal display device, one embodiment of the display
`device according to the present invention.
`[0052] In FIG. 2, a substrate SUB1 made of, for example,
`glass is shown. This substrate SUB1 is constituted as one
`substrate SUB1 of a pair of substrates disposed opposite each
`other through a liquid crystal interposed therebetween.
`[0053] Further, gate signal lines GL which extend in the x
`direction and are juxtaposed in the y direction and drain signal
`lines DL which extend in the y direction and are juxtaposed in
`the x direction in FIG. 2 are formed on a liquid-crystal-side
`surface of the substrate SUB1.
`[0054] Each of the gate signal lines GL is formed so that, for
`example, its one end is connected to a scanning signal drive
`circuit V and hence, scanning signals are sequentially sup-
`plied to the line GL by the scanning signal drive circuit V. This
`scanning signal drive circuit V is constituted of a large num-
`ber of CMOS thin film transistors CM in which an n-channel
`type MOS transistor and a p-channel type MOS transistor are
`complementarily connected to each other.
`
`[0055] Each of the drain signal lines DL is formed so that,
`for example, its upper end is connected to a video signal drive
`circuit H and hence, video signals are supplied to the line DL
`by the video signal drive circuit H. This video signal drive
`circuit H is constituted of a large number of CMOS thin film
`transistors CM in which an n-channel type MOS transistor
`and a p-channel type MOS transistor are complementarily
`connected to each other.
`[0056] A rectangular area (e.g., indicated by a dotted frame
`in the figure) surrounded by adjacent ones of the gate signal
`lines and adjacent ones of the drain signal lines is formed as
`an area in which a pixel PIX is formed. The pixel PIX has a
`thin film transistor TFT turned on by scanning signals from
`the gate signal line GL, a pixel electrode PX to which video
`signals from the drain signal line DL are supplied via the
`turned-on thin film transistor TFT, and a capacitance element
`Cstg formed between the pixel electrode PX and a capaci-
`tance signal line CL disposed in parallel with, for example,
`the gate signal line GL.
`[0057] Additionally, the pixel electrode PX is arranged so
`as to generate an electric field with a counter electrode (not
`shown) formed on a liquid-crystal-side surface of the sub-
`strate SUB1 or on a liquid-crystal-side surface of another
`substrate SUB2 different from the substrate SUB1 and so as
`to cause molecules in a liquid crystal LC of the pixel to behave
`by this electric field.
`[0058] The liquid crystal display device having such a
`structure is driven so as to sequentially select each pixel
`column by turning on the thin film transistor TFT formed in
`each of the pixels by scanning signals supplied via the com-
`mon gate signal line GL, and so as to supply video signals to
`each of the pixel electrodes PX via the drain signal line DL
`connected in common to the pixels of another pixel column
`corresponding to the respective pixels of the pixel column in
`conformity with this selection timing.
`
`Construction of Pixel>
`[0059] FIG. 3 A is a plan view showing one embodiment of
`a construction of the pixel, and shows a portion equivalent to
`an area surrounded by a dotted frame of FIG. 2.
`[0060] Further, FIG. 3B shows a cross-sectional view taken
`along line b-b of FIG. 3A, and FIG. 3C shows a cross-sec-
`tional view taken along line c-c of FIG. 3 A.
`[0061] Additionally, this pixel includes a so-called top gate
`type thin film transistor in which a gate electrode is formed on
`the upper layer of a semiconductor layer.
`[0062] An undercoat layer FL made of, for example, a
`silicon dioxide film is formed on a liquid-crystal-side surface
`of the substrate SUB1. The undercoat layer FL serves as a
`layer for preventing impurities within the substrate SUB1
`from penetrating an after-mentioned semiconductor layer PS.
`The capacitance signal line CL is formed on a surface of the
`undercoat layer FL, and formed in a pattern partially having
`an extended portion whose one side has a relatively wide area.
`The extended portion is formed as one electrode CT of the
`after-mentioned capacitance element Cstg.
`[0063] Further, the semiconductor layer PS made of a poly-
`silicon film is formed close to an electrode CT of the capaci-
`tance signal line CL.
`[0064] This semiconductor layer PS is formed as a semi-
`conductor layer of, for example, an after-mentioned n-chan-
`nel type thin film transistor NTFT. In the semiconductor layer
`PS, low concentration n-type impurity regions are respec-
`tively formed on both outer sides of a channel region CH
`
`BLUEHOUSE EXHIBIT 1004
`Page 16 of 24
`
`
`
`US 2008/0299693 Al
`
`Dec. 4, 2008
`
`positioned roughly in its center, and high-concentration
`n-type impurity regions are respectively formed on an outer
`side of the low concentration n-type impurity regions. Each of
`the low concentration n-type impurity regions functions as an
`LDD region, and each of the high concentration n-type impu-
`rity regions functions as a drain region DD and a source
`region SD.
`[0065] A source region and a drain region of the thin film
`transistor TFT changes in a state where a bias voltage is
`applied. In this specification, for convenience sake, a part
`connected to the after-mentioned drain signal line DL is des-
`ignated as the drain region DD, and a part connected to the
`pixel electrode PX is designated as the source region SD.
`[0066] On a surface of the substrate SUB1 on which the
`capacitance signal line CL and the semiconductor layer PS
`are thus formed, an insulating film (first insulating film) GI
`made of, for example, a silicon dioxide film is formed to also
`cover these capacitance signal line CL and semiconductor
`layer PS. This insulating film GI functions as a gate insulating
`film of the n-channel type thin film transistor NTFT.
`[0067] Further, the gate signal line GL made of, for
`example, aluminum is formed on a surface of the insulating
`film GI. This gate signal line GL has an extended portion
`overlapping the channel region CH of the semiconductor
`layer PS and this extended portion functions as the gate elec-
`trode GT of the thin film transistor TFT.
`[0068] On a surface of the substrate SUB1 on which the
`gate signal line GL is thus formed, an insulating film (second
`insulating film) IN made of, for example, silicon dioxide film
`is formed.
`[0069] Further, the drain signal line DL is formed on the
`surface of the insulating film IN, and partially has an extended
`portion. The extended portion is formed as a drain electrode
`DT of the thin film transistor TFT. This drain electrode DT is
`connected to a drain region DD of the semiconductor layer PS
`via a contact hole TH formed through the insulating films IN
`and GI.
`[0070] Further, a source electrode ST of the n-channel type
`thin film transistor NTFT is formed during the formation of
`the drain signal line DL. The source electrode ST is connected
`to a source region SD of the semiconductor layer PS via the
`contact hole TH formed through the insulating films IN and
`GI.
`[0071] The source electrode ST is formed on the insulating
`film IN so as to overlap the electrode CT of the capacitance
`signal line CL as well as is formed to extend toward the
`central side of the pixel region. A portion of the source elec-
`trode ST overlapping the electrode CT is formed as the
`capacitance element Cstg using the insulating films IN and GI
`as a dielectric film. Further, a portion corresponding to an end
`of the extended portion of the source electrode ST serves as a
`connection portion to the after-mentioned pixel electrode PX.
`[0072] Here, each of the drain signal line DL, the drain
`electrode DT and the source electrode ST has the two-layered
`structure in which, for example, a conductive layer made of
`tungsten having a thickness of about 30 nm and a conductive
`layer made of aluminum having a thickness of about 500 nm
`are sequentially stacked. Further, this two-layered structure
`has a structure in which a lower conductive layer protrudes
`outward from an upper conductive layer at the periphery.
`[0073] Therefore, the drain electrode DT includes a lower
`drain electrode DT(D) and an upper drain electrode DT(U),
`and the lower drain electrode DT(D) is formed to protrude
`outward from the upper drain electrode DT(U).
`
`[0074] In the same manner, the source electrode ST
`includes a lower source electrode ST(D) and an upper source
`electrode ST(U), and the lower source electrode ST(D) is
`formed to protrude outward from the upper source electrode
`ST(U).
`[0075] Additionally, also in the extended end of the source
`electrode ST serving as the connection portion to the pixel
`electrode PX, the lower source electrode ST(D) is formed to
`protrude outward from the upper source electrode ST(U) as
`shown in FIG. 3C.
`[0076] On the surface of the substrate SUB1 on which the
`drain signal line DL, the drain electrode DT, and the source
`electrode ST are thus formed, a protective coat PAS made of,
`for example, resin is formed. Further, on a surface of the
`protective coat PAS, the pixel electrode PX made of, for
`example, an ITO film is formed. This pixel electrode PX is
`connected to the source electrode ST via the contact hole TH
`formed in the protective coat PAS.
`
`<CMOS Thin Film Transistor>
`
`[0077] FIG. 1A is a plan view showing one of the CMOS
`thin film transistors CM formed by being incorporated into
`the scanning signal drive circuit V or the video signal drive
`circuit H. FIG. IB shows a cross-sectional view taken along
`line b-b of FIG. 1A, and FIG. 1C shows a cross-sectional view
`taken along line c-c of FIG. 1A.
`[0078] Additionally, this CMOS thin film transistor CM is
`formed along with the formation of the pixel PIX.
`[0079] In the FIG. 1A, the CMOS thin film transistor CM
`has a structure in which the n-channel type thin film transistor
`NTFT and a p-channel type thin film transistor PTFT are
`arranged in parallel with each other, and the gate electrodes of
`both the transistors are formed in common.
`[0080] Further, respective electrodes at the right sides in the
`figures of the n-channel type thin film transistor NTFT and the
`p-channel type thin film transisto