Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1003
`
`EX. 1003
`
`
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1003
`
`EX. 1003
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE IPR: 2018-01377
`
`U.S. PATENT NO.9,281,405 B2
`
`_____________________________
`
`
`DECLARATION OF RICHARD A. FLASCK
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
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`BLUEHOUSE EXHIBIT 1003
`Page 2 of 79
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`I, Richard A. Flasck, declare as follows:
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`
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`I.
`
`INTRODUCTION
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`1.
`
`I am over the age of twenty-one (21) and am competent to make this
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`Declaration.
`
`2.
`
`I am an independent consultant in liquid crystal display (“LCD”)
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`technology, including manufacturing processes and product design.
`
`A. Engagement
`
`3.
`
`I have been retained by counsel for BlueHouse Global Ltd. in the
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`above-captioned Inter Partes Review (“IPR”) matter as an independent technical
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`expert.
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`4.
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`As part of this engagement, I have been retained to review and
`
`evaluate whether certain patents and publications disclose to a person of ordinary
`
`skill in the art (“POSA”) the subject matter of specific claims of United States
`
`Patent No. 9,281,405 B2 (“the ‘405 Patent”) as of the time of the filing date of the
`
`application from which the ‘405 Patent issued. I expect to testify regarding the
`
`matters set forth in this declaration if asked to do so.
`
`5.
`
`I am being compensated on an hourly basis for my work performed in
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`connection with this case. I have received no additional compensation for my work
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`
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`in this case, and my compensation does not depend upon the contents of this
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`report, any testimony I may provide, or the ultimate outcome of the case.
`
`B.
`
`6.
`
`Background and Qualifications
`
`I earned my Bachelor of Science degree in Physics from the
`
`University of Michigan in 1970. I subsequently earned my M.S. in Physics at
`
`Oakland University in 1976.
`
`7.
`
`I have nearly fifty (50) years of experience in hi tech product
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`development, including all aspects of LCD systems and technologies, through
`
`positions ranging from research and development to manufacturing at multiple
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`large and small technology companies. I have led engineering teams to develop
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`Liquid Crystal on Silicon (LCOS) microdisplay technology. I played a significant
`
`part in the early development of amorphous silicon thin film transistor (TFT)
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`active matrix Liquid Crystal Displays (AMLCD), including designing the world’s
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`first amorphous silicon TFT LCD pilot line in 1986. I have experience in TFT
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`process and circuit design, data driver and gate driver design, scalers, video
`
`circuits, backlighting, and inverter design. I also have a solid functional
`
`background in all display technologies, their applications and associated process
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`and manufacturing technologies.
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`8.
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`I am an inventor or co-inventor of 26 patents, including patents on
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`various aspects of LCD technology, including TFT structure and fabrication. A list
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`
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`3
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`of my patents is included in my curriculum vitae, a copy of which is attached
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`hereto as Appendix B.
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`9.
`
`A detailed description of my professional qualifications, including a
`
`listing of my specialties/expertise and professional activities, is contained in my
`
`curriculum vitae, a copy of which is attached hereto as Appendix B.
`
`C. Basis of My Opinions and Materials Considered
`
`10.
`
`In forming my opinions, I have relied upon my education, knowledge
`
`and experience with LCDs and related technologies, including manufacturing
`
`processes. I have also relied upon my education, knowledge and experience with
`
`electronic design, mechanical design, and processes and materials for LCD
`
`manufacture.
`
`11. For this work, I reviewed and considered the following materials:
`
` U.S. Patent No. 9,281,405 B2 (“the ‘405 Patent”; Ex. 1001), including
`
`the specification and claims;
`
` The prosecution history of United States Patent Application No.
`
`14/337,583(“the ‘583 Application”), i.e., the prosecution history of
`
`the ‘405 Patent (Ex. 1002);
`
`In forming my opinions, I have relied upon my education, knowledge and
`
`experience with LCD technologies, including manufacturing processes and product
`
`design. I have also relied upon my education, knowledge and experience with
`
`
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`electronic design, mechanical design, and materials for LCDs and components
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`thereof.
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`
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`12.
`
`I have also been asked to review the subject matter disclosed by
`
`various patents and publications that are prior art to the ‘405 Patent, and have been
`
`further asked to compare the subject matter disclosed by those patents and
`
`publications to claims 10, 11, 15 and 16 of the ‘405 Patent and determine whether
`
`those patents and printed publications taught the claimed subject matter to a POSA
`
`prior to the earliest effective filing date of the ‘405 Patent, which I have been
`
`instructed to assume is December 23, 2011 for purposes of my analysis. The
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`principal documents that I have analyzed with regard to their teachings of subject
`
`matter claimed in the ‘405Patent are listed below:
`
`
`
`United States Patent Application Publication No. 2011/0193081 A1
`
`(“Godo”; Ex. 1004);and
`
`
`
`United States Patent Application Publication No. 2008/0299693 A1;
`
`(“Toyota”; Ex. 1005).
`
`Additional documents that I have analyzed are provided on the list of Exhibits
`
`attached hereto as Appendix A.
`
`
`
`
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`II.
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`PATENT PRINCIPLES
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`13.
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`I am an engineer by trade, and the opinions I express in this
`
`declaration involve the application of my engineering knowledge and experience to
`
`the evaluation of certain prior art with respect to the ‘405Patent. I am not a lawyer
`
`and have not been trained in the law of patents. Therefore, I have requested the
`
`attorneys from Taft, Stettinius & Hollister, who represent BlueHouse Global, to
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`provide me with guidance as to the applicable patent law in this matter. The
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`paragraphs below express my understanding of how I must apply current legal
`
`principles related to patent validity to my analysis.
`
`14.
`
`It is my understanding that in determining whether a patent claim
`
`under inter partes review before the United States Patent Office (PTO) is
`
`anticipated or obvious in view of the prior art, the PTO must construe the claim by
`
`giving the claim its broadest reasonable interpretation consistent with the
`
`specification as the claim terms and specification would be understood by a POSA.
`
`It is my understanding that the broadest reasonable interpretation is the plain
`
`meaning, i.e., the ordinary and customary meaning, given to the term by a POSA at
`
`the time of the invention, taking into account whatever guidance, such as through
`
`definitions, may be provided by the written description in the patent, without
`
`importing limitations from the specification. For the purposes of this review, I have
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`
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`construed each claim term in accordance with its plain meaning, i.e., its ordinary
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`and customary meaning under the required broadest reasonable interpretation.
`
`It is my understanding that a claim is anticipated under 35 U.S.C. § 102 if each and
`
`every limitation of the claim is disclosed in a single prior art reference, either
`
`expressly or inherently. I understand inherent disclosure to mean that the claim
`
`feature necessarily flows from the disclosure of the prior art reference. I understand
`
`that a claim is unpatentable under 35 U.S.C. § 103 if the claimed subject matter as a
`
`whole would have been obvious to a POSA at the time of the alleged invention,
`
`which I have been instructed to treat at present as the earliest effective filing date of
`
`the ‘405 Patent. I also understand that an obviousness analysis takes into account
`
`the scope and content of the prior art, the differences between the claimed subject
`
`matter and the prior art, and the level of ordinary skill in the art at the time of the
`
`invention. Finally, I understand that I must consider any known secondary evidence
`
`that might show nonobviousness of the application, such as long felt but unfulfilled
`
`need for the claimed invention, failure by others to come up with the claimed
`
`invention, commercial success of the claimed invention, praise of the invention by
`
`others in the field, unexpected results achieved by the invention, the taking of
`
`licenses under the patent by others, expressions of surprise by experts and those
`
`POSAs at the making of the invention, and the patentee proceeded contrary to the
`
`conventional wisdom of the prior art. But the secondary evidence must be tied
`
`
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`specifically to claim features that are argued to be patentable, and not those already
`
`in the public domain. I appreciate that secondary considerations must be assessed
`
`as part of the overall obviousness analysis (i.e., as opposed to analyzing the prior
`
`art, reaching a tentative conclusion, and then assessing whether objective indicia
`
`alter that conclusion).
`
`15. Put another way, my understanding is that not all innovations are
`
`patentable. Even if a claimed product or method is not explicitly described in its
`
`entirety in a single prior art reference, the patent claim will still be denied if the
`
`claim would have been obvious to a POSA at the time of the patent application
`
`filing.
`
`16.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art if it falls within
`
`the field of the inventor’s endeavor. In addition, a reference is prior art if it is
`
`reasonably pertinent to the particular problem with which the inventor was
`
`involved. A reference is reasonably pertinent if it logically would have
`
`commended itself to an inventor’s attention in considering his problem. If a
`
`reference relates to the same problem as the claimed invention, that supports use of
`
`the reference as prior art in an obviousness analysis.
`
`17. To assess the differences between prior art and the claimed subject
`
`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
`
`
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`to be considered as a whole. This “as a whole” assessment requires showing that a
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`POSA at the time of invention, confronted by the same problems as the inventor
`
`and with no knowledge of the claimed invention, would have selected the elements
`
`from the prior art and combined them in the claimed manner.
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`18.
`
`In determining whether the subject matter as a whole would have been
`
`considered obvious at the time that the patent application was filed, by a POSA, I
`
`have been informed of several principles regarding the combination of elements of
`
`the prior art. First, a combination of familiar elements according to known methods
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`is likely to be obvious when it yields predictable results. Likewise, combinations
`
`involving simple substitution of one known element for another to obtain
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`predictable results, a predictable use of prior art elements according to their
`
`established functions, applying a known technique to a known device (method or
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`product) ready for improvement to yield predictable results, and choosing from a
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`finite number of identified, predictable solutions to solve a problem are likely to be
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`obvious. Thus, if a POSA can implement a “predictable variation” in a prior art
`
`device, and would see the benefit from doing so, such a variation would be obvious.
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`Also, when there is pressure to solve a problem and there are a finite number of
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`identifiable, predictable solutions, it would be reasonable for a POSA to pursue
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`those options that fall within his or her technical grasp. If such a process leads to
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`the claimed invention, then the latter is not an innovation, but more the result of
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`ordinary skill and common sense.
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`19.
`
`I also understand that the “teaching, suggestion, or motivation” test is
`
`a useful guide in establishing a rationale for combining elements of the prior art.
`
`This test poses the question as to whether there is an explicit teaching, suggestion,
`
`or motivation in the prior art to combine prior art elements in a way that realizes
`
`the claimed invention. Though useful to the obviousness inquiry, I understand that
`
`this test should not be treated as a rigid rule. It is not necessary to seek out precise
`
`teachings; it is permissible to consider the inferences and creative steps that a
`
`POSA (who is considered to have an ordinary level of creativity and is not an
`
`“automaton”) would employ.
`
`20.
`
`It is my understanding that when interpreting the claims of the ‘405
`
`Patent I must do so based on the perspective of a POSA at the relevant priority
`
`date. My understanding is that the earliest priority date that is claimed by the ‘405
`
`Patent is December 23, 2011.
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`
`
`III. TECHNOLOGY BACKGROUND
`
`21. Semiconductor devices are electronic components that exploit the
`
`electronic properties of semiconductor materials, such as silicon. Semiconductor
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`materials are useful because their behavior can be easily manipulated by the
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`addition of impurities, known as doping. Current conduction in a semiconductor
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`occurs via mobile or “free” electrons and holes, collectively known as charge
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`carriers. Doping a semiconductor such as silicon with a small proportion of an
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`atomic impurity, such as phosphorus, greatly increases the number of free electrons
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`or holes within the semiconductor (a doped semiconductor containing excess holes
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`is called “p-type”; one containing excess free electrons is known as “n-type”).
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`22. A thin film transistor, or TFT, is an example of semiconductor device.
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`TFTs can be used as simple ON/OFF switches in a wide variety of electrical
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`devices, such as active-matrix LCD displays. Basically, a TFT consists of a
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`semiconductor and three electrodes: (i) the gate electrode; (ii) the source electrode;
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`and (iii) the drain electrode. The gate electrode must be insulated from the
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`semiconductor by a dielectric layer (or gate insulation layer), while the drain
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`electrode and source electrode must both directly contact the semiconductor.
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`Because of this, TFTs generally have one of the following configurations:
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`where “coplanar” in the drawings above refers to the gate electrode being on the
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`same side of the semiconductor as the source and drain electrode; “staggered”
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`refers to the gate electrode being on the opposite side of the semiconductor; and
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`“top” and “bottom” refer to the location of the gate electrode relative to the other
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`layers.
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`
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`IV. PERSON OF ORDINARY SKILL IN THE ART
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`
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`23. A United States patent is to be read and understood from the
`
`perspective of a person of ordinary skill in the relevant art (technical field) at the
`
`time the invention was made. Here, the relevant date is December 23, 2011, i.e.
`
`when the inventors named on the ‘405 Patent filed the original Japanese patent
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`applications to the subject matter now claimed in the ‘405 Patent and to which
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`priority is claimed.
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`
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`24.
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`It is my understanding that a person of ordinary skill in the art is a
`
`hypothetical person presumed to know the relevant prior art. Such a person is of
`
`ordinary creativity, not merely an automaton, and is capable of combining the
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`teachings of the prior art. The factors that may be used to determine the level of
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`skill of a person of ordinary skill in the art may include the education level of those
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`working in the field, the sophistication of the technology, the types of problems
`
`encountered in the art, prior art solutions to those problems and the speed at which
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`innovations in the art are made and implemented.
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`
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`25.
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`In this case, the ‘405 Patent is directed to improving the process of
`
`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
`
`in many display devices. A person of ordinary skill in the art should therefore
`
`have some at least some familiarity with the practical aspects of fabricating TFTs.
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`More specifically, a person of ordinary skill in the art of the ‘405 Patent as of
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`December 23, 2011, would have had at least a bachelor of science or engineering
`
`degree in electrical or mechanical engineering, semiconductor technology, display
`
`technology, physics, or a related field, and either an advanced degree (such as a
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`masters) or an equivalent amount of work experience, i.e. 2-3 years, in an area
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`relating to semiconductor design and/or fabrication, liquid crystal display (“LCD”)
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`design or fabrication, electrical engineering, or a related technical field.
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`26. Based on my experience, I have an understanding of the capabilities
`
`of a POSA in the relevant field. I have supervised and directed many such persons
`
`over the course of my career. Further, I had those capabilities myself at the time
`
`the ‘405 Patent was effectively filed.
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`
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`V. OVERVIEW OF THE ‘405 PATENT
`
`27. The ‘405Patent (Ex. 1001) is entitled “Semiconductor Device and
`
`Method for Manufacturing the Same” and names Shinya Sasagawa et al. as the
`
`inventors.
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`
`
`
`
`28. According to the specification, the ‘405 Patent relates “to a
`
`semiconductor device typified by a transistor and a method for manufacturing the
`
`semiconductor device.” Ex. 1001 at 1:18-20.
`
`
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`29. The specification discloses that
`
`a semiconductor device including a gate electrode layer; a gate
`insulating layer on and in contact with the gate electrode layer; an
`oxide semiconductor layer being on and in contact with the gate
`insulating layer and overlapping with the gate electrode layer; a first
`conductive layer and a second conductive layer provided on and in
`contact with the oxide semiconductor layer apart from each other with
`the gate electrode layer provided therebetween; a first low-resistance
`material layer on and in contact with the first conductive layer; a
`second low-resistance material layer on and in contact with the second
`conductive layer; a first protective layer on and in contact with the
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`first conductive layer, the first low-resistance material layer, the
`second conductive layer, and the second low-resistance material layer;
`and a second protective layer in contact with a part of the oxide
`semiconductor layer. In the semiconductor device, a distance between
`the first conductive layer and the second conductive layer is shorter
`than a distance between the first low-resistance material layer and the
`second low-resistance material layer. The first conductive layer and
`the first low-resistance material layer serve as a source electrode and
`the second conductive layer and the second low-resistance material
`layer serve as a drain electrode.
`
`Ex. 1001 at 4:40-63.
`
`
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`VI. PROSECUTION HISTORY OF THE ‘405 PATENT
`
`
`
`30. The prosecution history of the ‘405 Patent (Ex. 1002) is relatively
`
`brief, with the majority of the claims, including the challenged claims being
`
`allowed in the first Office Action on the merits. Ex. 1002 at 8-18.
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`
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`31. Neither of the references relied upon herein was cited or considered
`
`during the prosecution of the ‘405 Patent.
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`
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`VII. CLAIM CONSTRUCTION
`
`32. Counsel for Petitioner has advised me that they do not believe that any
`
`claim term in the ‘405 Patent requires specific construction. Based on my review
`
`of the specification and claims of the ‘405 Patent, I concur with that conclusion.
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`VIII. SUMMARY OF OPINIONS
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`33. Based on my review of the ‘405 Patent, its prosecution history, and
`
`the patents and publications listed above, it is my opinion that the subject matter of
`
`claims 10, 11, 15 and 16 of the ‘405 Patent was, as of the effective filing date of
`
`the ‘405 Patent, unpatentable as either anticipated or obvious in view of the various
`
`prior art references identified, the grounds for which are listed and explained
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`below.
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`
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`IX. UNPATENTABILITY OF CLAIMS 10, 11, 15 AND 16
`
`
`
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`A. Claims 10, 11, 15 and 16 are anticipated by Godo
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`34. Claims 10, 11, 15 and 16 of the ‘405 Patent are anticipated by Godo
`
`(Ex. 1004) as explained below.
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`1.
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`
`
`Claim 10
`
`a.
`
`The preamble
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`35. The preamble of claim 10 of the ‘405 Patent recites “[a]
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`semiconductor device comprising . . ..” Ex 1001 at 29:48. If deemed a limitation,
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`then this limitation is expressly disclosed by Godo. Specifically, Godo discloses
`
`that “[t]he present invention relates to a semiconductor device.” Ex. 1004 at ¶ 1.
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`
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`36. Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Godo.
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`b.
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`a gate electrode layer
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`37. The first element of claim 10 is a gate electrode layer. Ex. 1001 at
`
`29:49. Godo identically discloses this element.
`
`
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`38. Godo discloses a semiconductor device having a gate electrode layer.
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`Ex. 1004 at ¶¶ 51,52. More specifically, Godo discloses that FIGS. 1A and 1B
`
`both depict transistors, i.e., “FIGS. 1A and 1B each illustrate a cross-sectional
`
`structure of a transistor as an example of a semiconductor device.” Id. at ¶ 51.
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`Further, Godo discloses that FIG. 1B depicts a simple variation of the transistor
`
`shown in FIG. 1A in which there is a two-layer conductor structure for each of the
`
`source electrode and the drain electrode, i.e.,
`
`Alternatively, as in a transistor 190 illustrated in FIG. 1B, a structure
`in which the source electrode 141a has a structure in which a second
`conductive layer 145a and a first conductive layer 142a are stacked in
`this order and the drain electrode 141b has a structure in which a
`second conductive layer 145b and a first conductive layer 142b are
`stacked in this order may be employed.
`
`Id. at ¶ 55. And, finally, Godo expressly discloses that both of these transistors
`
`have a gate electrode; “A transistor…includes…a gate electrode 148….” Id. at 52.
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`
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`39. Godo’s FIG. 1B, showing the gate electrode 148, is reproduced
`
`below:
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`40. Godo therefore discloses a gate electrode layer.
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`
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`c.
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`a gate insulating layer . . .
`
`41. The second element of claim 10 is a gate insulating layer over the
`
`gate electrode layer. Ex 1001 at 29:50. Godo identically discloses this element,
`
`and in the same arrangement as recited in the claim.
`
`
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`42. Godo discloses a semiconductor device having a gate insulating layer
`
`over the gate electrode layer. Godo discloses that the transistor “includes, . . . a
`
`gate insulating layer 146 provided over the gate electrode 148 . . ..” Ex. 1004 at ¶
`
`52.
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`
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`43. Godo’s FIG. 1B is reproduced below:
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`As shown in this FIG., the gate insulating layer 146 is over, and directly on top of,
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`the gate electrode 148.
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`
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`44. Godo therefore discloses a gate insulating layer over the gate
`
`electrode layer.
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`
`d.
`
`a semiconductor layer . . .
`
`45. The third element of the semiconductor device of claim 10 is a
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`semiconductor layer over the gate insulating layer. Ex. 1001 at col. 29:51. Godo
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`identically discloses this element, and in the same arrangement as recited in the
`
`claim.
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`
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`46. Godo discloses a semiconductor device having a semiconductor layer
`
`over the gate insulating layer. More specifically, Godo discloses that the transistor
`
`“includes . . . an oxide semiconductor layer 144a provided over the gate insulating
`
`layer 146 . . ..” Ex. 1004 at ¶ 52.
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`
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`47. Godo’s FIG. 1Bis reproduced below:
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`As shown in this FIG., the semiconductor layer (144a) is over, and, in fact, sits
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`directly upon, the gate insulating layer (146).
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`
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`48. Godo therefore discloses a semiconductor layer over the gate
`
`insulating layer.
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`
`
`
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` e.
`
`a first conductive layer . . .
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`49. The fourth element of the semiconductor device of claim 10 is a first
`
`conductive layer and a second conductive layer over the semiconductor layer. Ex
`
`1001 at col. 29:52-53. Godo identically discloses this element, and in the same
`
`arrangement as recited in the claim.
`
`
`
`50. Godo discloses a semiconductor device having a source electrode and
`
`a drain electrode. More specifically, Godo discloses that the transistor “includes, .
`
`. . a source electrode 141a and a drain electrode 141b . . ..” Ex. 1004 at ¶ 52.
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`
`
`
`
`
`
`51. Godo’s FIG. 1Bis reproduced below:
`
`20
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`BLUEHOUSE EXHIBIT 1003
`Page 21 of 79
`
`
`
`As can be seen in this FIG., the source electrode 141a is composed of two layers,
`
`142a and 145a. Similarly, the drain electrode 141b is also composed of two layers,
`
`142b and 145b.
`
`
`
`52. Godo discloses that FIG. 1B depicts “a structure in which the source
`
`electrode 141a has a structure in which a second conductive layer 145a and a first
`
`conductive layer 142a are stacked in this order and the drain electrode 141b has a
`
`structure in which a second conductive layer 145b and a first conductive layer
`
`142b are stacked in this order may be employed.” Ex. 1004 at ¶ 55. Thus, Godo
`
`discloses that the two layers that compose the source electrode are both conductive
`
`layers and the two layers that compose the drain electrode are both conductive
`
`layers. Godo’s conductive layer 145a corresponds to the claimed first conductive
`
`layer and Godo’s conductive layer 145b corresponds to the claimed second
`
`conductive layer.
`
`
`
`53. Godo further discloses that the “source electrode 141a and a drain
`
`electrode 141b [are] provided over the gate insulating layer 146 and [the] layer
`
`150a” and that “layer 150a [is] provided on and in contact with the oxide
`
`semiconductor layer 144a.” Ex. 1004 at ¶ 52. Based on this arrangement, and as
`
`clearly shown in FIG. 1B above, the source electrode 141a and the drain electrode
`
`141b are above (over) the semiconductor layer 144a.
`
`
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`21
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`BLUEHOUSE EXHIBIT 1003
`Page 22 of 79
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`
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`
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`54. Godo therefore discloses a first conductive layer and a second
`
`conductive layer over the semiconductor layer.
`
`
`
`
`
`
`
`
`
`f.
`
`a third conductive layer . . .
`
`55. The next element of claim 10 is a third conductive layer over the first
`
`conductive layer. Ex 1001 at 29:54. Godo identically discloses this element, and in
`
`the same arrangement as recited in the claim.
`
`
`
`56. Godo’s FIG. 1B depicts a semiconductor device “in which the source
`
`electrode 141a has a structure in which a second conductive layer 145a and a first
`
`conductive layer 142a are stacked in this order and the drain electrode 141b has a
`
`structure in which a second conductive layer 145b and a first conductive layer
`
`142b are stacked in this order.” Ex. 1004 at ¶ 55. As described above, Godo’s
`
`145a corresponds to the claimed first conductive layer; Godo’s 142a corresponds
`
`to the claimed third conductive layer.
`
`
`
`
`
`
`
`57. Godo’s FIG. 1B is shown below:
`
`22
`
`BLUEHOUSE EXHIBIT 1003
`Page 23 of 79
`
`
`
`where 142a and 145a are the two conductive layers (the first conductive layer and
`
`the third conductive layer) that together form the source electrode 141a. Ex. 1004
`
`at ¶ 55. As shown in this FIG., the third conductive layer 142a is above (over) the
`
`first conductive layer 145a.
`
`
`
`58. Godo therefore discloses a third conductive layer over the first
`
`conductive layer.
`
`
`
`
`
`
`
`
`
`g.
`
`a fourth conductive layer . . .
`
`59. The next element of claim 10 is a fourth conductive layer over the
`
`second conductive layer. Ex 1001 at 29:55-56. Godo identically discloses this
`
`element, and in the same arrangement as recited in the claim.
`
`
`
`60. Godo’s FIG. 1B depicts a semiconductor device “in which the source
`
`electrode 141a has a structure in which a second conductive layer 145a and a first
`
`conductive layer 142a are stacked in this order and the drain electrode 141b has a
`
`structure in which a second conductive layer 145b and a first conductive layer
`
`142b are stacked in this order.” Ex. 1004 at ¶ 55. As described above, Godo’s
`
`145b corresponds to the claimed second conductive layer; Godo’s 142b
`
`corresponds to the claimed fourth conductive layer.
`
`
`
`
`
`
`
`
`
`61. Godo’s FIG. 1B is shown below:
`
`23
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`BLUEHOUSE EXHIBIT 1003
`Page 24 of 79
`
`
`
`
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`where 142b and 145b are the two conductive layers (the second conductive layer
`
`and the fourth conductive layer) that together form the drain electrode 141b. As
`
`shown in this FIG., the fourth conductive layer 142b is stacked above (over) and
`
`directly on the second conductive layer 145b.
`
`
`
`62. Godo therefore identically discloses the fourth conductive layer over
`
`the second conductive layer limitation of claim 10.
`
`
`
`
`
`
`
` h.
`
`a first insulating layer . . .
`
`63. The final element of claim 10 of the ‘405 Patent is a first insulating
`
`layer over the third conductive layer and the fourth conductive layer. Ex. 1001 at
`
`29:57-58. Godo identically discloses this element, and in the same arrangement as
`
`recited in the claim.
`
`
`
`64. Godo discloses that a “protective insulating layer” is formed over the
`
`semiconductor device after formation of the source electrode and the drain
`
`electrode. More specifically, Godo teaches that a “second heat treatment is
`
`performed after the source electrode 141a and the drain electrode 141b are formed
`
`
`
`24
`
`BLUEHOUSE EXHIBIT 1003
`Page 25 of 79
`
`
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`in this embodiment; however, the timing of the second heat treatment is not
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`particularly limited to this. For example, the second heat treatment may be
`
`performed after a protective insulating layer is formed over the transistor . .
`
`..” Ex. 1004 at ¶ 110 (emphasis added).
`
`
`
`65. Godo’s FIG. 1B is shown below:
`
`where 190 is the transistor and 142a and 142b are the upper conductive layers of
`
`the source electrode 141a and the drain electrode 141b, respectively (i.e. the
`
`claimed third conductive layer and the claimed fourth conductive layer,
`
`respectively). Ex. 1004 at ¶ 55.
`
`
`
`66. Since Godo teaches that the “protective insulating layer” is to be
`
`formed over the transistor, the “protective insulating layer” formed over the
`
`transistor shown in FIG. 1B would necessarily be on top of, and therefore over, the
`
`upper layer of the source electrode 142a (i.e. the claimed third conductive layer)
`
`and the upper layer of the drain electrode 142b (i.e. the claimed fourth conductive
`
`layer).
`
`
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`25
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`BLUEHOUSE EXHIBIT 1003
`Page 26 of 79
`
`
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`
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`67. Godo therefore identically discloses a first insulating layer over the
`
`third conductive layer and the fourth conductive layer.
`
`
`
`
`
`
`
`
`
`i.
`
`the wherein clauses
`
`68. The final limitations of claim 10 are two wherein clauses relating to
`
`the claimed first conductive layer, second conductive layer, thirdconductive layer
`
`and fourth conductive layer. As described below, Godo identically discloses both
`
`of these features of the claimed semiconductor device.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` i.
`
`
`
`
`wherein a distance between the first conductive
`layer and the second conductive layer is shorter than a
`distance between the third conductive layer and the
`fourth conductive layer
`
`69. The first wherein clause relates to the distance between the upper
`
`layers of the electrodes (142a and 142b) and the distance between the lower layers
`
`of the electrodes (145a and 145b). Ex. 1001 at 29:59-62. More specifically, the
`
`first wherein clause of claim 10 requires that a distance between the first
`
`conductive layer and the second conductive layer is shorter than a distance
`
`between the third conductive layer and the fourth conductive layer. Ex. 1001 at
`
`29:59-62. Godo identically discloses this feature.
`
`
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`
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`70. Godo’s FIG. 1B is shown below:
`
`26
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`BLUEHOUSE EXHIBIT 1003
`Page 27 of 79
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`
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`A magnification of a region of the transistor 190 in the FIG. 1B above, with the
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`relevant
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