Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1004
`
`EX. 1004
`
`

`

`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2011/0193081 A1
`
`
` GODO et al. (43) Pub. Date: Aug. 11, 2011
`
`US 20110193081A1
`
`(54) SEMICONDUCTOR DEVICE
`
`Publication Classification
`
`(75)
`
`Inventors:
`
`Hiromichi GODO, lsehara (JP);
`YasuyukiARAI, Atsugi (JP);
`Satohiro OKAMOTO, Fukuroi
`(JP); Mari TERASHIMA, Ayase
`(JP); Eriko NISHIDA, Atsugi (JP);
`Junpei SUGAO,Atsugi (JP)
`
`(73) Assignee:
`
`SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.,
`Kanagawa-ken (JP)
`
`(21) Appl. No.:
`
`13/018,879
`
`(22)
`
`Filed:
`
`Feb. 1’ 2011
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 5, 2010
`
`(JP) ................................. 2010-024636
`
`(51)
`
`Int. Cl.
`(2006.01)
`H01L 29/78
`(52) us. Cl. ................................... 257/43; 257/E29.273
`
`ABSTRACT
`(57)
`An object is to provide a semiconductor device including an
`oxide semiconductor in which miniaturization is achieved
`while favorable characteristics are maintained. The semicon-
`ductor includes an oxide semiconductor layer, a source elec-
`trode and a drain electrode in contact with the oxide semicon-
`ductor layer, a gate electrode overlapping with the oxide
`semiconductor
`layer,
`a gate insulating layer provided
`between the oxide semiconductor layer and the gate elec-
`trode, and an insulating layer provided in contact with the
`oxide semiconductor layer. A side surface of the oxide semi-
`conductor layer is in contact with the source electrode or the
`drain electrode. An upper surface ofthe oxide semiconductor
`layer overlaps with the source electrode or the drain electrode
`with the insulating layer interposed between the oxide semi-
`conductor layer and the source electrode or the drain elec-
`trode.
`
`141a
`
`122:
`
`a
`
`150a 144a
`
`
`i \\
`.. \\
`
`
`190
`
`
`
`
`-
`142b
`\\\\\\\\m—“—“&‘\\\\
`
`,,
`,
`
`NI
`a, 100
`
`
`146
`148
`
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`

`

`Patent Application Publication
`
`Aug. 11, 2011 Sheet 1 of 12
`
`US 2011/0193081 A1
`
`150a 144a
`
`180
`
`
`
`14
`
`150a 144a
`
`190
`
`
`
`14
`
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`

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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 2 of 12
`
`US 2011/0193081 A1
`
`FIG. 2A
`
`
`
`
`FIG. 20
`
`FIG. 2D
`
`
`
`
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`

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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 3 of 12
`
`US 2011/0193081 A1
`
`FIG. 3A
`
`\
`
`..
`
`
` 245a _
`242a
`\\\\\\\\\\\\\\\
`:
`
`
`
`
`A“
`
`
`
`
`2453 _ v; \ ,
`.
`2423 ~\\\\\“\\\\\\\ _
`
`
`
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`

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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 4 of 12
`
`US 2011/0193081 A1
`
`246
`
`248
`
`FIG. 4A
`
`
`252
`
`
`
`
` 245b
`
`
`
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`

`

`Patent Application Publication
`
`Aug. 11, 2011 Sheet 5 of 12
`
`US 2011/0193081 A1
`
`FIG. 5A
`
`
`
`344a
`
`3508
`
`FIG. 5B
`
`341a { 342a
`
`
`
` I ~ l:\\
`
`\\\T\\\
`\\ 3433} 341b
`[”7 ~ 3353b
`
`
`
`344a
`
`350a
`
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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 6 of 12
`
`US 2011/0193081 A1
`
`FIG. 6A
`
`FIG. GB
`
`
`
`344
`
`350
`
`344a 350a
`
`
`
`FIG. 6D
`
`FIG. 6E
`
`346
`
`
`
`
`
`‘Q&§§§§E:_______‘ww§;::\\\\\\
`
`~
`~
`
`
`
`"X:
`
`
`‘
`‘\\\\\
`
`
`
`
`
`
`
`
`I
`
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`

`

`Patent Application Publication
`
`Aug. 11, 2011 Sheet 7 of 12
`
`US 2011/0193081 A1
`
`FTC3.'7
`
` ‘\
`
`.
`m7~
`
`446a 444a
`
`400
`
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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 8 of 12
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`US 2011/0193081 A1
`
`FIG. 8A
`
`450
`
`
`
`v'rrrv‘
`
`
`
`
`x‘““““““‘“““‘“‘“
`
`r ~
`
`I
`
`
`
`
`
`
`
`
`
`A
`.
`\
`
`\\
`\
`L\ \ ““““‘ §
`
`
`
` A A
`
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`
`FIG. SB
`
`FIG. 80
`
`FIG. 8D
`
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`

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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 9 of 12
`
`US 2011/0193081 A1
`
`FIG. 9A1
`
`FIG. QB
`
`
`
`
`
`
`
`
`3‘53"- 3rd Line
` \
`
`
`It
`
`I
`
`1...........'\
`
`500
`
`1st Line
`
`:'"""""‘\
`
`500
`
`1st Line
`
`I 0
`
`8
`
`C1
`
`R1
`
`R2
`
`C2
`
`FIG. 9A2
`
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`

`Patent Application Publication
`
`Aug. 11, 2011 Sheet 10 0f 12
`
`US 2011/0193081 A1
`
`FIG. 10A WU”
`
`81(1)
`
`520 500 BLU)
`
`FIG. 1OB
`
`
`BL(1)
`
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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 11 of 12
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`US 2011/0193081 A1
`
`FIG. 11A
`
`Vdd
`
`|
`
`Vbias
`
`
`
`
`sense amplifier
`
`output
`
`terminalA
`
`FIG. IIB
`
`FIG. 11C)
`
`
`
`Vdd
`
`IHSD
`
`V2
`
`|—°Sn
`
`GND
`
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`Patent Application Publication
`
`Aug. 11, 2011 Sheet 12 of 12
`
`US 2011/0193081 A1
`
`FIG. 12A
`
`FIG. 12D
`
`647
`
` 61
`
`\\\\\\\\\\\\\\\\\\\\\*9‘9}
`§\\\\\\\\\\\\\\\\\\\\\\\\\\\\§
`s_----—--_-—--—--—-—--_-—-4
`675
`
`7/
`
`/,.’.’.’./l
`
` \ \
`
`FIG. 120
`
`627 623 @ 625 621
`
`
`
`
`7
`(lllllllllIllllllllllllllllllllll /’
`
`i
`
`
`
`
`
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`US 2011/0193081A1
`
`Aug. 11,2011
`
`SEMICONDUCTOR DEVICE
`
`TECHNICAL FIELD
`
`[0001] The present invention relates to a semiconductor
`device. Here, semiconductor devices refer to general ele-
`ments and devices which function by utilizing semiconductor
`characteristics.
`
`BACKGROUND ART
`
`[0002] There are a wide variety of metal oxides and such
`metal oxides are used for various applications. Indium oxide
`is a well-known material and has been used for transparent
`electrodes required in liquid crystal display devices or the
`like.
`
`Some metal oxides have semiconductor character-
`[0003]
`istics. The examples of such metal oxides having semicon-
`ductor characteristics are, for example, tungsten oxide, tin
`oxide, indium oxide, zinc oxide, and the like. A thin film
`transistor in which a channel formation region is formed
`using such metal oxides is already known (for example, see
`Patent Documents 1 to 4, Non-Patent Document 1, and the
`like).
`[0004] As metal oxides, not only single-component oxides
`but also multi-component oxides are known. For example,
`InGaO3(ZnO)m (m: natural number) having a homologous
`phase is known as a multi-component oxide semiconductor
`including In, Ga, and Zn (for example, see Non-Patent Docu-
`ments 2 to 4 and the like).
`[0005]
`Furthermore, it is confirmed that an oxide semicon-
`ductor including such an In%a7Zn-based oxide is appli-
`cable to a channel formation region of a thin film transistor
`(for example, see Patent Document 5, Non-Patent Documents
`5 and 6, and the like).
`
`REFERENCE
`
`Patent Documents
`
`[Patent Document 1] Japanese Published Patent
`[0006]
`Application No. S60-198861
`[0007]
`[Patent Document 2] Japanese Published Patent
`Application No. HOS-264794
`[0008]
`[Patent Document 3] Japanese Translation of PCT
`International Application No. H11-505377
`[0009]
`[Patent Document 4] Japanese Published Patent
`Application No. 2000-150900
`[0010]
`[Patent Document 5] Japanese Published Patent
`Application No. 2004-103957
`
`Non-Patent Documents
`
`[Non-Patent Document 1] M. W. Prins, K. O.
`[0011]
`Grosse-Holz, G Muller, J. F. M. Cillessen, J. B. Giesbers,
`R. P. Weening, and R. M. Wolf, “A ferroelectric transparent
`thin-film transistor”, Appl. Phys. L611, 17 Jun. 1996, Vol.
`68, pp. 3650-3652
`[0012]
`[Non-Patent Document 2] M. Nakamura, N. Kimi-
`zuka, and T. Mohri, “The Phase Relations in the In2037
`Ga2ZnO47ZnO System at 13500 C.”, J. Solid State Chem,
`1991, Vol. 93, pp. 298-315
`[0013]
`[Non-Patent Document 3] N. Kimizuka, M. Isobe,
`and M. Nakamura, “Syntheses and Single-Crystal Data of
`Homologous Compounds, In203(ZnO)m (m:3, 4, and 5),
`InGaO3(ZnO)3, and Ga203(ZnO)m (m:7, 8, 9, and 16) in
`
`J. Solid State
`
`the In2037ZnGa2047ZnO System”,
`Chem, 1995,Vol. 116, pp. 170-178
`[0014]
`[Non-Patent Document 4] M. Nakamura, N. Kimi-
`zuka, T. Mohri, and M. Isobe, “Syntheses and crystal struc-
`tures of new homologous compounds, indium iron zinc
`oxides (InFeO3(ZnO)m) (mznatural number) and related
`compounds”, KOTAI BUTSURI (SOLID STATE PHYS-
`ICS), 1993, Vol. 28, No. 5, pp. 317-327
`[0015]
`[Non-Patent Document 5] K. Nomura, H. Ohta, K.
`Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film
`transistor fabricated in single-crystalline transparent oxide
`semiconductor”, SCIENCE, 2003,Vol. 300, pp. 1269-1272
`[0016]
`[Non-Patent Document 6] K. Nomura, H. Ohta, A.
`Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-
`temperature fabrication of transparent flexible thin-film
`transistors using amorphous oxide semiconductors”,
`NATURE, 2004, Vol. 432, pp. 488-492
`
`DISCLOSURE OF INVENTION
`
`In order to achieve high-speed operation, low power
`[0017]
`consumption, cost reduction, or the like of a transistor, it is
`necessary to miniaturize a transistor.
`[0018]
`In the case where a transistor is miniaturized, a
`defect generated in a manufacturing process becomes a major
`problem. For example, in the case where a transistor is min-
`iaturized, a short-channel effect becomes a problem. Here,
`the short-channel effect refers to degradation of electrical
`characteristics which becomes pronounced with miniaturiza-
`tion of a transistor (a reduction in channel length (L)). The
`short-channel effect results from the effect of an electric field
`
`of a drain on a source. Specific examples of the short-channel
`effect are decrease in the threshold voltage, increase in the
`subthreshold swing (S value), increase in leakage current, and
`the like. In particular, it is known that a transistor including an
`oxide semiconductor has small off-state current at room tem-
`
`perature as compared to a transistor including silicon. This is
`thought to be attributed to the fact that carriers generated by
`thermal excitation are few, that is, the carrier density is low. A
`transistor including a material having low carrier density
`tends to show a short-channel effect such as decrease in the
`
`threshold voltage.
`[0019] Therefore, it is an object of one embodiment of the
`disclosed invention to provide a semiconductor device which
`achieves miniaturization while defects are suppressed. Fur-
`ther, it is another object to provide a semiconductor device
`which achieves miniaturization while favorable characteris-
`tics are maintained.
`
`[0020] One embodiment of the present invention is a semi-
`conductor device including an oxide semiconductor layer, a
`source electrode and a drain electrode in contact with the
`
`oxide semiconductor layer, a gate electrode overlapping with
`the oxide semiconductor layer, a gate insulating layer pro-
`vided between the oxide semiconductor layer and the gate
`electrode, and an insulating layer provided in contact with the
`oxide semiconductor layer. A side surface of the oxide semi-
`conductor layer is in contact with the source electrode or the
`drain electrode. An upper surface of the oxide semiconductor
`layer overlaps with the source electrode or the drain electrode
`with the insulating layer interposed between the oxide semi-
`conductor layer and the source electrode or the drain elec-
`trode.
`
`[0021] Another embodiment of the present invention is a
`semiconductor device including a gate electrode provided
`over a substrate, a gate insulating layer provided over the gate
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`US 2011/0193081 A1
`
`Aug. 11,2011
`
`electrode, an oxide semiconductor layer provided over the
`gate insulating layer, an insulating layer provided on and in
`contact with the oxide semiconductor layer, and a source
`electrode and a drain electrode provided over the insulating
`layer and the gate insulating layer. A side surface ofthe oxide
`semiconductor layer is in contact with the source electrode or
`the drain electrode. An upper end of the side surface of the
`oxide semiconductor layer aligns with a lower end of a side
`surface of the insulating layer.
`[0022] Another embodiment of the present invention is a
`semiconductor device including an oxide semiconductor
`layer provided over a substrate, an insulating layer provided
`on and in contact with the oxide semiconductor layer, a source
`electrode and a drain electrode provided over the substrate
`and the insulating layer, a gate insulating layer provided over
`the insulating layer, the source electrode, and the drain elec-
`trode, and a gate electrode provided over the gate insulating
`layer. A side surface of the oxide semiconductor layer is in
`contact with the source electrode or the drain electrode. An
`
`upper surface of the oxide semiconductor layer overlaps with
`the source electrode or the drain electrode with the insulating
`layer interposed between the oxide semiconductor layer and
`the source electrode or the drain electrode.
`
`In the above structure, it is preferable that an upper
`[0023]
`end ofthe side surface of the oxide semiconductor layer align
`with a lower end of the side surface of the insulating layer.
`Further, it is preferable that each of the source electrode and
`the drain electrode include a first conductive layer and a
`second conductive layer having higher resistance than the
`first conductive layer and that the second conductive layer be
`in contact with the oxide semiconductor layer.
`[0024] Another embodiment of the present invention is a
`semiconductor device including a gate electrode provided
`over a substrate, a gate insulating layer provided over the gate
`electrode, a source electrode and a drain electrode provided
`over the gate insulating layer each of which includes a first
`conductive layer and a second conductive layer having higher
`resistance than the first conductive layer, an oxide semicon-
`ductor layer which overlaps with the gate electrode and is
`provided in contact with the second conductive layer, and an
`insulating layer provided between the first conductive layer
`and the oxide semiconductor layer.
`[0025]
`In the above structure, it is preferable that the second
`conductive layer have a region extending beyond a side sur-
`face ofthe first conductive layer in a channel length direction.
`In addition, the thickness of the second conductive layer is
`preferably 5 nm to 15 nm. Moreover, the second conductive
`layer is preferably formed of a nitride of a metal.
`to general
`[0026] Here,
`semiconductor devices
`refer
`devices which function by utilizing semiconductor character-
`istics. For example, a display device, a memory device, an
`integrated circuit, and the like are included in the category of
`the semiconductor device.
`
`In this specification and the like, the term such as
`[0027]
`“over” or “below” does not necessarily mean that a compo-
`nent is placed “directly on” or “directly below” another com-
`ponent. For example, the expression “a gate electrode over a
`gate insulating layer” can mean the case where there is an
`additional component between the gate insulating layer and
`the gate electrode. Moreover, the terms such as “over” and
`“below” are only used for convenience of description and can
`include the case where the relation of components is reversed,
`unless otherwise specified.
`
`In addition, in this specification and the like, the
`[0028]
`term such as “electrode” or “wiring” does not limit a function
`of a component. For example, an “electrode” is sometimes
`used as part of a “wiring”, and vice versa. Furthermore, the
`term “electrode” or “wiring” can include the case where a
`plurality of “electrodes” or “wirings” are formed in an inte-
`grated manner.
`[0029]
`Functions of a “source” and a “drain” are sometimes
`replaced with each other when a transistor of opposite polar-
`ity is used or when the direction of current flow is changed in
`circuit operation, for example. Therefore, the terms “source”
`and “drain” can be replaced with each other in this specifica-
`tion.
`
`[0030] Note that in this specification and the like, the term
`“electrically connected” includes the case where components
`are connected through an object having any electric function.
`There is no particular limitation on an object having any
`electric function as long as electric signals can be transmitted
`and received between components that are connected through
`the object. Examples of an “object having any electric func-
`tion” are a switching element such as a transistor, a resistor, an
`inductor, a capacitor, and an element with a variety of func-
`tions as well as an electrode and a wiring.
`[0031] According to one embodiment of the disclosed
`invention, an electric field between the source electrode and
`the drain electrode can be relaxed when the vicinity of the
`interface where the oxide semiconductor layer is in contact
`with the source electrode or the drain electrode is made to be
`
`a high resistance region. Therefore, a short-channel effect
`such as decrease in the threshold voltage can be suppressed.
`[0032] Thus,
`the problems with miniaturization can be
`solved. As a result, the size ofthe transistor can be sufficiently
`reduced. When the size of the transistor is sufficiently
`reduced, the size of a semiconductor device is also reduced
`and thus the number of semiconductor devices manufactured
`
`from one substrate is increased. Accordingly, manufacturing
`cost per semiconductor device is reduced. Since the semicon-
`ductor device is miniaturized, a semiconductor device with a
`size similar to that of the conventional semiconductor device
`
`can have improved functions. Further, effects such as high
`speed operation, reduction in power consumption, and the
`like can be obtained because of reduction in channel length.
`That is, miniaturization of a transistor including an oxide
`semiconductor is achieved in accordance with one embodi-
`ment of the disclosed invention, and various effects accom-
`panying therewith can also be obtained.
`[0033]
`In this manner, according to one embodiment of the
`disclosed invention, a semiconductor device which achieves
`miniaturization while defects are suppressed or favorable
`characteristics are maintained can be provided.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`In the accompanying drawings:
`[0034]
`FIGS. 1A and 1B are each a cross sectional view of
`[0035]
`a semiconductor device;
`[0036]
`FIGS. 2A to 2E are cross-sectional views of manu-
`facturing steps of a semiconductor device;
`[0037]
`FIGS. 3A to 3C are each a cross-sectional view ofa
`semiconductor device;
`[0038]
`FIGS. 4A to 4F are cross-sectional views of manu-
`facturing steps of a semiconductor device;
`[0039]
`FIGS. 5A and 5B are each a cross-sectional view of
`a semiconductor device;
`
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`US 2011/0193081 A1
`
`Aug. 11,2011
`
`FIGS. 6A to 6E are cross-sectional views of manu-
`[0040]
`facturing steps of a semiconductor device;
`[0041]
`FIG. 7 is a cross-sectional view ofa semiconductor
`device;
`FIGS. 8A to 8D are cross-sectional views of manu-
`[0042]
`facturing steps of a semiconductor device;
`[0043]
`FIGS. 9A1, 9A2, and 9B are each an example ofa
`circuit diagram of a semiconductor device;
`[0044]
`FIGS. 10A and 10B are each an example of a circuit
`diagram of a semiconductor device;
`[0045]
`FIGS. 11A to 11C are each an example ofa circuit
`diagram of a semiconductor device; and
`[0046]
`FIGS. 12A to 12F are each an example ofan elec-
`tronic device.
`
`BEST MODE FOR CARRYING OUT THE
`INVENTION
`
`[0047] Hereinafter, embodiments of the present invention
`will be described with reference to the drawings. Note that the
`present invention is not limited to the following description
`and it will be readily appreciated by those skilled in the art
`that modes and details can be modified in various ways with-
`out departing from the spirit and the scope of the present
`invention. Therefore, the present invention should not be
`construed as being limited to the description in the following
`embodiment.
`
`[0048] Note that the position, the size, the range, or the like
`of each structure illustrated in drawings and the like is not
`accurately represented in some cases for easy understanding.
`Therefore, the disclosed invention is not necessarily limited
`to the position, size, range, or the like as disclosed in the
`drawings and the like.
`[0049]
`In this specification and the like, ordinal numbers
`such as “first”, “second”, and “third” are used in order to
`avoid confusion among components, and the terms do not
`mean limitation of the number of components.
`
`Embodiment l
`
`In this embodiment, a structure and a manufacturing
`[0050]
`process of a semiconductor device according to one embodi-
`ment of the disclosed invention will be described with refer-
`ence to FIGS. 1A and 1B and FIGS. 2A to 2E.
`
`<Example of Structure of Semiconductor Device>
`
`FIGS. 1A and 1B each illustrate a cross-sectional
`[0051]
`structure of a transistor as an example of a semiconductor
`device. In each of FIGS. 1A and 1B, a bottom gate transistor
`is illustrated as a transistor of one embodiment of the dis-
`closed invention.
`
`[0052] A transistor 180 illustrated in FIG. 1A includes, over
`a substrate 100, a gate electrode 148, a gate insulating layer
`146 provided over the gate electrode 148, an oxide semicon-
`ductor layer 144a provided over the gate insulating layer 146,
`an insulating layer 150a provided on and in contact with the
`oxide semiconductor layer 144a, and a source electrode 141a
`and a drain electrode 141!) provided over the gate insulating
`layer 146 and the insulating layer 150a.
`[0053]
`In the transistor 180 illustrated in FIG. 1A, side
`surfaces of the oxide semiconductor layer 14411 are in contact
`with the source electrode 141a and the drain electrode 1411).
`
`Further, upper ends ofthe side surfaces ofthe oxide semicon-
`ductor layer 144a align with lower ends of side surfaces ofthe
`insulating layer 150a and the oxide semiconductor layer 144a
`
`overlaps with the source electrode 141a and the drain elec-
`trode 14119 with the insulating layer 150a over the oxide
`semiconductor layer 144a therebetween. That is, the oxide
`semiconductor layer 14411 is in contact with the source elec-
`trode 141a and the drain electrode 141!) only at the side
`surfaces.
`
`In this specification, the “side surface” means a sur-
`[0054]
`face generated in such a manner that an oxide semiconductor
`layer, a conductive film, or the like is cut in a direction
`substantially perpendicular to a surface of the substrate. Fur-
`ther, the “side surface” means a surface generated in such a
`manner that an oxide semiconductor layer, a conductive film,
`or the like is cut at a range of 130° to 160° with respect to a
`direction perpendicular to the surface ofthe substrate. That is,
`the “side surface” means a cut surface generated by etching a
`film-like structure. Note that in this specification, “aligning
`with” includes “substantially aligning with”. For example, a
`side surface of a layerA and a side surface of a layer B, which
`are included in a stacked structure and etched using the same
`mask, are considered to align with each other.
`[0055] Alternatively, as in a transistor 190 illustrated in
`FIG. 1B, a structure in which the source electrode 14111 has a
`structure in which a second conductive layer 145a and a first
`conductive layer 14211 are stacked in this order and the drain
`electrode 141!) has a structure in which a second conductive
`
`layer 1451) and a first conductive layer 1421) are stacked in this
`order may be employed.
`
`<Example of Manufacturing Steps of Transistor>
`
`[0056] An example of steps ofmanufacturing the transistor
`illustrated in FIG. 1A will be described with reference to
`FIGS. 2A to 2E below.
`
`First, a conductive film is formed over the substrate
`[0057]
`100 having an insulating surface and the conductive film is
`selectively etched into the gate electrode 148 (see FIG. 2A).
`Note that the entire surface of the substrate 100 is not neces-
`
`sarily an insulating surface and part may be conductive.
`[0058] Although there is no particular limitation on a sub-
`strate which can be used as the substrate 100, it is necessary
`that the substrate have at least heat resistance high enough to
`withstand heat treatment performed later. For example, a
`substrate such as a glass substrate, a ceramic substrate, a
`quartz substrate, or a sapphire substrate can be used. Altema-
`tively, a single crystal semiconductor substrate or a polycrys-
`talline semiconductor substrate made of silicon, silicon car-
`bide, or the like, a compound semiconductor substrate made
`of silicon germanium or the like, an SOI substrate, or the like
`can be used as long as the substrate has an insulating surface.
`A semiconductor element may be provided over the substrate.
`Further, a base film may be provided over the substrate 100.
`[0059] The conductive film to be the gate electrode 148 can
`be formed by a PVD method typified by a sputtering method
`or a CVD method such as a plasma CVD method. As a
`material ofthe conductive film to be the gate electrode 148, an
`element selected from aluminum, chromium, copper, tanta-
`lum, titanium, molybdenum, and tungsten, a nitride thereof,
`an alloy containing any of the above elements as its compo-
`nent, or the like can be used. One or more materials selected
`from manganese, magnesium, zirconium, and beryllium may
`be used. Alternatively, aluminum combined with one or more
`of elements selected from titanium,
`tantalum,
`tungsten,
`molybdenum, chromium, neodymium, and scandium may be
`used. Further alternatively, a conductive metal oxide such as
`indium oxide (InZO3), tin oxide (SnOz), zinc oxide (ZnO), an
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`US 2011/0193081A1
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`Aug. 11,2011
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`alloy of indium oxide and tin oxide (In20378n02, which is
`abbreviated to ITO in some cases), an alloy of indium oxide
`and zinc oxide (In2037ZnO), or any of these metal oxide
`materials in which silicon or silicon oxide is included can be
`used.
`
`[0060] Note that when the work function of the material of
`the gate electrode 148 is substantially the same as or smaller
`than the electron affinity of the oxide semiconductor layer
`14411, the threshold voltage of the transistor might shift in the
`negative direction in miniaturization of the transistor.
`Accordingly, it is preferable that a material which has the
`work function larger than the electron affinity of the oxide
`semiconductor layer 144a be used for the gate electrode 148.
`As such materials, for example, tungsten, platinum, gold,
`silicon to which p-type conductivity is imparted, or the like is
`given.
`Further, the gate electrode 148 may have a single-
`[0061]
`layer structure or a stacked-layer structure of two or more
`layers. The thickness ofthe gate electrode 148 is 10 nm to 400
`nm, preferably 100 nm to 200 nm.
`[0062] Here, ultraviolet light, a KrF laser beam, or an ArF
`laser beam is preferably used for light exposure for forming a
`mask used in etching to form the gate electrode 148. Particu-
`larly for light exposure in the case where the processing
`dimension is less than 25 nm, light exposure for forming a
`mask is preferably performed with extreme ultraviolet light
`whose wavelength is several nanometers to several tens of
`nanometers, which is extremely short. In light exposure using
`extreme ultraviolet light, resolution is high and depth offocus
`is large, which are suitable for miniaturization.
`[0063]
`In etching the conductive film, end portions of the
`gate electrode 148 are preferably tapered as illustrated in FIG.
`2A. This is for the prevention of disconnection of the gate
`insulating layer 146 or the like when the gate insulating layer
`146 or the like is formed over the gate electrode 148 in a later
`step.
`[0064] Next, the gate insulating layer 146 is formed so as to
`cover the gate electrode 148 (see FIG. 2B).
`[0065] The gate insulating layer 146 can be formed by a
`CVD method, a sputtering method, or the like. The gate
`insulating layer 146 is preferably formed so as to include
`silicon oxide, silicon nitride, silicon oxynitride, aluminum
`oxide,
`tantalum oxide, hafnium oxide, yttrium oxide,
`hafnium silicate (HfSiXOy (x>0, y>0)), hafnium silicate (Hf-
`SiXOy (x>0, y>0)) to which nitrogen is added, hafnium alu-
`minate (HfAlXOy (x>0, y>0)) to which nitrogen is added, or
`the like. Note that the gate insulating layer 146 may have a
`single-layer structure or a layered structure. There is no par-
`ticular limitation on the thickness; however, in the case where
`a semiconductor device is miniaturized, the thickness is pref-
`erably small for ensuring operation of the transistor. For
`example, in the case where silicon oxide is used, the thickness
`can be set to greater than or equal to 1 nm and less than or
`equal to 100 nm, preferably greater than or equal to 10 nm and
`less than or equal to 50 nm.
`[0066] As described above, when the gate insulating layer
`146 is thin, there is a problem of gate leakage due to a
`tunneling effect or the like. In order to solve the problem of
`gate leakage, it is preferable that the gate insulating layer 146
`be formed using a high dielectric constant (high-k) material
`such as hafnium oxide,
`tantalum oxide, yttrium oxide,
`hafnium silicate (HfSiXOy (x>0, y>0)), hafnium silicate (Hf-
`SiXOy (x>0, y>0)) to which nitrogen is added, or hafnium
`aluminate (HfAlXOy (x>0, y>0)) to which nitrogen is added.
`
`With the use of a material with a high dielectric constant
`(high-k) material for the gate insulating layer 146, the thick-
`ness of the gate insulating layer 146 can be large so as to
`ensure electrical characteristics and prevent gate leakage.
`Note that a stacked structure of a film including a high dielec-
`tric constant (high-k) material and a film including any of
`silicon oxide, silicon nitride, silicon oxynitride, silicon
`nitride oxide, aluminum oxide, and the like may also be
`employed.
`[0067] Next, an oxide semiconductor layer 144 is formed
`over the gate insulating layer 146 by a sputtering method and
`an insulating layer 150 is formed over the oxide semiconduc-
`tor layer 144 (see FIG. 2C).
`[0068] As the oxide semiconductor layer 144, an Inisni
`Ga7anO-based oxide semiconductor layer which is a
`four-component metal oxide; an IngGa7anO-based
`oxide semiconductor layer, an In7$n7anO-based oxide
`semiconductor layer, an IniA17ZniO-based oxide semi-
`conductor layer, a Sn4Ga7anO-based oxide semicon-
`ductor layer, an A14Ga7anO-based oxide semiconduc-
`tor layer, or a SniA17ZniO-based oxide semiconductor
`layer which are three-component metal oxide; an In7Zni
`O-based oxide semiconductor layer, a Sn7anO-based
`oxide semiconductor layer, anA17ZniO-based oxide semi-
`conductor layer, a ZnngiO-based oxide semiconductor
`layer, a SnnggO-based oxide semiconductor layer, or an
`InnggO-based oxide semiconductor layer which are
`two-component metal oxide; or an IniO-based oxide semi-
`conductor layer, a SniO-based oxide semiconductor layer
`or a anO-based oxide semiconductor layer which are
`single-component metal oxide can be used.
`[0069]
`In particular, an IniGa7ZniO-based oxide
`semiconductor material has sufficiently high resistance when
`there is no electric field and thus off-state current can be
`
`sufficiently reduced. In addition, with high field-effect mobil-
`ity, the IngGa7anO-based oxide semiconductor mate-
`rial is suitable for a material used in a semiconductor device.
`
`[0070] As a typical example of the IngGa7anO-based
`oxide semiconductor material, one represented by InGaO3
`(ZnO)m (m>0) is given. Further, there is an oxide semicon-
`ductor material represented by InMO3 (ZnO)m (m>0) using M
`instead of Ga. Here, M denotes one or more metal elements
`selected from gallium (Ga), aluminum (Al), iron (Fe), nickel
`(Ni), manganese (Mn), cobalt (Co), and the like. For example,
`M may be Ga, Ga andAl, Ga and Fe, Ga and Ni, Ga and Mn,
`Ga and Co, or the like. Note that the above-described com-
`positions are derived from the crystal structures that the oxide
`semiconductor material can have and are mere examples.
`[0071] As a target for forming the oxide semiconductor
`layer 144 by a sputtering method, a target having a composi-
`tion ratio of In:Ga:Zn:1:x:y (x is greater than or equal to 0,
`and y is greater than or equal to 0.5 and less than or equal to
`5) is preferable. For example, a metal oxide target having a
`composition ratio of In:Ga:Zn:1:1:1 [atomic ratio] (x:1,
`y:1) (i.e., In203zGaZO32ZnO:1:1:2 [molar ratio]) can be
`used. Alternatively, a metal oxide target having a composition
`ratio of In:Ga:Zn:1:1:0.5 [atomic ratio] (x:1, y:0.5) (i.e.,
`In203zGa2032ZnO:l : 1:1 [molar ratio]); a metal oxide target
`having a composition ratio of In:Ga:Zn:1:1:2 [atomic ratio]
`(x:1, y:2) (i.e., In203zGaZO32ZnO:1:1:4 [molar ratio]); or a
`metal oxide target having a composition ratio of In:Ga:Zn:l :
`0:1 [atomic ratio] (x:0, y:1) (i.e., In2032ZnO:l :2 [molar
`ratio]) can be used.
`
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`US 2011/0193081A1
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`In this embodiment, the oxide semiconductor layer
`[0072]
`144 having an amorphous structure is formed by a sput