UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE No. IPR2018-01362
`
`U.S. PATENT NO. 8,492,840 B2
`
`_____________________________
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`_____________________________
`
`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
`
`_____________________________
`
`
`BLUEHOUSE GLOBAL LTD.
`Petitioner
`
`v.
`
`
`SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
`Patent Owner
`
`
`
`
`_____________________________
`
`
`CASE No. IPR2018-01362
`
`U.S. PATENT NO. 8,492,840 B2
`
`_____________________________
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`
`I.
`
`Table of Contents
`
`INTRODUCTION………………………………………………………….1
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`II. MANDATORY NOTICES (37 C.F.R. § 42.8)…………………….............1
`
`
`
`
`
`
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`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))…………...............1
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))…………………….……...1
`
`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))………………….2
`
`D. Service Information (37 C.F.R. § 42.8(b)(4))…………………...……2
`
`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))………………..…..3
`
`IV.
`
`V.
`
`
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`
`
`IDENTIFICATION OF CHALLENGES…………………….……..........3
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`BACKGROUND……………………………………………………………4
`
`A.
`
`B.
`
`C.
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`Technology……………………………………………………...........4
`
`The ‘840 Patent………………………………………………………6
`
`Prosecution History………………………………………………….7
`
`VI. PERSON OF ORDINARY SKILL IN THE ART………………………..8
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`VII. CLAIM CONSTRUCTION……………………………………………….9
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`VIII. IDENTIFICATION OF HOW EACH CHALLENGED
`
`CLAIM OF THE ’840 PATENT IS UNPATENTABLE…...………….11
`
`
`
`
`
`A. Challenge #1: Claims 1, 4, 14, 16 and 19 are
`
`anticipated under pre-AIA 35 U.S.C. § 102(b)
`
`by Toyota……………………………………………………..……..11
`
`
`
`ii
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`1.
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`2.
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`3.
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`4.
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`5.
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`Claim 1……………………………………………………….14
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`Claim 4………………………………………………….........29
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`Claim 14…………………………………………………. …..30
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`Claim 16…………………………………………………. …..38
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`Claim 19…………………………………………………. …..39
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`B. Challenge #2: Claims 2 and 17 are obvious under
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`
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`pre-AIA 35 U.S.C. § 103(a) over Toyota in view of
`
`Chung……………..………………………………………………...40
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`Claim 2………………….…………………………………....41
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`1.
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`IX. CONCLUSION…………………………………………………………..56
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`
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`2.
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`Claim 17……………………………………………………...43
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`C. Challenge #3: Claims 4 and 19 are obvious under
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`pre-AIA 35 U.S.C. § 103(a) over Toyota in view of
`
`Miyazaki……………………………………………………………..45
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`
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`
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`1.
`
`2.
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`Claim 4…………………………………..…………………...46
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`Claim 19……………………………………………………...49
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`D. Challenge #3: Claims 4 and 19 are obvious under
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`pre-AIA 35 U.S.C. § 103(a) over Toyota in view of
`
`Akimoto…………………………………………….........................52
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`1.
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`2.
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`Claim 4……………………………………………………...53
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`Claim 19…………………………………………………….54
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`iii
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`
`
`List of Exhibits
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`
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`Ex. 1001 United States Letters Patent No. 8,492,840 B2
`
`Prosecution history of U.S. Patent No. 8,492,840 B2 (Excluding
`
`foreign prior art references).
`
`Ex. 1002
`
`
`Ex. 1003 Declaration of Richard A. Flasck
`
`Ex. 1004 United States Patent Application Publication No. 2008/0299693 A1
`
`
`(“Toyota”)
`
`Ex. 1005 United States Patent Application Publication No. 2005/0173752 A1
`
`
` (“Chung”)
`
`Ex. 1006 United States Letters Patent No. 6,784,453 (“Miyazaki”)
`
`Ex. 1007 United States Patent Application Publication No. 2007/0072439 A1
`
`
` (“Akimoto”)
`
`
`
`iv
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`
`
`I.
`
`
`
`INTRODUCTION
`
`BlueHouse Global Ltd. (“Petitioner”) hereby petitions for inter partes
`
`review of claims 1, 2, 4, 14, 16, 17 and 19 (the “challenged claims”) of U.S. Patent
`
`No. 8,492,840 (“the ‘840 Patent”) (Ex. 1001) under 35 U.S.C. §§ 311–319 and 37
`
`C.F.R. § 42. According to the assignment information on the front of the ‘840
`
`Patent, and the records of the United States Patent & Trademark Office (the
`
`“USPTO”), the ‘840 Patent is assigned to, and therefore owned by, Semiconductor
`
`Energy Laboratory Co., Ltd. (the “Patent Owner”). For the reasons provided in
`
`detail below, the challenged claims should be found unpatentable and canceled.
`
`
`
`II. MANDATORY NOTICES (37 C.F.R. § 42.8)
`
`
`
`
`
`A. Real Parties-In-Interest (37 C.F.R. § 42.8(b)(1))
`
`The real parties-in-interest in this matter are Petitioner BlueHouse Global
`
`Ltd. and its parent company, Caesar Global Fund.
`
`
`
`
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`
`As of the filing date of this Petition, Petitioner is unaware of any matters
`
`involving the ‘840 Patent pending in any United States court or administrative
`
`agency
`
`
`
`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`
`
`
`Lead Counsel:
`
`Ryan O. White (USPTO Reg. No. 45,541)
`
`TAFT, STETTINIUS & HOLLISTER LLP
`
`One Indiana Square, Suite 3500
`
`
`Indianapolis, IN 46204
`
`
`
`
`Tel: (317) 713-3455
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`Fax: (317) 713-3699
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`Email: rwhite@taftlaw.com
`
`
`
`Backup Counsel:
`
`
`
`
`
`
`Roshan P Shrestha (No. 71,277)
`TAFT, STETTINIUS & HOLLISTER LLP
`111 East Wacker Dr. Suite 2800
`Chicago, IL 60601
`Tel: (312) 527-4000
`Fax: (312) 966-8573
`Email: rshrestha@taftlaw.com
`
`
`Philip R. Bautista (pro hac vice
`authorization requested)
`TAFT, STETTINIUS & HOLLISTER LLP
`200 Public Square Suite 3500
`Cleveland, OH 44114-2302
`Tel: (216) 706-3957
`Fax: (216) 241-3707
`Email: pbautista@taftlaw.com
`
`
`Petitioner hereby requests authorization to file a motion under 37 C.F.R. § 42.10(c)
`
`for Backup Counsel Philip R. Bautista to appear pro hac vice, as Mr. Bautista is an
`
`experienced litigating attorney and has an established familiarity with this subject
`
`matter at issue in this proceeding. Petitioner intends to file such a motion once
`
`authorization is granted.
`
`D.
`
`Service Information (37 C.F.R. § 42.8(b)(4))
`
`
`
`Please address all correspondence to Lead Counsel at the mailing address
`
`shown above. Petitioner also consents to electronic service by email.
`
`
`
`2
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`
`
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`III. GROUNDS FOR STANDING (37 C.F.R. § 42.104(a))
`
`
`
`Petitioner hereby certifies that: (1) the ’840 'Patent issued on July 23, 2013
`
`and so is eligible for inter partes review; (2) Petitioner has not been served with a
`
`complaint alleging infringement of any of the claims of the ‘840 patent and so is
`
`therefore not barred or estopped from requesting inter partes review of the ‘840
`
`Patent on the grounds identified herein; and (3) Petitioner has not filed a complaint
`
`challenging the validity of the ‘840 Patent. This Petition is being filed in
`
`accordance with 37 C.F.R. § 42.106(a).
`
`
`
`IV.
`
`IDENTIFICATION OF CHALLENGES
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis thereof, and the supporting evidence, institute a trial for Inter Partes
`
`Review of claims 1, 2, 4, 14, 16, 17 and 19 of the ‘840 Patent, and cancel those
`
`claims as invalid under 35 U.S.C. § 102 or 35 U.S.C. § 103. More specifically,
`
`Petitioner requests cancellation of claims 1, 2, 4, 14, 16, 17 and 19 of the ‘840
`
`Patent on the following grounds:
`
`
`
`Challenge #1: Claims 1, 4, 14, 16 and 19 are anticipated under pre-AIA 35
`
`U.S.C. § 102(b) by United States Patent Application Publication No.
`
`2008/0299693 A1 to Toyota et al. (“Toyota”; Ex. 1004). Toyota was published on
`
`
`
`3
`
`
`
`
`December 4, 2008 and is prior art to the ‘840 Patent under pre-AIA 35 U.S.C. §
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`102(b).
`
`
`
`Challenge #2: Claims 2 and 17 are obvious under pre-AIA 35 U.S.C.
`
`103(a) over Toyota in view of United States Patent Application Publication No.
`
`2005/0173752 A1 to Chung et al. (“Chung”; Ex. 1005). Chung was published on
`
`August 11, 2005 and is prior art to the ‘840 Patent under pre-AIA 35 U.S.C. §
`
`102(b).
`
`
`
`Challenge #3: Claims 4 and 19 are obvious under pre-AIA 35 U.S.C.
`
`103(a) over Toyota in view of United States Letters Patent No. 6,784,453 to
`
`Miyazaki et al. (“Miyazaki”; Ex. 1006). Miyazaki issued on August 31, 2004 and
`
`is prior art to the ‘840 Patent under pre-AIA 35 U.S.C. § 102(b).
`
`
`
`Challenge #4: Claims 4 and 19 are obvious under pre-AIA 35 U.S.C.
`
`103(a) over Toyota in view of United States Patent Publication No. 2007/0072439
`
`to Akimoto et al. (“Akimoto”; Ex. 1007). Akimoto was published on March 29,
`
`2007 and is prior art to the ‘840 Patent under pre-AIA 35 U.S.C. § 102(b).
`
`
`
`V.
`
`BACKGROUND
`
`
`
`
`
`A.
`
`Technology
`
`Semiconductor devices are electronic components that exploit the electronic
`
`properties of semiconductor materials, such as silicon. Ex. 1003 at ¶ 21.
`
`
`
`4
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`
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`Semiconductor materials are useful because their behavior can be easily
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`manipulated by the addition of impurities, known as “doping.” Id. Current
`
`conduction in a semiconductor occurs via mobile or “free” electrons and holes,
`
`collectively known as “charge carriers.” Id. Doping a semiconductor such as
`
`silicon with a small proportion of an atomic impurity, such as phosphorus, greatly
`
`increases the number of free electrons or holes within the semiconductor (a doped
`
`semiconductor containing excess holes is called “p-type”; one containing excess
`
`free electrons is known as “n-type”). Id.
`
`
`
`A thin film transistor, or TFT, is an example of semiconductor device. TFTs
`
`can be used as simple ON/OFF switches in a wide variety of electrical devices,
`
`such as active-matrix LCD displays. Id. at ¶ 22. Basically, a TFT consists of a
`
`semiconductor and three electrodes: (i) the gate electrode; (ii) the source electrode;
`
`and (iii) the drain electrode. Id. The gate electrode must be insulated from the
`
`semiconductor by a dielectric layer (or gate insulation layer), while the drain
`
`electrode and source electrode must both directly contact the semiconductor. Id.
`
`Because of this, TFTs generally have one of the following configurations:
`
`
`
`5
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`where “coplanar” in the drawings above refers to the gate electrode being on the
`
`same side of the semiconductor as the source and drain electrode; “staggered”
`
`refers to the gate electrode being on the opposite side of the semiconductor; and
`
`“top” and “bottom” refer to the location of the gate electrode relative to the other
`
`layers. Id.
`
`
`
`
`
`
`
`B.
`
`The ‘840 Patent
`
`According to the specification, the ‘840 Patent relates to semiconductor
`
`devices. Ex. 1001 at 1:7-9. These semiconductor devices include general elements
`
`and devices which function by utilizing semiconductor characteristics. Ex. 1001 at
`
`1:7-9.
`
`One specifically disclosed embodiment is
`
`6
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`
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`
`
`a semiconductor device which includes an oxide semiconductor layer,
`a source electrode and a drain electrode in contact with the oxide
`semiconductor layer, a gate electrode overlapping with the oxide
`semiconductor layer, and a gate insulating layer provided between the
`oxide semiconductor layer and the gate electrode, in which the source
`electrode and the drain electrode each include a first conductive layer,
`and a second conductive layer having a region which extends in a
`channel length direction from an end portion of the first conductive
`layer.
`
`Ex. 1001 at 2:54-64. The specification further discloses that “[i]n the above
`
`semiconductor device, each of the first conductive layer and the second conductive
`
`layer preferably has a tapered shape. Ex. 1001 at 2:65-67.
`
`
`
`A second specifically disclosed embodiment is
`
`a semiconductor device which includes an oxide semiconductor layer,
`a source electrode and a drain electrode in contact with the oxide
`semiconductor layer, a gate electrode overlapping with the oxide
`semiconductor layer, and a gate insulating layer provided between the
`oxide semiconductor layer and the gate electrode, in which the source
`electrode and the drain electrode each include a first conductive layer
`and a second conductive layer having a higher resistance than the first
`conductive layer, where the second conductive layer is in contact with
`the oxide semiconductor layer.
`
`Ex. 1001 at 3:4-15. According to the specification of the ‘840 Patent, “the second
`
`conductive layer is preferably a nitride of a metal.” Ex. 1001 at 3:28-29.
`
`
`
`With respect to the conductive layers, the specification discloses that “[a]s
`
`the material for the second conductive film 145, a material having higher resistance
`
`than the first conductive layers 142a and 142b is preferably used.” Ex. 1001 at
`
`8:44-46. The specification further discloses that
`
`
`
`7
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`
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`
`
`As a conductive material used for the second conductive film 145, for
`example, a metal nitride such as titanium nitride, tungsten nitride,
`tantalum nitride, or molybdenum nitride can be preferably used. The
`second conductive film 145 serves one part of the source electrode or
`the drain electrode and is in contact with the oxide semiconductor
`layer; thus, a material which does not cause a chemical reaction by
`contact with the oxide semiconductor layer is preferably used. The
`above mentioned metal nitride is preferable in this regard.
`
`Ex. 1001 at 8:52-61.
`
`
`
`
`
`C.
`
`Prosecution History
`
`The prosecution history of the ‘840 Patent (Ex. 1002) is relatively brief, with
`
`the substantive prosecution consisting of only a single Office Action on the merits
`
`and a response by the applicant, without any amendment to the claims, which was
`
`followed by a Notice of Allowance. Ex. 1002 at 15-22, 29-32, 36-43.
`
`
`
`None of the references relied upon herein was cited or considered during the
`
`prosecution of the ‘840 Patent. Ex. 1003 at ¶ 33.
`
`
`
`
`
`8
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`
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`VI. PERSON OF ORDINARY SKILL IN THE ART
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`
`
`A United States patent is to be read and understood from the perspective of a
`
`person of ordinary skill in the relevant art (technical field) at the time the invention
`
`was made. Here, the relevant date is January 22, 2010, i.e. when the inventors
`
`named on the ‘840 Patent filed the original Japanese patent application to the
`
`subject matter now claimed in the ‘840 Patent and to which priority is claimed.
`
`
`
`A person of ordinary skill in the art is a hypothetical person presumed to
`
`know the relevant prior art. See, e.g., Gnosis S.p.A. v. South Alabama Med. Sci.
`
`Found., IPR2013-00116, Final Written Decision (Paper 68) at 9. Such a person is
`
`of ordinary creativity, not merely an automaton, and is capable of combining the
`
`teachings of the prior art. See id., citing KSR Int’l Co. v. Teleflex Inc., 550 U.S.
`
`398, 420-21 (2007). The factors that may be used to determine the level of skill of
`
`a person of ordinary skill in the art may include the education level of those
`
`working in the field, the sophistication of the technology, the types of problems
`
`encountered in the art, prior art solutions to those problems and the speed at which
`
`innovations in the art are made and implemented.
`
`
`
`In this case, the ‘840 Patent is directed to improving the process of
`
`fabricating semiconductor devices, such as the thin film transistors (“TFTs”) found
`
`in many display devices. Petitioner therefore submits that a person of ordinary
`
`skill should have some at least some familiarity with the practical aspects of
`
`
`
`9
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`
`
`
`fabricating TFTs. Ex. 1003 at ¶ 24. Accordingly, Petitioner submits that a person
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`of ordinary skill in the art of the ‘840 Patent as of January 22, 2010, would have
`
`had at least a bachelor of science or engineering degree in electrical engineering,
`
`semiconductor technology, physics, or a related field, and either an advanced
`
`degree (such as a masters) or an equivalent amount of work experience, i.e. 2-3
`
`years, in an area relating to semiconductor design and/or fabrication, liquid crystal
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`display (“LCD”) design or fabrication, electrical engineering, or a related technical
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`field. Id.
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`
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`VII. CLAIM CONSTRUCTION
`
`
`
`The following constructions of certain claim terms are proposed by
`
`Petitioner using the “broadest reasonable interpretation” standard currently
`
`applicable for inter partes review. See 37 C.F.R. § 42.100(b); Cuozzo Speed
`
`Techs. v. Lee, 579 U.S. ___, ___, 136 S. Ct. 2131, 2134 (2016). If, however, the
`
`“plain and ordinary meaning” standard was applicable, Petitioner would still
`
`propose the same constructions for the same reasons as provided below.
`
`
`
`
`
`1.
`
`“semiconductor device” (claims 1, 2, 4, 14, 16, 17 and 19)
`
`This term appears in the preamble of all of the challenged claims. The
`
`specification of the ‘840 Patent states that “semiconductor devices herein refer to
`
`general devices which function by utilizing semiconductor characteristics.” Ex.
`
`
`
`10
`
`
`
`
`1001 at 1:7-9. Petitioner therefore submits that the claim term semiconductor
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`device should be construed to mean “a device that functions by utilizing
`
`semiconductor characteristics.” Ex. 1003 at ¶ 35.
`
`
`
`
`
`2.
`
` “in contact with” (claims 1, 2, 4, 14, 16, 17 and 19)
`
`This term appears in all of the challenged claims in the limitations regarding
`
`the source electrode, drain electrode and semiconductor oxide layer elements of
`
`the claimed semiconductor device. The specification of the ‘840 Patent does not
`
`define this term, but does include the following passage:
`
`As a conductive material used for the second conductive film 145, for
`example, a metal nitride such as titanium nitride, tungsten nitride,
`tantalum nitride, or molybdenum nitride can be preferably used. The
`second conductive film 145 serves one part of the source electrode or
`the drain electrode and is in contact with the oxide semiconductor
`layer; thus, a material which does not cause a chemical reaction by
`contact with the oxide semiconductor layer is preferably used.
`
`Ex. 1001 at 8:52-60. As a general principal, a chemical reaction between a
`
`conductive material and a semiconductor layer, such as ohmic contact degradation,
`
`occurs only if those two layers are actually physically touching one another. Ex.
`
`1003 at ¶ 36. Petitioner therefore submits that the claim term in contact with
`
`should be construed to mean “physically touching.” Id.
`
`
`
`
`
`3.
`
`“opposed to” (claims 1, 2, 4, 14, 16, 17 and 19)
`
`This term appears in all of the challenged claims in the limitations regarding
`
`the end portion of the first conductive layer and the end portion of the third
`
`
`
`11
`
`
`
`
`conductive layer elements. This term does not appear anywhere in the
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`specification of the ‘840 Patent, but, based on the depiction of the end portion of
`
`the first conductive layer and the end portion of the third conductive layer elements
`
`in at least FIGS. 1A-1D, 2A-2F and 3A-3F (Ex. 1001), Petitioner submits that the
`
`claim term opposed to should be construed to mean “located directly across from.”
`
`Ex. 1003 at ¶ 37.
`
`
`
`VIII. IDENTIFICATION OF HOW EACH CHALLENGED CLAIM OF
`
`THE ’840 PATENT IS UNPAENTABLE
`
`
`
`As discussed in detail below, the challenged claims are unpatentable over
`
`the prior art.
`
`
`
`
`
`
`A. Challenge #1: Claims 1, 4, 14, 16 and 19 are anticipated
`under pre-AIA 35 U.S.C. § 102(b) by Toyota
`
`Toyota (Ex. 1004) was published on December 4, 2008. Since the
`
`application from which the ‘840 Patent issued was first filed in the United States
`
`on January 18, 2011, Toyota qualifies as prior art against the ‘840 Patent under
`
`pre-AIA 35 U.S.C. § 102(b).
`
`
`
`“‘Anticipation’ in patent terms means that the claimed invention is not new;
`
`that is, the invention as claimed was already known.” Ericsson Inc. v. Intellectual
`
`Ventures I LLC, 890 F.3d 1336, 1338 (Fed. Cir. 2018). A finding of anticipation
`
`requires that every limitation of the claim is present in a single prior art reference.
`
`
`
`12
`
`
`
`
`See, e.g., Blue Calypso, LLC v. Groupon, Inc., 815 F.3d 1331, 1341 (Fed. Cir.
`
`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
`
`2016); In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009).
`
`
`
`Toyota anticipates each of claims 1, 4, 14, 16 and 19 of the ‘840 Patent.
`
`That is, “each and every element” of 1, 4, 14, 16 and 19 of the ‘840 Patent is
`
`identically disclosed by Toyota, “arranged or combined in the same way as in the
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`claim.” Id. at 1346 (citing Blue Calypso, 815 F.3d at 1341). Specifically, as
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`described in detail below, in at least FIG. 3B and the accompanying text in the
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`specification, Toyota discloses a thin film transistor (for use in, e.g., a display
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`device) having all of the same layers that are recited in each of claims 1, 4, 14, 16
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`and 19 and those layers are arranged in the same order as required by those claims.
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`An annotated (colorized and labeled) version of Toyota’s FIG. 3B, showing
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`a top gate transistor, is shown below:
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`where:
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`GT is the gate electrode (Ex. 1004 at ¶¶ 135-136);
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`DT(U) and DT(D) are each conductive layers that together form the drain
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`electrode (Id.);
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`ST(U) and ST(D) are each conductive layers that together form the source
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`electrode (Id.);
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`GI is the gate insulating layer (Id.); and
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`PAS is the protective coating (Id).
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`The semiconductor layer PS is not labelled in this FIG. Ex. 1003 at ¶ 40.
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`1.
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`Claim 1
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`a.
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`The preamble
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`The preamble of claim 1 recites “[a] semiconductor device comprising . . ..”
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`Ex 1001 at 35:2. To the extent that this preamble is deemed a limitation, this
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`limitation is expressly disclosed by Toyota. Ex 1003 at ¶¶ 41-45.
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`
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`The ‘840 Patent specifically identifies transistors (and, more particularly, top
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`gate transistors) as examples of a semiconductor device within the scope of claim
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`1. Ex 1003 at ¶ 43. For example, the specification of the ‘840 Patent discloses that
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`“[i]n this [first] embodiment, an example of a structure and a manufacturing
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`process of a semiconductor device according to an embodiment of the disclosed
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`invention will be described with reference to FIGS. 1A to 1D, FIGS. 2A to 2F, and
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`FIGS. 3A to 3F. . . . In FIGS. 1A to 1D, as examples of semiconductor devices,
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`14
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`cross-sectional structures of transistors are illustrated. In FIGS. 1A to 1D,
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`top-gate transistors are illustrated as transistors according to one embodiment
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`of the disclosed invention.” Ex. 1001 at 5:47-56 (emphasis added).
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`Toyota also discloses thin-film transistors (“TFTs”) and, more specifically,
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`top gate TFTs. Ex 1003 at ¶ 44. Toyota teaches that “FIGS. 3A to 3C are block
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`diagrams showing one embodiment of pixels of the display device to which the
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`manufacturing method for a display device according to the present invention is
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`applied. . .. [T]his pixel includes a so-called top gate type thin film transistor in
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`which a gate electrode is formed on the upper layer of a semiconductor layer.”
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`Ex. 1004 at ¶¶ 59, 61 (emphasis added).
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`Accordingly, to the extent the preamble is limiting, this limitation is
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`identically disclosed by Toyota. Ex 1003 at ¶ 45.
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`b.
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`an oxide semiconductor layer
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`The first element of the semiconductor device of claim 1 of the ‘840 Patent
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`is an oxide semiconductor layer. Ex 1001 at col. 35:3. Toyota identically discloses
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`this element. Ex 1003 at ¶¶ 47-50.
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`Toyota teaches that “[the] pixel includes a so-called top gate type thin film
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`transistor in which a gate electrode is formed on the upper layer of a
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`semiconductor layer.” Ex. 1004 at ¶ 61. Toyota further teaches that “[i]n each of
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`the above-described embodiments, a polysilicon layer is used as the semiconductor
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`layer and further, an amorphous silicon layer or microcrystalline silicon layer may
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`be used. Further, a polysilicon layer formed directly using a catalytic chemical
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`vapor phase growth method or reactive thermal CVD method may be used.
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`Additionally, an oxide semiconductor layer may be used.” Ex. 1004 at ¶ 181
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`(emphasis added).
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`Toyota’s FIG. 3B, with the semiconductor layer colorized and labeled for
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`clarity, is shown below:
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`Toyota therefore identically discloses the oxide semiconductor layer
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`limitation of claim 1. Ex 1003 at ¶ 50.
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`c.
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`a source electrode . . .
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`The next element of claim 1 is a source electrode in contact with the oxide
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`semiconductor layer comprising: a first conductive layer; and a second conductive
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`16
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`layer. Ex 1001 at 35:4-7. Toyota identically discloses this element, and in the
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`same arrangement as recited in the claim. Ex 1003 at ¶¶ 53-57, 59-61.
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`i.
`a source electrode in contact with the oxide
`semiconductor layer
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`The first feature of the source electrode element is that it is in contact with
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`the oxide semiconductor layer. Ex 1001 at 35:4-5. This feature is disclosed by
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`Toyota. Ex 1003 at ¶¶ 53-57.
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`
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`Toyota discloses a TFT having a two-layer source electrode ST in contact
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`with the semiconductor layer PS (which can be an oxide semiconductor layer). Ex.
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`1004 at ¶¶ 70, 181; Ex 1003 at ¶ 57. More specifically, Toyota teaches that “[t]he
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`source electrode ST is connected to . . . the semiconductor layer PS via the contact
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`hole TH formed through the insulating film[] . . . GI.” Ex. 1004 at ¶ 70.
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`17
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`Toyota’s FIG. 3B, with the two-layer source electrode (ST(U) and ST(D))
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`U.S. Patent No. 8,492,840
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`and the oxide semiconductor layer (PS) colorized and labeled for clarity, is shown
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`below:
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`Because a contact hole has been formed through the insulating film GI (and the
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`layer above it) so that the source electrode ST can be connected to the oxide
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`semiconductor layer PS, the lower layer of the source electrode ST(D) physically
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`touches (is in contact with) the oxide semiconductor layer PS. Ex 1003 at ¶ 56.
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`Toyota therefore identically discloses the source electrode in contact with
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`the oxide semiconductor layer limitation of claim 1. Ex 1003 at ¶ 57.
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`ii.
`a source electrode . . . comprising: a first
`conductive layer; and a second conductive layer
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`The second feature of the source electrode element is that it compris[es] a
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`first conductive layer; and a second conductive layer. Ex 1001 at 35:4-7. This
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`feature is also disclosed by Toyota. Ex 1003 at ¶¶ 59-61.
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`
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`Toyota teaches that the two-layer source electrode (ST) in contact with the
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`oxide semiconductor layer (PS) comprises a first conductive layer (ST(U)) and a
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`second conductive layer (ST(D)) in a stacked arrangement. Ex. 1004 at ¶¶ 72, 74;
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`Ex 1003 at ¶ 59. Toyota teaches that “the source electrode ST has the two-layered
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`structure in which, for example, a conductive layer made of tungsten having a
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`thickness of about 30 nm and a conductive layer made of aluminum having a
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`thickness of about 500 nm are sequentially stacked.” Ex. 1004 at ¶ 72. Toyota
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`also teaches that “the source electrode ST includes a lower source electrode ST(D)
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`and an upper source electrode ST(U).” Ex. 1004 at ¶ 74.
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`19
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`Toyota’s FIG. 3B, with the two layers of the source electrode (ST(U) and
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`ST(D)) colorized and labeled for clarity, is shown below:
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`Toyota therefore identically discloses the source electrode . . . comprising: a
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`first conductive layer; and a second conductive layer limitation of claim 1. Ex
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`1003 at ¶ 61.
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`d.
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`a drain electrode . . .
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`The third element recited in claim 1 of the ‘840 Patent is a drain electrode in
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`contact with the oxide semiconductor layer comprising: a third conductive layer;
`
`and a fourth conductive layer. Ex 1001 at 35:8-11. Toyota identically discloses
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`this element, and in the same arrangement as recited in the claim. Ex 1003 at ¶¶
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`64-67, 69-71.
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`i.
`a drain electrode in contact with the oxide
`semiconductor layer
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`Similar to the source electrode limitation, the first feature of the drain
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`electrode element is that it is in contact with the oxide semiconductor layer. Ex
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`1001 at 35:8-9. This feature is disclosed by Toyota. Ex 1003 at ¶¶ 64-67.
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`Toyota discloses a TFT having a drain electrode in contact with the oxide
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`semiconductor layer. Ex. 1004 at ¶ 69, 181; Ex 1003 at ¶ 64. Referring to FIG.
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`3B, Toyota teaches that “[t]his drain electrode DT is connected to . . . the
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`semiconductor layer PS via a contact hole TH formed through the insulating film[]
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`. . . GI.” Ex. 1004 at ¶ 69.
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`Toyota’s FIG. 3B, with the two-layer drain electrode (DT(U) and DT(D))
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`and the oxide semiconductor layer (PS) colorized and labeled for clarity, is shown
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`below:
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`
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`Because a contact hole has been formed through the insulating film GI (and the
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`additional insulating layer IN above it), the lower layer of the drain electrode
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`DT(D) physically touches (is in contact with) the oxide semiconductor layer PS.
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`Ex. 1003 at ¶ 66.
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`Toyota therefore identically discloses the drain electrode in contact with the
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`oxide semiconductor layer limitation of claim 1. Ex 1003 at ¶ 67.
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`ii.
`a drain electrode . . . comprising: a third
`conductive layer; and a fourth conductive layer.
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`
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`The second feature of the drain electrode element is that it compris[es] a
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`third conductive layer; and a fourth conductive layer. Ex 1001 at 35:8-11. This
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`feature is also disclosed by Toyota. Ex. 1003 at ¶¶ 69-71.
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`
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`Toyota discloses that the two-layer drain electrode in contact with the oxide
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`semiconductor layer comprises a third conductive layer and a fourth conductive
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`layer in a stacked arrangement. Ex. 1004 at ¶¶ 72, 73; Ex 1003 at ¶¶ 69-70.
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`Toyota teaches that “the drain electrode DT has the two-layered structure in which,
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`for example, a conductive layer made of tungsten having a thickness of about 30
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`nm and a conductive layer made of aluminum having a thickness of about 500 nm
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`are sequentially stacked.” Ex. 1004 at ¶ 72; Ex 1003 at ¶ 69. Toyota also teaches
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`that “the drain electrode DT includes a lower drain electrode DT(D) and an upper
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`drain electrode DT(U).” Ex. 1004 at ¶ 73; Ex 1003 at ¶ 69.
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`
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`Toyota’s FIG. 3B, with the two layers of the drain electrode (DT(U) and
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`DT(D)) colorized and labeled for clarity, is shown below:
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`Toyota therefore identically discloses the drain electrode . . . comprising: a
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`third conductive layer; and a fourth conductive layer limitation of claim 1. Ex.
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`1003 at ¶ 71.
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`e.
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`a gate electrode . . .
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`The fourth element of claim 1 is a gate electrode overlapping with the oxide
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`semiconductor layer. Ex. 1001 at 35:12-13. Toyota identically discloses this
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`element, and in the same arrangement as recited in the claim. Ex. 1003 at ¶¶ 73-
`
`75.
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`
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`Toyota discloses a TFT having a gate electrode that overlaps with the oxide
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`semiconductor layer. Ex. 1004 at ¶¶ 72-73, 181; Ex 1003 at ¶ 73. With reference
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`to FIG 3B, Toyota teaches that “[the] gate signal line GL has an extended portion
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`overlapping the channel region CH of the semiconductor layer PS and this
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`extended portion functions as the gate electrode GT of the thin film transistor
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`TFT.” Ex. 1004 at ¶ 67 (emphasis added); Ex 1003 at ¶ 73.
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`23
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`Toyota’s FIG. 3B, with the gate electrode (GT) and the oxide semiconductor
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`Petition for Inter Partes Review
`U.S. Patent No. 8,492,840
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`layer (PS) colorized and labeled for clarity, is shown below:
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`
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`Toyota therefore identically discloses the gate electrode overlapping with
`
`the oxide semiconductor layer limitation of claim 1. Ex 1003 at ¶ 75.
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`f.
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`a gate insulating layer
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