`Petitioner Bluehouse Global Ltd.
`
`Ex. 1005
`EX. 1005
`
`
`
`(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0173752 A1
`
`(43) Pub. Date:
`Aug. 11, 2005
`Chung et al.
`
`US 20050173752A1
`
`(54) OPTIC MASK AND MANUFACTURING
`METHOD OF THIN FILM TRANSISTOR
`ARRAY PANEL USING THE SAME
`
`(76)
`
`Inventors: Ui-Jin Chung, Suwon-si (KR);
`Myung-Koo Kang, Seoul (KR);
`Jae-Bok Lee, Seoul (KR)
`
`Correspondence Address:
`Hae Chan Park
`McGuire Woods LLP
`Suite 1800
`
`1750 Tysons Blvd.
`McLean, VA 22102 (US)
`
`(21) Appl. No.:
`
`11/029,011
`
`(22)
`
`Filed:
`
`Jan. 5, 2005
`
`(30)
`
`Foreign Application Priority Data
`
`Jan. 6, 2004
`Jan. 16, 2004
`
`(KR) .............................. 10-2004-000547
`(KR) .............................. 10-2004-003216
`
`Publication Classification
`
`Int. Cl.7 .................................................. H01L 29/788
`(51)
`(52) U.S.Cl.
`.............................................................. 257/315
`
`(57)
`
`ABSTRACT
`
`An optic mask for crystallizing amorphous silicon comprises
`a first slit region including a plurality of slits regularly
`arranged for defining incident region of laser beam, wherein
`the slits of the first slit region are formed to slope by a
`predetermined angle to the direction of transfer of the optic
`mask in crystallization process, and wherein the slits of the
`first slit region includes a first slit having a first length and
`a second slit having a second length which is longer than the
`first length.
`
`
`
`
`
`110140
`
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`
`152
`'53
`152150A 140
`157
`152
`154152
`
`150
`
`155
`
`
`
`111
`
`
`
`Patent Application Publication Aug. 11, 2005 Sheet 1 0f 27
`
`US 2005/0173752 A1
`
`FIG. 7
`
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`Patent Application Publication Aug. 11, 2005 Sheet 2 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 3 0f 27
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`US 2005/0173752 A1
`
`FIG. 3A
`
`IIIB
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`150
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`Patent Application Publication Aug. 11, 2005 Sheet 4 0f 27
`
`US 2005/0173752 A1
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`140
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`Patent Application Publication Aug. 11, 2005 Sheet 5 0f 27
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`FIG-.4
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`Patent Application Publication Aug. 11, 2005 Sheet 7 0f 27
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`US 2005/0173752 A1
`
`FIG. 6A
`
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`
`Patent Application Publication Aug. 11, 2005 Sheet 8 0f 27
`
`US 2005/0173752 A1
`
`FIG.6B
`
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`Patent Application Publication Aug. 11, 2005 Sheet 9 0f 27
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`A65%
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`Patent Application Publication Aug. 11, 2005 Sheet 10 0f 27
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`US 2005/0173752 A1
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`FIG. 8A
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`Patent Application Publication Aug. 11, 2005 Sheet 11 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 12 0f 27
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`US 2005/0173752 A1
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`FIG. 9A
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`Patent Application Publication Aug. 11, 2005 Sheet 13 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 14 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 15 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 16 0f 27
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`US 2005/0173752 A1
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`FIG. 72A
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`Patent Application Publication Aug. 11, 2005 Sheet 17 0f 27
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`US 2005/0173752 A1
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`Patent Application Publication Aug. 11, 2005 Sheet 18 0f 27
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`US 2005/0173752 A1
`
`FIG.73A
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`Patent Application Publication Aug. 11, 2005 Sheet 19 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 20 0f 27
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`Patent Application Publication Aug. 11, 2005 Sheet 21 0f 27
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`US 2005/0173752 A1
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`FIG. 75A
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`Patent Application Publication Aug. 11, 2005 Sheet 22 0f 27
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`US 2005/0173752 A1
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`Patent Application Publication Aug. 11, 2005 Sheet 23 0f 27
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`US 2005/0173752 A1
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`F1016
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`Patent Application Publication Aug. 11, 2005 Sheet 24 0f 27
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`US 2005/0173752 A1
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`Patent Application Publication Aug. 11, 2005 Sheet 25 0f 27
`
`US 2005/0173752 A1
`
`F1020
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`Patent Application Publication Aug. 11, 2005 Sheet 26 0f 27
`
`US 2005/0173752 A1
`
`FIG.22A
`
`Sequential
`
`lateral solidification
`
`::
`
`50
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`110
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`
`Patent Application Publication Aug. 11, 2005 Sheet 27 0f 27
`
`US 2005/0173752 A1
`
`FIG. 22D
`
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`
`140
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`154 110 155 150
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`
`
`US 2005/0173752 A1
`
`Aug. 11, 2005
`
`OPTIC MASK AND MANUFACTURING METHOD
`OF THIN FILM TRANSISTOR ARRAY PANEL
`USING THE SAME
`
`CROSS REFERENCE
`
`[0001] This application claims the benefit of Korean
`Patent Application No. 10-2004-000547, filed on Jan. 6,
`2004 and Korean Patent Application No. 10-2004-003216,
`filed on Jan. 16, 2004, which is hereby incorporated by
`reference for all purposes as if fully set forth herein.
`
`[0002]
`
`1. Field of the Invention
`
`[0003] The present invention relates to an optic mask for
`crystallizing amorphous silicon into poly crystalline silicon
`and a method for manufacturing a thin film transistor array
`panel using the same.
`
`[0004]
`
`2. Description of the Related Art
`
`[0005] Generally, silicon is divided into amorphous silicon
`and crystalline silicon according to the state of crystal.
`Amorphous silicon is widely used in display having glasses
`whose melting point is low, since amorphous silicon film can
`be fabricated at a low temperature.
`
`[0006] However, the amorphous silicon film has low car-
`rier mobility. It may be unsuitable for applying to a high
`quality driving circuit of display panels. Whereas, since
`polycrystalline silicon has prominent electric field effect
`mobility, high frequency operation, and low leakage current,
`high quality driving circuits require the polycrystalline sili-
`con.
`
`laser annealing (ELA) and chamber
`[0007] Excimer
`annealing are typical methods for producing polycrystalline
`silicon. Recently, sequential lateral solidification (SLS) pro-
`cess is proposed. The SLS technique utilizes a phenomenon
`that the silicon grains grow laterally to the boundary of a
`liquid region and a solid region.
`
`SUMMARY OF THE INVENTION
`
`[0008] The present invention provides an optic mask for
`crystallizing silicon that
`is enhancing the uniformity of
`characteristics of thin film transistors, and a method of
`manufacturing a thin film transistor array panel using the
`same.
`
`[0009] According to one aspect of the present invention,
`an optic mask for crystallizing amorphous silicon comprises
`a first slit region including a plurality of slits regularly
`arranged for defining incident region of laser beam, wherein
`the slits of the first slit region are inclined by a predeter-
`mined angle to the direction of transfer of the optic mask in
`crystallization process, and wherein the slits of the first slit
`region includes a first slit having a first length and a second
`slit having a second length which is longer than the first
`length.
`
`the second length is
`is preferable that
`it
`[0010] Here,
`longer than the first length by the margin of misalignment of
`the optic mask.
`
`[0011] The optic mask may further comprises a second slit
`region including a plurality of slits regularly arranged for
`defining incident region of laser beam, wherein the slits of
`the first silt region are arranged to deviate from the slits of
`the second slit region.
`
`[0012] According to another aspect of the present inven-
`tion, a method of manufacturing a thin film transistor
`comprises forming an amorphous silicon layer on an insu-
`lating substrate, forming a polycrystalline silicon layer by
`irradiating a laser beam to the amorphous silicon layer
`through an optic mask that includes a first slit of a first length
`and a second slit of a second length and translating the laser
`beam and the optic mask, forming a semiconductor layer by
`patterning the poly silicon layer, forming a gate insulating
`layer over the semiconductor layer, forming a gate line on
`the gate insulating layer to overlap the semiconductor layer
`partially, forming a source region and a drain region by
`doping conductive impurities of high concentration on pre-
`determined regions of the semiconductor layer, forming a
`first interlayer insulating layer over the gate line and the
`semiconductor layer, forming a data line including a source
`electrode connected with the source region and forming a
`drain electrode connected with the drain region, forming a
`second interlayer insulating layer on the data line and the
`drain electrode, and forming a pixel electrode on the second
`interlayer insulating layer to be connected with the drain
`electrode.
`
`[0013] According to another aspect of the present inven-
`tion, a method of manufacturing a thin film transistor
`comprises the steps of: forming an amorphous silicon layer
`on an insulating substrate, forming a polycrystalline silicon
`layer by irradiating a laser beam to the amorphous silicon
`layer through an optic mask which includes a first slit of a
`first length and a second slit of a second length and trans-
`lating the laser beam and the optic mask, forming a semi-
`conductor layer by patterning the poly silicon layer, forming
`a gate insulating layer over the semiconductor layer, forming
`a data metal piece and a gate line that has a portion
`overlapping the semiconductor layer,
`forming a source
`region and a drain region by doping conductive impurities of
`high concentration on predetermined regions of the semi-
`conductor layer, forming an interlayer insulating layer over
`the semiconductor layer, and forming a data connection part
`connected with the source region and the data metal piece,
`and a pixel electrode connected with the drain region.
`
`[0014] Here, the manufacturing method can further com-
`prise forming LDD regions in the semiconductor layer by
`doping conductive impurities having a lower concentration
`compared to the source region and the drain region.
`
`[0015] The manufacturing method can further comprise
`forming a blocking layer between the insulating substrate
`and the semiconductor layer.
`
`[0016] At this time, the slits are formed to slope by as
`much as a predetermined angle to the direction of transfer of
`the optic mask.
`
`[0017] The optic mask includes a first slit region and a
`second slit region that individually include the first slit and
`the second slit, and wherein the slits of the first slit region
`and the slit of the second slit region are arranged to deviate
`from each other.
`
`[0018] The present invention provides an optic mask for
`crystallizing amorphous silicon comprises slits that are
`transparent area of laser beam and have curved boundary
`line.
`
`[0019] Here, the slits may have a shape of arc.
`
`
`
`US 2005/0173752 A1
`
`Aug. 11, 2005
`
`[0020] The present invention provides a method of manu-
`facturing a thin film transistor comprising:
`forming an
`amorphous silicon layer on an insulating substrate; forming
`a polycrystalline silicon layer by crystallizing the amor-
`phous silicon layer;
`forming a semiconductor layer by
`patterning the poly silicon layer; forming a gate insulating
`layer on the semiconductor layer; forming a gate electrode
`on the gate insulating layer to overlap the semiconductor
`layer partially; forming a source region and a drain region on
`both sides of the gate electrode to define a channel region
`therebetween; forming a first interlayer insulating layer on
`the gate electrode; forming a source and drain electrodes
`respectively connected to the source region and the drain
`region; forming a second interlayer insulating layer on the
`drain electrode; and forming a pixel electrode on the second
`interlayer insulating layer to be connected with the drain
`electrode, wherein the step of forming a polycrystalline
`silicon layer is performed by a SLS and grain groups formed
`by the SLS have boundaries deviating from the boundary of
`the channel region.
`
`[0021] Here, the SLS may be performed with using an
`optic mask having slits that are transparent area of laser
`beam and have curved boundary line. The slits may have a
`shape of arc. The mask may have two regions having a
`plurality of slits that are arranged in a row and the slits of the
`two regions are arranged to deviate from each other. The
`method may further includes a step of forming LDDs
`disposed between the channel region and the source and
`drain regions.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0022] FIG. 1 is a plan view of a TFT array panel
`according to an embodiment of the present invention.
`
`[0023] FIG. 2 is a cross-sectional view taken along the
`line II-II' of FIG. 1.
`
`[0024] FIG. 3A, FIG. 6A, FIG. 8A, and FIG. 9A are plan
`views showing intermediate steps to manufacture a TFT
`array panel according to an embodiment of the present
`invention.
`
`[0025] FIG. 3B is a cross-sectional view taken along the
`line VIB-VIB' of FIG. 3A.
`
`[0026] FIG. 4 and FIG. 5 are views showing crystalliza-
`tion processes using an optic mask pattern according to the
`present invention.
`
`[0027] FIG. 6B is a cross-sectional view taken along the
`line VIB-VIB' of FIG. 6A.
`
`[0028] FIG. 7 is a cross-sectional view showing a subse-
`quent step of FIG. 6B.
`
`[0029] FIG. 8B is a cross-sectional view taken along the
`line VIIIB-VIIIB' of FIG. 8A.
`
`[0030] FIG. 9B is a cross-sectional view taken along the
`line IXB-IXB' of FIG. 9A.
`
`[0031] FIG. 10 is a plan view of a TFT array panel
`according to another embodiment of the present invention.
`
`[0032] FIG. 11 is a cross-sectional view taken along the
`line XI-XI‘-XI" of FIG. 10.
`
`[0033] FIG. 12A, FIG. 13A, and FIG. 15A are plan views
`showing intermediate steps to manufacture a TFT array
`panel according to another embodiment of the present
`invention.
`
`[0034] FIG. 12B is a cross-sectional view taken along the
`line XIIB-XIIB'-XIIB" of FIG. 12A.
`
`[0035] FIG. 13B is a cross-sectional view taken along the
`line XIIIB-XIIIB'-XIIIB" of FIG. 13A.
`
`[0036] FIG. 14 is a cross-sectional view showing a sub-
`sequent step of FIG. 13B.
`
`[0037] FIG. 15B is a cross-sectional view taken along the
`line XVB-XVB'-XVB" of FIG. 15A.
`
`[0038] FIG. 16 is a view showing laser beam irradiation
`using a mask.
`
`[0039] FIG. 17 plane view of a mask according to an
`embodiment of the present invention.
`
`[0040] FIG. 18 illustrates processes of a sequential lateral
`solidification according to an embodiment of the present
`invention.
`
`[0041] FIG. 19 illustrates crystal grains of polysilicon
`crystallized by a sequential lateral solidification according to
`an embodiment of the present invention.
`
`[0042] FIG. 20 is a cross-sectional view of a polysilicon
`thin film transistor array panel according to an embodiment
`of the present invention.
`
`[0043] FIG. 21 illustrates structure of grain groups in a
`step of manufacturing process of a thin film transistor array
`panel according to an embodiment of the present invention.
`
`[0044] FIGS. 22A to 22E are cross-sectional views illus-
`trating manufacturing process of a polysilicon thin film
`transistor array panel according to an embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`[0045] Preferred embodiments of the present invention
`will now be described hereinafter with reference to the
`
`accompanying drawings, in which preferred embodiments
`of the invention are shown. The present invention may,
`however, be embodied in different forms and should not be
`construed as being limited to the embodiments set forth
`herein. Rather, these embodiments are provided so that this
`disclosure will be thorough and complete, and will fully
`convey the scope of the invention to those skilled in the art.
`
`In the drawings, the thickness of the layers, films,
`[0046]
`and regions are exaggerated for clarity. Like numerals refer
`to like elements throughout. It will be understood that when
`an element such as a layer, film, region, or substrate is
`referred to as being “on” another element, it can be directly
`on the other element or intervening elements may also be
`present.
`
`[0047] Hereinafter, TFT array panels and methods of
`manufacturing the same according to preferred embodi-
`ments of the present
`invention will be described with
`reference to the accompanying drawings.
`
`[0048] Optic masks for crystallization according to the
`preferred embodiments of the present invention include first
`slits having a first length and second slits having a second
`length. This will be described in the description of manu-
`facturing methods of a TFT array panel.
`
`
`
`US 2005/0173752 A1
`
`Aug. 11, 2005
`
`[0049] <Embodiment 1>
`
`[0050] Referring to FIG. 1 and FIG. 2, a blocking layer
`111 made of silicon oxide, etc. is formed on a transparent
`insulating substrate 110. A semiconductor layer 150 is
`formed on the blocking layer 111 and includes a source
`region 153 and a drain region 155 which are doped with
`impurities, and a channel region 154 which is made of
`intrinsic semiconductor and is interposed between the source
`region 153 and the drain region 155. The semiconductor
`layer 150 further comprises lightly doped drain (LDD)
`regions 152 formed between the source region 153 and the
`channel region 154, and between the drain region 155 and
`the channel region 154.
`
`[0051] The LDD regions 152 prevent leakage current and
`a “punch through” phenomenon. The source region 153 and
`the drain region 155 are doped with conductive impurities of
`high concentration, whereas the LDD regions 152 are doped
`with conductive impurities of low concentration.
`
`[0052] The conductive impurities are either P-type or
`N-type. Boron (B) or gallium (Ga) may be used as the P-type
`and phosphorus (P) or arsenic (As) can be used as the
`N-type.
`
`[0053] A gate insulating layer 140 made of silicon nitride
`(SiNx) or silicon oxide (SiOz) is formed on the semicon-
`ductor layer 150. A gate line 121 extending in a transverse
`direction is formed on the gate insulating layer 140. A
`portion of the gate line 121 extends to the semiconductor
`layer 150 and overlaps the channel region 154 to form a gate
`electrode 124. The LDD regions 152 can be overlapped with
`the gate electrode 124.
`
`[0054] Also, a storage electrode line 131 is formed in
`parallel with the gate line 121. The storage electrode line 131
`and the gate line 121 are made of the same material on the
`same layer. A portion of the storage electrode line 131
`overlaps the semiconductor layer 150 to form a storage
`electrode 133. The potion of the semiconductor layer 150
`overlapped with the storage electrode 133 becomes a storage
`electrode region 157. An end of the gate line 121 can be
`formed wider than the rest of the gate line 121 to connect
`with the exterior circuitry (not shown).
`
`[0055] A first interlayer insulating layer 601 is formed on
`the gate insulating layer 140, the gate line 121, and the
`storage electrode line 131. The first interlayer insulating
`layer 601 includes a first contact hole 161 and a second
`contact hole 162 through which the source region 153 and
`the drain region 155 are exposed, respectively.
`
`[0056] A data line 171 is formed on the first interlayer
`insulating layer 601. When a pair of the data lines 171 in
`parallel and a pair of the gate lines 121 in parallel are
`intersected, a pixel region is defined therein. The portion of
`the data line 171 is connected with the source region 153
`through the first contact hole 161 to form a source electrode
`173 of TFT. An end of the data line 171 may be formed
`wider than the rest of the data line 171 to connect with the
`
`exterior circuitry.
`
`[0057] A drain electrode 175 is formed on the same layer
`as the data line 171, having a predetermined distance from
`the source electrode 173. The drain electrode 175 is con-
`
`nected with the drain region 155 through the second contact
`hole 162.
`
`[0058] A second interlayer insulating layer 602 is formed
`on the first interlayer insulating layer 601, the drain elec-
`trode 175, and the data line 171. The second interlayer
`insulating layer 602 includes a third contact hole 163
`through which the drain electrode 175 is exposed.
`
`[0059] A pixel electrode 190 is formed on the second
`interlayer insulating layer 602 and is connected with the
`drain electrode 175 through the third contact hole 163.
`
`[0060] Hereinafter, a method of manufacturing the above-
`mentioned TFT array panel will be described with reference
`to FIG. 3A through 9A, along with the above-referenced
`FIG. 1 and FIG. 2.
`
`[0061] As shown in FIG. 3A and FIG. 3B, a blocking
`layer 111 is formed on a transparent insulating substrate 110.
`The transparent insulating substrate 110 can be made of
`glass, quartz, sapphire, etc. The blocking layer 111 is formed
`by depositing silicon oxide (SiOz) or silicon nitride (SiNx)
`with about 1000A thick. Then, clean the surface to remove
`impurities such as natural oxide layer from the blocking
`layer 111.
`
`[0062] An intrinsic amorphous silicon layer is formed with
`the range of 400A to 1200A thick by a chemical vapor
`deposition (CVD), etc.
`
`[0063] Next, the amorphous silicon layer is crystallized by
`the sequential lateral solidification (SLS) process to form a
`poly crystalline silicon layer. The poly crystalline silicon
`layer is patterned by a photolithography using an optic mask
`to form a semiconductor layer 150.
`
`[0064] The details of the crystallization process are
`described with reference to FIG. 4 and FIG. 5.
`
`[0065] FIG. 4 is a plan view showing arrangement of slits
`in an optic mask according to an embodiment of the present
`invention and FIG. 5 is a plan view showing the transfer
`state of optic masks according to an embodiment of the
`present invention.
`
`To poly-crystallize the amorphous silicon, an optic
`[0066]
`mask having a regular pattern, as shown in FIG. 4,
`is
`arranged on the amorphous silicon layer. The optic mask of
`FIG. 4 includes two regions A and B having the same
`pattern. Each region includes a plurality of slits which are
`arranged in a row and have a regular distance therebetween.
`The slits are passages of laser beams. Here, the slits of the
`regionsA and B are arranged to deviate from each other and
`to slope by a predetermined angle to the transfer direction of
`the optic mask in the crystallization process.
`
`In the poly crystalline silicon TFT, the character-
`[0067]
`istics of the TFT depends on the grain size and the boundary
`position of the grains of the silicon. Because the grain length
`of the silicon grain is similar to or a little less than the
`channel distance of the TFT, when the silicon boundary is
`parallel to the channel direction, some TFT may include one
`silicon grain boundary in the channel, some TFT may
`include two silicon grain boundary in the channel, and some
`TFT may include no silicon grain boundary in the channel.
`In this case, the TFT characteristics may not be uniform
`through the whole display area. If the boundary of the silicon
`grain is inclined at a certain angle to the TFT channel, the
`characteristics of the TFT will be much more uniform
`
`through the whole display area.
`
`
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`Aug. 11, 2005
`
`[0068] To make the silicon grain boundary to be inclined
`from the TFT channel, the TFT channel can be inclined from
`the display when the grain boundary is parallel
`to the
`display. Another solution is crystallizing the silicon to an
`inclined direction from the display when the TFT channel is
`parallel to the display. To do this, inclining the substrate
`from the photo mask transferring direction is one way,
`inclining the photo mask pattern from the mask transferring
`direction is another way.
`
`It is preferable that the uppermost slit Sl which is
`[0069]
`provided at the uppermost portion of each region A and B is
`longer than the other slits S2 which are provided in the rest
`portion of each region A and B. The uppermost slit SI may
`be provided more than one in each region A and B. It is also
`preferable that the more inclined the slit from the transfer
`direction of the mask, the more of the uppermost slit SI.
`
`[0070] Through the slits SI and S2 arranged in the optic
`mask, a laser beam is irradiated to the amorphous silicon
`layer, so that laser-irradiated amorphous silicon changes into
`liquid state while non-irradiated amorphous silicon remains
`in solid state. Accordingly, the crystallization begins from
`the border of the solid and liquid, and grains are vertically
`grown to the border of the solid and liquid.
`
`[0071] Next, as shown in FIG. 5, a laser beam is irradiated
`to crystallize the amorphous silicon layer while the optic
`mask is horizontally transferred. The grains grow until the
`grains meet each other. After completing a horizontal trans-
`lation and laser irradiation,
`the optic mask is vertically
`translated and another horizontal translation and laser irra-
`
`diation in the opposite direction is successively performed to
`crystallize the amorphous silicon layer. That is, the optic
`mask is transferred in zigzag fashions to crystallize the
`amorphous silicon layer. Transfer of the optic mask and laser
`irradiation are performed through the entire amorphous
`silicon layer.
`
`[0072] When one silt Sl disposed at the uppermost portion
`is longer than the other slits S2,
`the amorphous silicon
`positioned at the border portions Q of shots can be com-
`pletely crystallized even when misalignment is occurred in
`the transferring optic mask.
`
`[0073] Here, it is preferable that the uppermost slit $1 is
`longer than the other slits S2 by the margin of misalignment
`of the mask. In this embodiment, the uppermost slit $1 is
`longer than the other slits S2 by 3 pm to 4 gm. Also
`preferably, the number of the uppermost slit Sl can be plural
`depending on the slope angle of the slits SI and S2.
`
`[0074] As shown in FIGS. 6A and 6B, insulating material
`such as SiNx, SiOz, etc. is deposited on the semiconductor
`layer 150 by CVD process to form a gate insulating layer
`140. Subsequently, a metal layer is deposited on the gate
`insulating layer 140 as a single layer or multi layers. The
`metal layer is made of at least one of silver (Ag), copper
`(Cu), titanium (Ti), aluminum (Al), tungsten (W), molyb-
`denum (Mo), and alloy thereof.
`[0075] After forming the metal layer, a photoresist layer is
`deposited on the metal layer, and etched using a photo mask
`to form a photoresist pattern. The metal layer is etched by
`wet etching or dry etching to form a gate line 121 and a
`storage electrode line 131. At this time, the metal layer is
`over-etched in order that the gate line 121 and the storage
`electrode 131 have narrower widths than that of the photo-
`resist pattern.
`
`[0076] The gate line 121 and the storage electrode 131
`have tapered lateral sides, so that the gate line 121 and the
`storage line 131 can be adhered more tightly with the
`overlying layer. In addition, it is possible to omit the storage
`electrode 131 if storage capacitance is sufficient without the
`storage electrode 131.
`
`layer 150 is heavily
`the semiconductor
`[0077] Then,
`doped with conductive impurities using a mask of the
`photoresist pattern to form a source region 153 and a drain
`region 155.
`
`[0078] Subsequently, as shown in FIG. 7, the semicon-
`ductor layer 150 is lightly doped with conductive impurities
`using a mask of the gate line 121 and the storage electrode
`131 after the photoresist pattern is removed, thereby com-
`pleting the semiconductor layer 150 having LDD regions
`152. Here, if the gate line 121 is not made of a material
`having high thermostability and high chemical property,
`such as titanium (Ti),
`the impurities can be doped after
`forming another photoresist pattern to reduce damage of
`interconnections.
`
`In the above, the LDD regions 152 are formed by
`[0079]
`using the photoresist pattern, but it can be formed without
`photoresist pattern if the metal layers having different etch-
`ing ratios are provided or a pair of spacers is formed to each
`sidewall of the gate line 121.
`
`[0080] Additionally, since the semiconductor layer 150,
`the storage electrode line 131, and the storage electrode 133
`are different in width and length, portions of the semicon-
`ductor layer 150 are not covered with the storage electrode
`line 131 and the storage electrode 133. The uncovered
`portions 150A also have the impurities and are adjacent to
`the storage electrode region 157. The uncovered portions
`150A are separated from the drain region 155.
`
`[0081] Next, as shown in FIG. 8A and FIG. 8B, a first
`interlayer insulating layer 601 is formed on the entire
`substrate 110, and then etched to form a first contact hole
`161 and a second contact hole 162 where the source region
`153 and the drain region 155 are respectively exposed.
`
`interlayer insulating layer 601 can be
`[0082] The first
`made of an organic material having prominent planarization
`property and photosensitivity, an insulating material having
`low dielectric constant such as a-SizCzO and a-SizOzF, which
`are formed by plasma enhanced chemical vapor deposition
`(PECVD), or an inorganic material such as SiNx, etc.
`
`[0083] Next, a metal layer made of tungsten (W), titanium
`(Ti), aluminum (Al), or alloy thereof is deposited on the first
`interlayer insulating layer 601 as a single layer or multi
`layers. The metal layer is then patterned by photo etching
`process to form a data line 171 including a source electrode
`173 which is connected with the source region 153 through
`the contact hole 161, and to form a drain electrode 175
`which is connected with the drain region 155 through the
`contact hole 162.
`
`[0084] The data line 171 and the drain electrode 175 have
`tapered lateral sides, so that the data line 171 and the drain
`electrode 175 can be adhered more tightly with the overlying
`layer.
`
`[0085] As shown in FIG. 9A and FIG. 9B, a second
`interlayer insulating layer 602 is formed to cover the data
`line 171 and the drain electrode 175. Then,
`the second
`
`
`
`US 2005/0173752 Al
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`Aug. 11,2005
`
`interlayer insulating layer 602 is patterned by photo etching
`process to form a third contact hole 163 through which the
`drain electrode 175 is exposed. The second interlayer insu-
`lating layer 602 can be made of the same material as the first
`interlayer insulating layer 601.
`
`[0086] Next, as shown in FIG. 1 and FIG. 2, a transparent
`conductive material such is as indium zinc oxide (IZO),
`indium tin oxide (ITO), etc.,
`is deposited on the second
`interlayer insulating layer 602. The transparent conductive
`layer is then patterned to form a pixel electrode 190 which
`is connected with the drain electrode 175 through the third
`contact hole 163.
`
`In case that the second interlayer insulating layer
`[0087]
`602 is made of insulating materials of low dielectric con-
`stant, the pixel electrode 190 may overlap the data line 171
`and the gate line 121, so that the aperture ratio of the pixel
`electrode 190 is enhanced.
`
`[0088] <Embodiment 2>
`
`[0089] As shown in FIGS. 10 and 11, a data connection
`part 171b and a pixel electrode 190 may be made of the same
`material on the same layer, and contact holes 161 and 162
`for connecting the data connection part 171b with a source
`region 153 and a drain region 155 of a semiconductor layer
`150 are simultaneously formed, respectively. According to
`this embodiment,
`it is possible to reduce the number of
`photo masks compared to the first embodiment.
`
`[0090] Details are described hereinafter. Some process and
`structure is same to the first embodiment. Therefore those
`
`descriptions are left out this time. A data metal piece 171a
`is formed on the same layer as the gate line 121 and extends
`perpendicular to the gate line 121, being separated from the
`gate line 121 by a predetermined distance. The data metal
`piece 171a is disposed between two adjacent gate lines 121,
`but it
`is not connected with them. Also, an end of the
`outermost data metal piece 171a can be enlarged to receive
`image signals from the external circuit (not shown).
`
`[0091] An interlayer insulating layer 160 is formed on the
`gate insulating layer 140, the gate line 121, and the storage
`electrode line 131.
`
`[0092] On the interlayer insulating layer 160, a data con-
`nection part 171b, a pixel electrode 190, and a contact
`assistant 82 are formed.