Petitioner Bluehouse Global Ltd.
`Petitioner Bluehouse Global Ltd.
`
`Ex. 1006
`Ex. 1006
`
`

`

`a2, United States Patent
`US 6,784,453 B2
`(10) Patent No.:
`Aug.31, 2004
`Miyazaki et al.
`(45) Date of Patent:
`
`US006784453B2
`
`(54) SEMICONDUCTOR DEVICE AND METHOD
`FOR PRODUCING THE SAME
`
`(75)
`
`Inventors: Minoru Miyazaki, Hokkaido (JP);
`Akane Murakami, Kanagawa(JP);
`Satoshi Teramoto, Kanagawa (JP)
`
`(73) Assignee: Semiconductor Energy Laboratory
`Co., Ltd., Kanagawa-ken (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`FOREIGN PATENT DOCUMENTS
`
`0 502 749 A2
`61-183971
`2-295111 A
`04-11722 A
`04-058564 A
`04-101453 A
`04-360580 A
`05-114724 A
`05-299655 A
`06-013615 A
`
`9/1992
`8/1986
`12/1990
`1/1992
`2/1992
`4/1992
`12/1992
`5/1993
`11/1993
`1/1994
`
`OTHER PUBLICATIONS
`
`(21) Appl. No.: 10/336,805
`
`(22)
`
`(65)
`
`Filed:
`
`Jan. 6, 2003
`
`Prior Publication Data
`US 2003/0132482 A1 Jul. 17, 2003
`
`Related U.S. Application Data
`
`(62) Division of application No. 09/782,299, filed on Feb. 14,
`2001, now Pat. No. 6,569,719, which is a division of
`application No. 08/635,283,filed on Apr. 19, 1996, now Pat.
`No. 6,201,281, which is a continuation of application No.
`08/270,773, filed on Jul. 5, 1994, now abandoned.
`
`(30)
`
`Foreign Application Priority Data
`
`Jul. 7, 1993
`
`(IP) vecee cece eeeeeceeseeesseecneseneeseneaes 5-192829
`
`(SL) Unt. C17 ee eeeeesesessessessessesneeeeees HO1L 31/036
`(52) U.S. Ch. eee teneeeeees 257/49; 257/72; 257/347
`(58) Field of Search oo... eee 257/49, 72-74,
`257/347, 348; 438/96-97, 482
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,855,112 A
`4,570,328 A
`4,646,426 A
`4,707,721 A
`
`12/1974 Tomozawaetal.
`2/1986 Price et al.
`3/1987 Sasaki
`11/1987 Angetal.
`
`S.K. Ghandhi, VLSI Fabrication Principles, pp. 486, 498,
`525.
`
`S. Wolfe, Silicon Processing for the VLSI Era, vol. 2, pp.
`104-105, 124-133, 194-196, 271-273.
`J-M Hwanget al., IEDM 792, p. 345 “Novel Polysilicon/
`TiN Stacked—Gate .
`.
`. SOI/CMOS”.
`M. Wittmeret al., Thin Solid Films, 93(1982) 397 “Appli-
`cations of TiN thin films .. .”.
`M. Wittmer, et al., J. Appl. Phys., 54(3) (1983) 1423,
`“Characteristics of TIN gate MOSEFTs”.
`
`Primary Examiner—Long Pham
`Assistant Examiner—Nathan W. Ha
`(74) Attorney, Agent, or Firm—Jeffrey L. Costellia; Nixon
`Peabody LLP
`
`(57)
`
`ABSTRACT
`
`In the production of thin film transistor (TFT), a gate
`insulating film is formed to cover an active layer, a titantum
`nitride film is formed on the gate insulating film, and an
`aluminum film used as the gate electrode is formed on the
`titanium nitride film. The resulted configuration prevents the
`etching of the aluminum film from the insulating film side
`even if the etchant of aluminum enters the recessed portion
`at the edge of the active layer during the patterning of the
`gate electrode. Also in the anodizing process, when an oxide
`film is formed on the surface of the aluminum film, the
`oxidation of aluminum from the gate insulating film side is
`prevented even when the electrolyte solution enters the
`recessed portion at the edge of the active layer.
`
`(List continued on next page.)
`
`27 Claims, 4 Drawing Sheets
`
`
`
`

`

`US 6,784,453 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`4,755,478
`4,931,411
`5,141,897
`5,166,086
`SATTS77
`5,240,868
`5,245,207
`5,252,502
`5,308,998
`5,366,912
`
`rrPrePrrere
`
`7/1988
`6/1990
`8/1992
`11/1992
`1/1993
`8/1993
`9/1993
`10/1993
`5/1994
`11/1994
`
`Abernatheyetal.
`Tigelaaretal.
`Manochaet al.
`Takedaetal.
`Taniguchiet al.
`Baeetal.
`Mikoshibaetal.
`Havemann
`Yamazaki etal.
`Kobayashi
`
`5,470,762
`5,478,766
`5,498,573
`5,576,225
`5,604,137
`5,614,732
`6,201,281 Bl *
`6,376,860 B1 *
`2003/0006414 Al *
`
`11/1995
`12/1995
`3/1996
`11/1996
`2/1997
`3/1997
`3/2001
`4/2002
`1/2003
`
`* cited by examiner
`
`Codamaet al.
`Park etal.
`Whetten
`Zhangetal.
`Yamazaki etal.
`Yamazaki
`
`........... 257/347
`Miyazaki et al.
`Mitanaga et al. oo... 257/57
`Takemura et al.
`............ 257/72
`
`

`

`Sheet 1 of 4
`
`US 6,784,453 B2
`
`U.S. Patent
`
`Aug.31, 2004
`
`FIG. 1A
`
`

`

`U.S. Patent
`
`Aug.31, 2004
`
`Sheet 2 of 4
`
`US 6,784,453 B2
`
`PnoRAR
`
`B®
`
`
`
`
`228
`
`FIG. 2B
`PRIORART
`
`94
`
`23
`
`22
`
`FIG. 2C
`PRIOR ART
`
`29
`
`FIG. 2D
`PRIOR ART
`
`

`

`U.S. Patent
`
`Aug.31, 2004
`
`Sheet 3 of 4
`
`US 6,784,453 B2
`
`FIG. 3
`PRIOR ART
`
`ST
`
`\\iid\—SSsssrCANNNNNSN
`
`NOTEEEECSN—+fsral
`
`
`

`

`U.S. Patent
`
`Aug.31, 2004
`
`Sheet 4 of 4
`
`US 6,784,453 B2
`
`
`
`
`
`

`

`US 6,784,453 B2
`
`1
`SEMICONDUCTOR DEVICE AND METHOD
`FOR PRODUCING THE SAME
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`This invention relates to an insulated gate field effect
`semiconductor device using a thin film semiconductor and a
`method for producing the same.
`2. Description of the Related Art
`A knownstructure of an insulated gate field effect tran-
`sistor using a thin film semiconductor (hereinafter referred
`to simply as “TFT”) is shown in FIG. 2D. The method for
`producing such TFT is described below with reference to
`FIGS. 2A to 2D.
`
`A basefilm (silicon oxide film) 22 is formed on a glass
`substrate 21 at a thickness of approximately 2000 A. Onthe
`base film 22, a silicon semiconductor layer 23 having
`amorphousor crystalline structure is formed as an active
`layer (where source/drain regions and a channel forming
`region are formed) at a thickness of about 1000 A to obtain
`the shape shown in FIG. 2A. An element separation pattern-
`ing is performed to obtain a shape shownin FIG. 2B. During
`this patterning,it is difficult to etch only the active layer 23,
`and the base film 22 is also etched to some extent. As a
`
`result, a recessed portion 24 occurs on the base film 22.
`A silicon oxide film 26 as the gate insulating film is
`formed at a thickness of approximately 1000 A. As seen in
`FIG. 2C, however, the film 26 also generates a recessed
`portion 27. FIG. 4 is a cross section TEM photograph
`corresponding to the shape shown in FIG. 2C. The photo-
`graph represents the state of thin film at the recessed portion
`27 where a concave strip appears to form a notch.
`After this etching, an aluminum film 28 is formed at a
`thickness of 6000 A, and the film 28 is patterned to form a
`gate electrode. Then an anodizing treatmentis given to the
`patternedelectrode to form an oxidelayer 29 at a thickness
`of 2000 A. FIG. 2D shows the A—A'crosssection of FIG.
`2C. As illustrated in FIG. 2D,
`the aluminum film 28 is
`patterned to form the gate electrode. FIG. 3 is a schematic
`drawing of a plan view of a TFT shownin FIG. 2C or FIG.
`2D. The C—C'cross section of FIG. 3 corresponds to FIG.
`2D, and the B—B' cross section corresponds to FIG. 2C. The
`reference numbers 30 through 32 in FIG. 3 are the contact
`electrodes, though they are not shown in FIG. 2C and FIG.
`2D.
`
`A problem of such TFTis that the presence of recessed
`portion 27 causes substantial break of the gate electrode and
`the gate wiring 28. The breaking is presumably caused by
`the following phenomena.
`1. The patterning of the gate electrode 28 made of aluminum
`is preferably conducted by a selective etching using a
`wet-etching method. Bythis etching process, however, an
`etchant solution enters into the recessed portion 27. As a
`result, the recess is enlarged, and, in the worst case, the
`gate electrode 28 breaks at the portion 34.
`2. By anodizing after the aluminum film 28is patterned, the
`surface of the patterned gate electrode 28 is oxidized.
`During the anodizing, however, the electrolyte solution
`enters into the recessed portion 27 to oxidize the portion
`34 from the gate electrode side. Consequently, the gate
`electrode 28 increases its resistance and further becomes
`insulated.
`
`The defects of TFT are supposed often to occur by the
`combination of these reasons. The production of TFTs
`having a structure shown in FIGS. 2C to 2D faces reduction
`of a yield.
`
`2
`SUMMARYOF THE INVENTION
`
`The object of this invention is to prevent the etching of the
`portion 27 during the patterning of the aluminum film 28 and
`to prevent the oxidation also at the recessed portion 27
`during the anodization after this patterning, in the treatment
`shown in FIG. 2C.
`
`A preferred mode of the invention is described using FIG.
`1C. According to the invention, as typically illustrated in
`FIG. 1C, a titanium nitride film 17 is formed on a gate
`insulating film 16, and further an aluminum film 18 used as
`a gate electrode is formed onthe film 16. Since the titantum
`nitride film 17 can be formed at an extremely high step
`coverage (difference level coating) using a sputtering
`method, the recess 151 is buried or covered by the film 17.
`The reason for selecting the titanium nitride film is that
`the material has etching selectivity to aluminum film. In
`concrete terms, during the etching of aluminum film, the
`titanium nitride film is not etched, and during anodizing, the
`titanium nitride film is not oxidized. Accordingly, a film
`having those characteristics may be used in placeoftitantum
`nitride film independent of the conductivity and insulating
`property of the film. Examples of that type of material that
`exhibits a similar effect as the titanium nitride film and is
`useful in this invention are a metallic titanium film in which
`
`no nitrogen is added and a phosphorus-doped silicon film
`formed by low pressure CVD (LPCVD) method. Thattype
`of film may be formed at a thickness from 50 to 1000 A,for
`example, a thickness from 50 to 500 AIt is necessary to
`form the thin film in consideration of the thickness of gate
`insulating film and of gate electrode.
`According to the invention, wiring containing mainly
`aluminum is formed with high reliability on an object having
`a convex portion. When an electrode or wiring containing
`mainly aluminum is formed by covering on or crossing over
`the object (for example, the active layer 14 in FIG. 1B)
`having a convex, the breakage of the wiring structured with
`the aluminum film 18 at the edge 15 of the convex portion
`can be prevented. Because thefirst film (for example, the
`titanium nitride film 17) exhibits an etching selectivity for
`the second film (for example, the aluminum film 18). This
`utilizes the characteristic that the first film is not etched or
`
`has a low etching rate during the etching of second film.
`In particular, when a titanium nitride film is used as the
`first film, when an aluminum film is used as the second film,
`and when the surface of the aluminum film is oxidized
`during the anodization, the oxidation in the vicinity (the
`portion 152 of FIG. 1C) of edge root of the convex on the
`object from the object side can be prevented, and the defects
`caused by substantial breakage of the second film can be
`reduced.
`
`Titanium nitride film is not etched by an aluminum
`etchant. Consequently, even when an etchant enters the
`recess 151 during the patterning of gate electrode and gate
`wiring, the etching of aluminum film 18 can be prevented.
`Furthermore,
`in the anodizing after the patterning of
`aluminum film 18, even if the electrolyte solution enters the
`portion 151, the oxidization of the aluminum film 18 from
`the gate insulating film side can be prevented.
`As described above, the breakage of the aluminum film
`can be prevented by forming on the gate insulating film an
`aluminum film used as the gate electrode, via a titantum
`nitride film.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A to 1D show the procedure for producing a TFT
`of an embodimentof this invention.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`

`

`US 6,784,453 B2
`
`3
`FIGS. 2A to 2D show the procedure for producing a
`common TFT.
`
`FIG. 3 showsa plan view ofthe structure of TFT in FIGS.
`2C and 2D.
`
`FIG. 4 is a photograph showinga cross section of the thin
`film in FIG. 2C.
`
`DETAIL DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`FIGS. 1A to 1D illustrate the procedure for producing an
`N-channel thin film transistor (TFT) of an embodiment of
`this invention. Although the embodimentdescribes the pro-
`duction procedure for an N-channel TFT, a P-channel TFT
`may be applied for this invention. The TFT of the embodi-
`mentis applicable for TFTs formedat a peripheral circuit or
`at a pixel area in a liquid crystal display unit, and further for
`TFTs in integrated circuits.
`The silicon oxide film 12 as the base film is formed at a
`thickness of 2000 A on the glass substrate 11 using a
`sputtering method. The amorphoussilicon film 13 is formed
`at a thickness of 1000 A by plasma CVD method. The
`formedsilicon film 13 is crystallized by heating,irradiating
`laser beam,irradiating intense light, etc. A crystalline silicon
`film may be formed directly by vapor deposition method
`instead of the amorphoussilicon film 13, and the amorphous
`film may be left non-crystallized. The element separation
`patterning is conducted to form the active layer 14. The
`active layer 14 has the source/drain regions and the channel
`forming region of TFT. During the element separation
`patterning, a mask is placed on the crystallized silicon film
`13 to perform anisotropic dry etching by the reactive ion
`etching (RIE) method. However,it is technically difficult to
`stop the dry etching at the surface of the base film 12, and
`the etching actually proceeds into the base film 12. In
`particular, the edge of the active layer 14 is notched, and the
`etching also proceeds in the horizontal direction. Asa result,
`the portion 15 produces.
`The silicon oxide film 16 as the gate insulating film is
`formed at a thickness of 1000 A by a sputtering method. As
`seen in FIG. 1C, a recess directed towards the active layer
`14 is formed in the silicon oxide film 16.
`
`It is useful to improve the characteristics of the interface
`between the silicon oxide film 16 and the silicon film 14
`used as the active layer by radiation of intense lightafter the
`silicon oxide film 16 is formed. As an example ofthe intense
`light, infrared light having a peak wavelength of 1.3 wm can
`be used. Radiation of such infrared light reduces the inter-
`face level between the silicon film 14 and the silicon oxide
`film 16.
`
`The next process is to form the titanium nitride film 17 at
`a thickness of, for example, 500 Aina range of from 50 to
`1000 A by a sputtering method. The sputtering method may
`be sputtering of a titanium nitride target by argon molecules
`or sputtering of a titantum by nitrogen molecules. The
`conditions of the sputtering are: a pressure of 3x10-3 Torr,
`RP powerof 200 W, heating temperature of 200° C.
`Thetitanium nitride film 17 is formedto bury or cover the
`recessed portion 151 on the silicon oxide film 16. Then, the
`aluminum film 18 is formed. The aluminum film 18 is
`
`patterned by a wet etching method. A mixed acid aluminum
`solution is used in the patterning to selectively etch only the
`aluminum film 18. Since the titanium nitride film 17 is not
`almost etched, the recess portion 151 does not enlarge. For
`the smooth operation of the succeeding anodization, one or
`more of the elements selected from scandium, palladium,
`andsilicon is added to the aluminum film 18 at 1 to 5% by
`weight.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`40
`
`45
`
`50
`
`55
`
`60
`
`4
`The titanium nitride film 17 is etched with an aqueous
`ammonia (NH,OH/H,O./H,O) using the patterned alumi-
`num film 18 as a mask. During the treatment, the titantum
`nitride film 17 is selectively etched. Then, the oxide layer 19
`is formed on the surface of the aluminum film 18, as the gate
`electrode patterned by anodization. In the anodization, the
`electrolyte solution of ethylene glycol containing tartaric
`acid (3% by weight) and ammonia water (5% by weight) is
`used. The thickness of the oxide layer formed by the
`treatment can be controlled by adjusting the applied voltage
`and the oxidation time.
`
`During the anodization, even if the electrolyte solution
`enters the recessed portion 151,
`the portion 152 is not
`oxidized from the side of the gate insulating film 16.
`Accordingly,
`the portion 152 becomes an insulator and
`breaking of the aluminum film 18 as the gate electrode can
`be prevented.
`FIG. 1D shows the A—A'cross section of FIG. 1C. The
`gate electrode 18 and the oxide layer 19 are used as the mask
`to perform the phosphorus (P) ion implantation. In the ion
`implantation, phosphorusions are implanted into the regions
`101 and 103, and the source/drain regions 101 and 103 and
`the channel forming region 102 are formedin a self-aligning
`manner. In this process, the thickness of the oxide layer 19
`formed during the anodization allows to form an offset gate
`region. The activation of the source/drain regions 101 and
`103 is performed by radiation of laser light or intense light.
`During the activation treatment (annealing), it is useful to
`apply rapid thermal annealing (RTA)using infrared light as
`the intense light. The annealing methodutilizes the selective
`absorption of infrared light to the silicon film, to heat the
`silicon film up to 1000 to 1200° C. within a short time.
`The film formation of interlayer insulators, the patterning
`for opening holes, and the formation of source/drain elec-
`trode and gate electrode are performed to complete the
`production of TFT, though these processes are not shown in
`the figures.
`When the titanium nitride film is formed on the gate
`insulating film, and when the aluminum film is formed on
`the titanium nitride film, the succeeding patterning of the
`aluminum film does not induce the etching of the aluminum
`film at the edge of the active layer from the gate insulating
`film side. Furthermore, during the formation of the oxide
`layer in the anodization, the progress of the oxidation of the
`aluminum film from the gate insulating film side is sup-
`pressed. Consequently, the substantial breakage of the gate
`wiring is prevented, and a TFT with a high reliability is
`produced.
`Whatis claimedis:
`
`1. An insulated gate field effect transistor comprising:
`an insulating film comprising silicon oxide;
`a semiconductor island formed on said insulating film,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island, said gate insulating film including silicon oxide;
`a metal nitride film formed on and in direct contact with
`
`the gate insulating film;
`a metalfilm formed on and in direct contact with the metal
`nitride film,
`wherein the metal nitride film extends beyond edges of
`the semiconductorisland.
`
`2. A transistor according to claim 1, wherein the metal
`nitride is a titantum nitride film.
`3. A transistor according to claim 1, wherein the metal
`nitride film has a thickness in a range of 50 to 1000 A.
`
`

`

`US 6,784,453 B2
`
`5
`4. A transistor according to claim 1, wherein the metal
`film is an aluminum film.
`
`5. A transistor according to claim 1 wherein a surface of
`said metal film is oxidized.
`6. A thin film transistor comprising:
`an insulating film comprising silicon oxide;
`a semiconductor island formed on said insulating film,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island, said gate insulating film including silicon oxide;
`a gate electrode formed on the gate insulating film, said
`gate electrode including a metal nitride film formed on
`the gate insulating film and a metal film formed on the
`metal nitride film,
`wherein the metal nitride film extends beyond edges of
`the semiconductorisland.
`7. A transistor according to claim 6, wherein the metal
`nitride is a titanium nitride film.
`8. A transistor according to claim 6, wherein the metal
`nitride film has a thickness in a range of 50 to 1000 A.
`9. A transistor according to claim 6, wherein the metal
`film is an aluminum film.
`
`10. A transistor according to claim 6 wherein a surface of
`said metal film is oxidized.
`
`11. A thin film transistor comprising:
`a semiconductor island formed on an insulating surface,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island;
`a gate electrode formed over the channel region with the
`gate insulating film interposed therebetween,said gate
`electrode including a metal nitride film formed on the
`gate insulating film and a metal film formed on the
`metal nitride film,
`wherein the gate electrode extends beyond edges of the
`semiconductor island and said metal nitride film
`extends beyond side edges of the metal film in a
`direction along said source and drain regions.
`12. A transistor according to claim 11, wherein the metal
`nitride is a titanium nitride film.
`
`13. A transistor according to claim 11, wherein the metal
`nitride film has a thickness in a range of 50 to 1000 A.
`14. A transistor according to claim 11, wherein the metal
`film is an aluminum film.
`15. A transistor according to claim 11 wherein a surface
`of said metal film is oxidized.
`16. A thin film transistor comprising:
`an insulating film comprising silicon oxide;
`a semiconductor island formed on said insulating film,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island;
`a gate electrode formed over the channel region with the
`gate insulating film interposed therebetween,said gate
`
`6
`electrode including a metal nitride film formed on the
`gate insulating film and a metal film formed on the
`metal nitride film,
`wherein the gate electrode extends beyond edges of the
`semiconductor island and said metal nitride film
`
`10
`
`extends beyond side edges of the metal film in a
`direction along said source and drain regions.
`17. A transistor according to claim 16, wherein the metal
`nitride is a titantum nitride film.
`18. A transistor according to claim 16, wherein the metal
`nitride film has a thickness in a range of 50 to 1000 A.
`19. A transistor according to claim 16, wherein the metal
`film is an aluminum film.
`
`15
`
`20. A transistor according to claim 16 wherein a surface
`of said metal film is oxidized.
`
`20
`
`25
`
`40
`
`45
`
`21. A thin film transistor comprising:
`a semiconductorisland formed on an insulating surface,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island;
`a gate electrode formed over the channel region with the
`gate insulating film interposed therebetween, said gate
`electrode including a titanium nitride film formed on
`the gate insulating film and an aluminum film formed
`on the titanium nitride film,
`wherein the gate electrode extends beyond edges of the
`semiconductor island and said titanium nitride film
`extends beyond side edges of the aluminum film in a
`direction along said source and drain regions.
`22. A transistor according to claim 21 wherein a surface
`of said metal film is oxidized.
`
`23. A thin film transistor comprising:
`an insulating film comprising silicon oxide;
`a semiconductor island formed on said insulating film,
`said semiconductor island including source and drain
`regions therein and a channel region therebetween;
`a gate insulating film formed over the semiconductor
`island;
`a gate electrode formed over the channel region with the
`gate insulating film interposed therebetween, said gate
`electrode including a metal nitride film formed on the
`gate insulating film and a metal film formed on the
`metal nitride film,
`wherein the metal nitride film extends beyond edges of
`the semiconductor island and said metal nitride film
`
`extends beyond side edges of the metal film in a
`direction along said source and drain regions.
`24. A transistor according to claim 23, wherein the metal
`nitride is a titantum nitride film.
`
`25. A transistor according to claim 23, wherein the metal
`nitride film has a thickness in a range of 50 to 1000 A.
`26. A transistor according to claim 23, wherein the metal
`film is an aluminum film.
`27. A transistor according to claim 23 wherein a surface
`of said metal film is oxidized.
`
`