United States Patent (19)
`Clark
`
`54) HIGH SPEED SIGNAL CONVERSION
`METHOD AND DEVICE
`
`75 Inventor: Iain Clark, Newark, Calif.
`
`0
`-
`73 Assignee: LSI Logic Corporation, Milpitas,
`Calif.
`This patent is subject to a terminal dis-
`claimer.
`
`Notice:
`
`*
`
`21 Appl. No.: 08/607,433
`22 Filed:
`Feb. 27, 1996
`O
`O
`Related U.S. Application Data
`63 Continuation of application No. 08/161,729, Dec. 3, 1993
`Pat. No. 5,504,503.
`2 4 - 2 - 1 wY-8 - 2
`2
`2- Y
`- 2
`(51) Int. Cl. ................................................. B09G 5/00
`52 U.S. C. ...
`345/518; 34.5/516; 34.5/507
`58 Field of Search ......................... 365/230.04, 230.05,
`365/230.08, 230.09, 189.05; 34.5/185, 189,
`186, 190, 200, 507, 509, 515, 516, 517,
`518; 395/507, 509, 515, 516, 517,518
`References Cited
`U.S. PATENT DOCUMENTS
`4,503,429 3/1985 Schreiber.
`4,742,350 5/1988 Ko et al..
`4,791,580 12/1988 Sherrill et al..
`4,849,937 7/1989 Yoshimoto.
`4,860,263 8/1989 Mattausch .......................... 363/230.05
`
`56)
`
`US006020904A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,020,904
`*Feb. 1, 2000
`
`1/1990 Frankenbach.
`4,894,653
`2/1990 Brunoli.
`4.905,189
`5,097,256 3/1992 Eldridge et al..
`5,163,024 11/1992 Heilveil et al..
`5,204,664 4/1993 Hamakawa.
`5,220,312 6/1993 Lumelsky et al..
`5,269,003 12/1993 Roskowski et al..
`5,276.803
`1/1994 Iwase.
`i.
`5,283,866
`2/1994 K
`f
`lumagal
`Primary Examiner Dennis-Doon Chow
`57
`ABSTRACT
`0
`-
`A random acceSS memory has an access time which is longer
`than the period of read input signals, for example digital
`Video data Signals, Such that it cannot respond directly to the
`input Signals. The memory has two read address inputs and
`two outputs which are arranged as separate channels, each of
`which can access any location in the memory. The access
`time of the memory is shorter than two input Signal periods.
`The input Signals are applied alternatingly to the read
`address inputs, and output Signals constituted by data Stored
`at addresses corresponding to the input signals are produced
`at the memory outputs by an arrangement of clocked latches
`Such that, although two input signal periods are used for
`accessing each memory location, the alternating accessing
`using two channels enables the memory to produce output
`Signals having the same period (at the same frequency) as
`the input signals. Additional elements are provided to enable
`writing to the memory using the alternating channel
`arrangement, and also to enable memory locations to be
`unconditionally interrogated while responding to a stream of
`read input signals.
`
`17 Claims, 4 Drawing Sheets
`
`24
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`1
`HIGH SPEED SIGNAL CONVERSION
`METHOD AND DEVICE
`
`This application is a continuation of U.S. patent appli
`cation Ser. No. 08/161,729, filed Dec. 3, 1993, now U.S. Pat.
`No. 5,504,503, issued Apr. 2, 1996.
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a method and apparatus
`for converting an input signal to an output signal at a high
`rate of Speed, and, more particularly, to a method and
`apparatus for accessing values in a memory device at high
`rates of Speed.
`2. Description of Related Art
`In the field of information processing it is highly desirable
`to convert or transform a Signal from one form to another at
`a high rate of Speed. A signal is often represented by a stream
`of data and arrives at an input to the information processing
`System. Each datum in the Stream often arrives at the input
`at a fixed time period after the preceding datum has arrived.
`The shorter the period is between incoming data, the higher
`the rate is of the data Stream.
`The data Stream can also be considered as a time Sequence
`of values arriving at the input to the information processing
`device. When a stream of incoming data arrives at an input
`to an information processing System at a high rate, it is often
`advantageous to convert or transform that data to an output
`at an equally high rate. Usually, at least one output Stream of
`data is desired at a rate Substantially equal to the input rate.
`One example of a System wherein high conversion rates
`are desired is in a color-enhancement System for conven
`tional Video displayS. The image on the Video display is
`composed of many points known as pixels. Each pixel is
`displayed according to data indicating its position on the
`display Screen and the color to be displayed at that position.
`The image is composed by updating the display Screen
`frequently using data provided for each pixel. Color
`enhancement usually is accomplished by expanding the
`number of bits used to designate color data for each pixel.
`In many conventional Video display Systems, pixel color
`data is composed of 8-bits of digital information, which
`allow for the potential to display 256 different colors at that
`pixel position. In order to enhance the quality of the dis
`played image, a practice has developed of expanding, in a
`conversion or transformation, the number of pixel color data
`bits, to, for example, 18 or 24 bits per pixel. Although Such
`a practice results in an enhanced color image, difficulties and
`limitations are encountered in its implementation.
`A Significant limitation is that the conversion device
`requires a relatively long amount of time to effect a
`conversion, or, in this case, a bit-length expansion. This has
`required the makers of color enhancement Systems to limit
`the rate of the incoming color pixel data Stream to accom
`modate a Slow conversion device. Slowing down the data
`Stream means that the pixel information in the Video display
`cannot be sent to the display Screen as frequently, thereby
`limiting the image quality.
`One of the most commonly used types of conversion
`devices is a Random Access Memory (RAM). In a RAM,
`data values are Stored in a number of locations commonly
`referred to as addresses. Each address or location holds one
`data value. An input signal to the RAM, commonly referred
`to as an address Signal, indicates which data value will be
`made available by the RAM on its output line as an output
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`Signal. The RAM effects a conversion by accepting an
`address input value, pointing to or Selecting a stored data
`value in a memory location based on the address input value,
`and by outputting the data value Stored in the Selected
`memory location. The time it takes for the RAM to convert
`an address input to a valid data Signal value is usually
`referred to as an access time.
`Returning to the Video display example, one color
`enhancement Scheme makes use of a RAM with an 8-bit
`address input capable of addressing or pointing to 256 (2)
`separate memory locations. The RAM can be built to store
`and output data values having Virtually any bit-length, Such
`as 18 or 24 bits. By Storing appropriate data values in each
`memory location, the RAM is capable of converting 8-bits
`of input data to, for example, 18 or 24 bits of output data.
`Ordinarily, a conventional Video display is configured to
`accept 8-bits of incoming color data per pixel in a data
`Stream. The Video display can be reconfigured to accept an
`expanded number of bits, Such as 18 or 24, in an incoming
`data stream. ARAM is interposed between the video display
`and the incoming 8-bit data Stream So that the incoming 8-bit
`data stream becomes an address input to the RAM. The
`address input is used to access an appropriate expanded
`value, Stored in a memory location or address, and to use that
`value as output to the Video display.
`Hence, the Video display accepts more color information
`per pixel, increasing the image quality of the displayed
`image. However, the period between incoming data values
`in the data Stream must not exceed the access time of the
`RAM, or erroneous conversions will occur, Scrambling the
`image. In other words, the rate of incoming data must be
`decreased to accommodate the RAM access time to maintain
`image integrity. This limits the quality of the image capable
`of being displayed by the Video display.
`The display of a Video image is just one example of an
`information processing application which requires a conver
`Sion of a signal from one form to another at a high rate of
`Speed. Many other situations are encountered where a con
`version device, Such as a RAM, requires a conversion time
`which exceeds the potential period between incoming data
`in a data Stream, So that accurate conversion is not possible
`without slowing down the incoming data Stream. A common
`Solution in Such situations has been to slow down the data
`Stream to accommodate a slow conversion device.
`Various references discuss the rate of image generation in
`a Video display device. However, the general problem of
`having to accommodate a relatively slow access device has
`not been adequately resolved by these references.
`For example, U.S. Pat. No. 4,905,189, issued to Brunolli,
`discloses a System for Synchronously reading information
`from a RAM device on a fast port independently of the
`devices ability to asynchronously read or write information
`to the RAM on a slow port. Information is read out of the
`memory and evaluated using two alternatingly Switched
`channels to increase the evaluation Speed.
`This reference does not effectively address the problem of
`converting values in an incoming data Steam at a relatively
`high rate using a conversion device having a high conver
`Sion or access time, utilizing external timing control ele
`ments. It merely teaches how to increase the evaluation
`Speed of data after it has been read out of the device.
`Another example, U.S. Pat. No. 4,742,350, issued to Ko
`et al., discloses a System for displaying an image using
`picture data, attribute data, and Synchronization data,
`wherein the attribute data includes embedded Synchroniza
`tion data.
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`6,020,904
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`U.S. Pat. No. 4,791,580, issued to Sherrill et al., discloses
`multiple color map memories to quickly Store color map
`information during display line retrace intervals. This pri
`marily involves a Scheme for quickly writing data into
`multiple color map RAM memories, included in a display
`processor, from a video RAM (VRAM) memory.
`U.S. Pat. No. 5,163,024, issued to Heilveil et al., discloses
`a Video memory device employing a bit-mapped RAM unit,
`a Serial shift register and appropriate decode circuitry to
`enable a single video memory to be used with displayS using
`various numbers of bit resolution.
`Although teaching the principles of data Storage and
`retrieval in a random access memory, the prior art, as
`represented by these references, does not effectively address
`the problem of converting values in a data Stream at a
`relatively high rate using a conversion device having a high
`conversion time.
`
`SUMMARY OF THE INVENTION
`The present invention effectively overcomes the problem
`discussed above which has remained unsolved in the prior
`art. More specifically, a device and method of the invention
`enable a random acceSS memory having an access time
`which is ordinarily too long to effectively process input data
`and perform conversions thereon, to accomplish this task.
`In accordance with the invention, a random access
`memory has an access time which is longer than the period
`of read input signals, for example digital Video data Signals,
`Such that it cannot respond directly to the input signals. The
`memory has two read address inputs and two outputs which
`are arranged as Separate channels, each of which can acceSS
`any location in the memory. The access time of the memory
`is shorter than two input signal periods.
`The input Signals are applied alternatingly to the read
`address inputs, and output Signals constituted by data Stored
`at addresses corresponding to the input signals are produced
`at the memory outputs by an arrangement of clocked latches
`Such that, although two input signal periods are used for
`accessing each memory location, the alternating accessing
`using two channels enables the memory to produce output
`Signals having the same period (at the same frequency) as
`the input signals.
`Additional elements are provided to enable writing to the
`memory using the alternating channel arrangement, and also
`to enable memory locations to be read by the cpu 12 while
`color conversion is occurring.
`The present invention also comprises a method of con
`Verting input values in a time Sequence of Signal values into
`a time Sequence of output values. The method comprises the
`Steps of temporarily Storing a first input value in a time
`Sequence of Signal values, temporarily Storing a Second
`input value in the time Sequence of Signal values, initiating
`conversion of the first Stored input value, initiating conver
`Sion of the Second Stored input value before completion of
`the first conversion, temporarily Storing a converted output
`value of the first input value, temporarily Storing a converted
`output value of the Second input value, and Selectively
`coupling to an output the Stored converted output values of
`the first and Second input values So as to provide a time
`Sequence of converted output values.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 shows the present high Speed signal conversion
`device in the context of a System for enhancing color in
`Video display image.
`
`4
`FIG. 2 shows a timing diagram of data flow in the present
`high Speed signal conversion device for converting an input
`Sequence of values to an output Sequence of values.
`FIG.3(a) shows a timing diagram of timing signals for the
`present high Speed signal conversion device.
`FIG. 3(b) shows a timing diagram of timing signals for
`effecting a read operation in the present high Speed signal
`conversion device.
`FIG. 4 shows a timing diagram of data flow during a read
`operation in the present high Speed signal conversion device.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`Referring to FIG. 1 of the drawings, in one typical
`operating environment, a high Speed signal conversion
`device 10 in accordance with the present invention can
`enhance the quality of an image displayed on a conventional
`Video display. The operating environment depicted in FIG.
`1 is of a computer controlled Video display device, and
`shows conventional computer or central processing unit
`(CPU) 12, video controller 14, display memory 16, digital
`to-analog conversion device 18 and video display 20, in
`addition to the present high Speed signal conversion device
`10.
`In conventional fashion, video controller 14 is operatively
`connected to video RAM 16 and to CPU 12. Digital-to
`analog conversion device 18 is operably connected to Video
`display 20, also in conventional fashion. High Speed signal
`conversion device 10 connects between video controller 14
`and digital-to-analog conversion device 18, and replaces
`conventional devices for effecting an expansion of the
`number of color bits used to provide color information for a
`pixel in a video display 20.
`In the context of this typical environment, high Speed
`Signal conversion device 10 accepts an input time Sequence
`of values, or a data Stream, typically comprising 8-bit digital
`values, over color data bus 42 from video controller 14. Each
`digital value in the data Stream comprises 8-bits of color
`information, or an 8-bit color value, which provides color
`information for a pixel displayable in an image on the Video
`display 20.
`High speed signal conversion device 10 converts 8-bit
`color values at a Substantially high rate, expanding the
`number of bits available to provide color information to, for
`example, 18-bits per pixel. By using high Speed signal
`conversion device 10, the frequency of the incoming (and
`outgoing) time sequence of data values can be increased, for
`example, from 80 MHZ-90 MHz to 160 MHz-170 MHz,
`when utilizing a memory device 22 with an access time of
`approximately 4 ns-5 ns, nominal, and approximately 10 ns
`WOrSt Case.
`One of ordinary skill in the art will appreciate that the
`designation, interconnection, and operation of the conven
`tional elements listed above is Susceptible to many different
`forms of implementation, and in no way limits the Scope of
`the present invention. Furthermore, the block diagrams
`shown in FIG. 1 merely illustrate the functions performed
`and should not be construed as limiting the possible appli
`cations of the present invention to any Specific environment.
`Thus, by way of example, display memory 16 could be
`either some form of RAM or ROM memory. Similarly, if
`desired, all of the CPU, video controller, and memory could
`be embodied in a single circuit. Alternatively, the CPU 12
`may be embodied in a single integrated circuit with con
`ventional dynamic random access memory (DRAM)
`employed as the display memory 16 thus applicants do not
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`regard their invention as being limited to any specific
`embodiment of these conventional elements. A detailed
`discussion of the high speed conversion device 10 of the
`present invention follows.
`Still referring to FIG. 1, one preferred embodiment of the
`high Speed conversion device 10 comprises a memory
`device 22, first and Second input latches 24 and 26, first and
`second output latches 28 and 30, and a first multiplexer 32.
`The device 10 can further include a second multiplexer 34,
`an address module 36, a third multiplexer 38 and a read latch
`40. A timing module 92 is also shown.
`Memory device 22 preferably is a RAM and includes at
`least two inputs, or address ports (AD1 and AD2), and at
`least two outputs, or data ports (OD1 and OD2). The
`memory device 22 may further include a write address port
`(WAD), a write data port (WD), and a write enable control
`(WE). Memory device 22 may, in alternative embodiments,
`comprise any type of digital Storage device, Such as, for
`example, a read only memory (ROM). Memory device 22
`contains a plurality of Stored digital values which are
`Selectable for output on the data ports based on input values
`on the address ports.
`Memory device 22 is of conventional design Such that any
`and all Storage locations (addresses) are addressable on
`either address port AD1 or AD2, and such that the data
`Stored in any address location may be simultaneously output
`to either data port OD1 or OD2. The address port AD1 and
`output OD1 constitute a first memory channel, whereas the
`address port AD2 and output OD2 constitute a second
`memory channel.
`Thus, inputs to AD1 at a particular time cause a particular
`stored data value to be output at OD1 at a later time which
`depends on the acceSS or conversion time of memory device
`22. Similarly, inputs to AD2 at a particular time cause a
`particular Stored data value to be output at OD2 at a later
`time which depends on the acceSS or conversion time of
`memory device 22. The two input-output channels just
`described operate independently from each other and can
`therefore simultaneously access the Stored data values.
`A preferred example of a two-port RAM memory device
`which is commercially available as an off-the-shelf item and
`can be directly utilized as the memory device 22 is the
`Model IDT7130SA/LA, IDT714OSA/LA, CMOS DUAL
`PORT RAMS 8K (1 Kx8-BIT), manufactured by Integrated
`45
`Device Technology Inc., Santa Clara, Calif., as described in
`a data sheet published in December 1987.
`The first and second input latches 24 and 26, as well as
`first and second output latches 28 and 30, each preferably
`have at least one input and at least one output, and each
`respond to a timing pulse at a control input. Respectively, on
`the occurrence of an appropriate timing pulse, a digital value
`presented at the latch input is provided at the latch output.
`Preferably, the input and output latches are conventional
`edge-triggered flip-flop type devices. Alternatively, the input
`and output latches may be conventional level-Sensitive, or
`transparent, latches.
`First (input) multiplexer 34, Second (output) multiplexer
`32, and third (read) multiplexer 38, are conventional mul
`tiplexers each including at least two data inputs, one output,
`and a Select input. Each multiplexer respectively provides a
`data value at a Single input to its output in response to a
`value, or Select pulse, presented to its Select input.
`Read latch 40 preferably includes at least one input and at
`least one output, and responds to a timing pulse at a control
`input. On the occurrence of an appropriate timing pulse, a
`digital value presented at the latch input is provided at the
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`latch output. Preferably, the read latch 40 is a conventional
`edge-triggered flip-flop type device. Alternatively, it may be
`a conventional level-Sensitive, or transparent, latch. In an
`alternative preferred embodiment, the read latch 40 may
`further include a conventional double-buffered, or
`multistage-buffered, arrangement, So that it may respec
`tively accept and Store previous data values and new data
`values in each Stage-buffer. Read latch 40 may also accept
`as input a byte-select signal, as part of R/W control bus 70,
`so that a subset of the digital bits stored therein may be
`selected for output on read/write interface bus 62.
`Address module 36 is preferably included in an embodi
`ment of the present high Speed conversion device 10.
`Address module 36 comprises conventional digital circuitry,
`and includes a read input 64 (RD), a write input 66 (WR),
`and an input/output address input 120 (I/O ADD) for con
`trolling the read/write mode of operation within the address
`module 36, a pixel clock timing input (PCLK), and a
`read/write data input (R/W DATA) for accepting read or
`write input data from the video controller 14, or, indirectly,
`from the CPU 12. Address module 36 provides as output a
`read output (RD), a read/write address output (R/W ADD),
`and a read/write control output (R/W).
`Timing module 92 comprises conventional digital cir
`cuitry and preferably includes a pixel clock timing input
`(PCLK) and preferably includes a read input (RD). Timing
`module 92 preferably provides phase timing pulse outputs
`(B/D and C/E) and first select pulse output (F). The timing
`module 92 can also provide Second timing pulse output (H)
`and Second Select pulse output (G).
`Still referring to FIG. 1, memory device 22 connects at a
`first address port AD1 to an output of first latch 24 over a
`first input channel 76. Memory device 22 connects at a
`Second address port AD2 to an output of Second input latch
`26 over second input channel 78. First and second input
`channels 76 and 78 preferably comprise 8-bit paths.
`Similarly, memory device 22 connects at a first data port
`OD1 to an input of output latch 28 over first output channel
`80 and connects at a second data port OD2 to an input of
`output latch 30 over second output channel 82. First and
`second output channels 80 and 82 preferably comprise
`18-bit paths.
`First input latch 24 and Second input latch 26 are respec
`tively connected, at an input, to common input channel 74.
`Common input channel 74, first input latch 24, and Second
`input latch 26 all preferably comprise 8-bits.
`First output latch 28 and second output latch 30 connect
`at an output to an input of first multiplexer 32 over first and
`second latched output channels 84 and 86, respectively. Both
`output latches 28 and 30 and the first multiplexer 32, as well
`as the latched output channels 84 and 86, preferably com
`prise 18-bits. The output of first multiplexer 32 is provided
`on converted output channel 94, which preferably comprises
`18-bits.
`The timing module 92 connects at an input to a clock
`output of video controller 14 over pixel clock line 72.
`Timing module 92 also connects at a first phase output (B/D)
`to a timing pulse input of first input latch 24 Over a first
`phase timing pulse line 46 and to a timing pulse input of first
`output latch 28 over a first phase timing pulse line 50.
`Second input latch 26 and second output latch 30 also
`connect at a respective timing pulse input to a Second phase
`output (C,E) of timing module 92 over Second phase timing
`pulse lines 48 and 52. Finally, timing module 92 connects at
`a first Select output (F) to a select input of first (output)
`multiplexer 32 over first select pulse line 54.
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`8
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`6,020,904
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`15
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`25
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`35
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`40
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`7
`In operation, the present invention provides for an input
`Signal arriving at a high rate to be converted to an output
`Signal at a Same rate, even though a conversion device is
`used with an access time ordinarily too long (slow) to
`operate properly at Such a high rate. In particular, input
`signal rates substantially in excess of 160 MHz-170 MHz
`are achievable when a memory device 22 is used having a
`nominal access time of approximately 4 nS-5 nS
`(nanoSeconds) and a worst case access time of approxi
`mately 10 nanoSeconds.
`Operation of the invention proceeds with reference to
`FIGS. 1 and 2. A pixel clock signal, carried on pixel clock
`line 72, is generated in the video controller 14 and controls
`the frequency of transmission of pixel information in the
`overall video display System. In this embodiment a period,
`or cycle, of the pixel clock preferably begins on each rising
`edge and concludes on the next rising edge of the pixel clock
`Signal.
`Input data values on common input channel 74 arrive in
`Synchronized relationship with the periods of the pixel
`clock, as shown in FIG. 2. Hence, a time Sequence of data
`values is presented at an input to high Speed signal conver
`sion device 10, at a frequency of approximately 160-170
`Megahertz.
`On a first rising edge of the pixel clock a first data value
`ID is valid on common input channel 74. On a Second rising
`edge of the pixel clock a Second data value ID is valid on
`common input channel 74, and so forth as indicated in FIG.
`2. Timing module 92 generates, in a conventional manner, a
`first phase timing pulse and a Second phase timing pulse
`each having a frequency which is one-half the frequency of
`the pixel clock, respectively shown in FIG.3 at numerals 46,
`50 and 48, 52.
`Also, the first and Second phase timing pulses are 180
`degrees out of phase with each other. Finally, the timing
`pulse signals are slightly delayed with respect to the pixel
`clock So that valid data values are present on common input
`line 74 whenever a rising edge-transition occurs on the pixel
`clock, and So that either the first phase signal is high or the
`Second phase Signal is high during a given rising edge
`transition of the pixel clock. This Scheme uses the first and
`Second phase signal levels to enable the first input latch 24
`or the Second input latch 26 on alternate data values in the
`incoming data Sequence. The first phase timing pulse signal
`appears on lines 46 and 50, while the Second phase timing
`pulse signal appears on lines 48 and 52. Alternatively, the
`latches 24 and 26 could be edge triggered by an edge
`transition of the first or Second phase timing Signals, respec
`tively.
`First input latch 24 and second input latch 26 each
`capture, or latch, alternate values from common input line
`74 in response to rising edge-transitions of the pixel clock,
`enabled by a high logic level of either first phase timing
`pulse line 46 or second phase timing pulse line 48. With
`reference to FIG. 2, the arrangement of the pixel clock
`periods and phase timing pulses is Such that, during a first
`period of the pixel clock, a first data value ID is latched
`from common input line 74 into first input latch 24. During
`a second period of the pixel clock, a Second data value ID
`is latched from common input line 74 into Second input latch
`26. In this fashion, the first and second input latches 24 and
`26 alternatingly latch odd and even numbers of data values
`from the input time Sequence of data values.
`Once latched, a data value is provided at the outputs of
`first and Second input latches for two cycles of the pixel
`clock, as shown in FIG. 3. In particular, reference is made to
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`45
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`50
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`55
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`60
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`65
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`8
`the Signal appearing on first input channel 76 and Second
`input channel 78, which prolong the availability of data
`values ID at the address ports AD1 and AD2 of memory
`device 22.
`Memory device 22 has an acceSS or conversion time
`asSociated with a data value conversion in each channel. A
`first channel access or conversion time 104 and a Second
`channel access or conversion time 106 are shown in FIG. 2.
`The access or conversion time is the time it takes before
`valid output data appears at a memory device 22 data port
`OD1 or OD2, after receiving a valid address port input value
`at AD1 or AD2, respectively.
`In FIG.2, access or conversion operations within memory
`device 22 are shown by vertical arrows 96, 98, 100, and 102.
`The access or conversion operations 96, 98, 100, and 102
`respectively terminate with a valid output data value OD,
`OD, OD, and ODI appearing on first and Second output
`channels 80 and 82 at the conclusion of an access or
`conversion time 104 or 106. Also, the conversions for odd
`and even values are time-staggered in the two channels.
`From FIG. 2 it can be seen that acceSS or conversion times
`104 and 106 both exceed the time of a single pixel clock
`period. This means that the input time Sequence of values is
`changing at a rate which is faster than a rate at which
`memory device 22 would ordinarily be able to properly
`convert the values to valid output data. The latching and
`timing Scheme herein discussed allows for the conversion of
`values at a rate in excess of the conversion rate in either
`channel of memory device 22.
`Converted output values are latched in a similar manner.
`First output latch 28 and second output latch 30 each
`capture, or latch, a value from respective data ports OD1,
`OD2 of memory device 22 over first output channel 80 and
`Second output channel 82, in response to a rising edge
`transition of the pixel clock, in conjunction with the Signal
`levels on first phase timing pulse line 50 and on second
`phase timing pulse line 52. With reference to FIG. 2, it is
`Seen that output data values are respectively latched into first
`and second output latches 28 and 30 a fixed number of pixel
`clock periods (two cycles) after input data values are latched
`in first and second input latches 24 and 26. In this fashion,
`the first and second input latches 24 and 26, and the first and
`second output latches 28 and 30, alternatingly latch odd and
`even numbers of data values.
`Once latched, an output data value is provided at the
`outputs of first and second output latches 28 and 30 for two
`cycles of the pixel clock, as shown in FIG. 2. In particular,
`reference is made to the Signal appearing on first latched
`output channel 84 and second latched output channel 86,
`which prolong the availability of output data values OD, at
`the respective inputs to first multiplexer 32.
`Timing module 92 also generates, in conventional
`fashion, a first Select pulse signal which is provided to a
`select input of first multiplexer 32 on first select pulse line
`54. Referring to FIG. 3, the first select pulse signal on select
`pulse line 54 is preferably generated to be one-half the
`frequency of the pixel clock and preferably has level
`transitions in phase with