US007203829B2
`
`(12) United States Patent
`US 7,203,829 B2
`(10) Patent N0.:
`
` Lim (45) Date of Patent: Apr. 10, 2007
`
`
`(54) APPARATUS AND METHOD FOR
`INITIALIZING COPROCESSOR FOR USE IN
`
`(52) US. Cl.
`
`.............................. 713/2; 713/1; 713/100;
`717/168
`
`SYSTEM COMPRISED 0F MAIN
`PROCESSOR AND COPROCESSOR
`
`(58) Field of Classification Search ..................... None
`See application file for complete search history.
`
`(75)
`
`Inventor: Chae-Whan Lim, Daegu (KR)
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Suwon—si (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 326 days.
`
`(21) Appl. N0.: 10/864,459
`
`(22)
`
`Filed:
`
`Jun. 10, 2004
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`US 2004/0255111 A1
`
`Dec. 16, 2004
`
`Foreign Application Priority Data
`
`Jun. 13, 2003
`
`(KR)
`
`...................... 10-2003 -0038386
`
`(51)
`
`Int. Cl.
`G06F 9/22
`G06F 9/44
`G06F 15/1 77
`
`(2006.01)
`(2006.01)
`(2006.01)
`
`START
`
`6/2001 Hayashi ...................... 711/147
`6,253,233 B1*
`6,330,658 B1* 12/2001 Evoy et a1.
`............
`712/31
`
`6,400,717 B1*
`6/2002 Von Ahnen et al.
`714/36
`............ 711/148
`6,604,189 B1 *
`8/2003 Zemlyak et a1.
`........... 717/168
`2002/0170051 A1* 11/2002 Watanabe et al.
`
`* cited by examiner
`
`Primary Examinerilames K. Trujillo
`(74) Attorney, Agent, or FirmiRoylance, Abrams, Berdo &
`Goodman, L.L.P.
`
`(57)
`
`ABSTRACT
`
`An apparatus and method for initializing a coprocessor for
`use in system comprised of a main processor and coproces-
`sor. The apparatus can be provided with fewer required
`memory components, such as a NOR flash memory, by
`enabling a coprocessor to perform a booting function upon
`receiving a control signal from the main processor.
`
`20 Claims, 12 Drawing Sheets
`
`POWER 0N7 “
`YES
`INITIALIZE COPROCESSOR USING
`BOOT PROGRAM OF INTERNAL ROM
`
`353
`
`COMMUNICATE WITH MAIN PROCESSOR
`USING LOADER PROGRAM OF INTERNAL ROM
`
`355
`
`REQUEST TINY FLASH FILE SYSTEM
`TRANSMISSION FROM MAIN PROCESSOR
`
`357
`
`
`
`
`
`
`
`
`INY FLASH FILE SYSTE
`RECEIVED?
`YES
`STORE RECEIVED TINY FLASH
`36‘
`FILE SYSTEM IN INTERNAL RAM
`
`
`MOVE/STORE PROGRAM CODE STORED IN
`SECOND FLASH MEMORY OF COPROCESSOR
`
`USING TINY FLASH FILE SYSTEM IN INTERNAL RAM
`
`
`
`
`
`363
`
`
`COMMAND COPROCESSOR'S PC To JUMP TO
`ENTRANCE POINT OF LOADED CODE AREA
`
`OPERATE COPROCESSOR
`
`
`
`369
`
`
`
`INTEL 1214
`
`INTEL 1214
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 1 0f 12
`
`US 7,203,829 B2
`
`100
`
`200
`
`MAIN
`PROCESSOR
`
`COPROCESSOR
`
`FIRST FLASH
`MEMORY
`
`FIRST FLASH
`MEMORY
`
`110
`
`SECOND FLASH
`MEMORY
`
`SECOND FLASH
`
`210
`
`220
`
`
`
`‘TIE.“ 130 PERIPHERAL
`
`DEVICES
`
`I
`. l
`PERIPHERAL
`DEVICES
`
`140
`
`(PRIOR ART)
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 2 0f 12
`
`US 7,203,829 B2
`
`1 00
`
`200
`
`MAIN
`
`COPROCESSOR
`PROCESSOR -
`
`
`
`
`SECOND FLASH
`
`220
`
`230
`
`240
`
`MEMORY
`
`
`
`FIRST FLASH
`
`MEMORY
`
`SECOND FLASH
`
`MEMORY
`
`
`OTHER
`PERIPHERAL
`
`DEVICES
`
`
`130
`
` OTHER
`PERIPHERAL
`DEVICES
`
`i
`
`140
`
`FIG.2
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 3 of 12
`
`US 7,203,829 B2
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`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 4 0f 12
`
`US 7,203,829 B2
`
`START
`
`POWER ON? “
`
`YES
`
`INITIALIZE COPROCESSOR USING
`
`BOOT PROGRAM OF INTERNAL ROM
`
`
`
`w Y
`
`ES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO
`ENTRANCE POINT OF LOADED CODE AREA
`
`OPERATE COPROCESSOR
`
`.
`
`I
`
`319
`
`321
`
`FIGA
`
`MOVE/STORE PROGRAM CODE STORED ‘
`IN SECOND FLASH MEMORY OF
`'
`
`COPROCESSOR USING TINY FLASH FILE
`
`SYSTEM OF INTERNAL ROM IN INTERNAL RAM
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 5 0f 12
`
`US 7,203,829 B2
`
`POWER ON?I
`
`YES
`
`INITIALIZE COPROCESSOR USING
`BOOT PROGRAM OF INTERNAL ROM
`
`353
`
`COMMUNICATE WITH MAIN PROCESSOR
`
`USING LOADER PROGRAM OF INTERNAL ROM
`
`REQUEST TINY FLASH FILE SYSTEM
`TRANSMISSION FROM MAIN PROCESSOR
`
`TINY FLASH FILE SYSTEM
`RECEIVED?
`
`YES
`
`361II
`
`STORE RECEIVED TINY FLASH
`FILE SYSTEM IN INTERNAL RAM
`
`MOVE/STORE PROGRAM CODE STORED IN
`SECOND FLASH MEMORY OF COPROCESSOR
`USING TINY FLASH FILE SYSTEM IN INTERNAL RAM
`
`
`
`
`
`¢ Y
`
`ES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO '
`
`ENTRANCE POINT OF LOADED CODE AREA
`
`'
`
`FIGS
`
`OPERATE COPROCESSOR
`
`369
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 6 of 12
`
`US 7,203,829 B2
`
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`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 7 0f 12
`
`US 7,203,829 B2
`
`POWER ON? “
`
`INITIALIZE COPROCESSOR USING
`
`BOOT PROGRAM OF INTERNAL ROM
`
`w
`
`MOVE/STORE PROGRAM CODE STORED IN SECOND
`
`FLASH MEMORY OF COPROCESSOR USING TINY FLASH
`
`FILE SYSTEM OF INTERNAL ROM IN EXTERNAL RAM
`
`YES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO
`ENTRANCE POINT OF LOADED CODE AREA
`
`4‘ 9
`
`OPERATE COPROCESSOR
`
`;
`
`421
`
`FIG.7
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 8 of 12
`
`US 7,203,829 B2
`
`START
`
`POWER ON?I
`
`YES
`
`INITIALIZE COPROCESSOR USING
`BOOT PROGRAM OF INTERNAL ROM
`
`COMMUNICATE WITH MAIN PROCESSOR USING
`LOADER PROGRAM OF INTERNAL ROM
`
`REQUEST TINY FLASH FILE SYSTEM
`TRANSMISSION FROM MAIN PROCESSOR
`
`-P4>A0'!(.110'1\I(II00
`
`TINY FLASH FILE SYSTEM
`RECEIVED?
`
`YES
`
`STORE RECEIVED TINY
`FLASH FILE SYSTEM IN EXTERNAL RAM
`
`461
`
`MOVE/STORE PROGRAM CODE STORED lN SECOND
`FLASH MEMORY OF COPROCESSOR USING
`TINY FLASH FILE SYSTEM IN EXTERNAL RAM
`
`465
`
`
`
`
`
`w Y
`
`ES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO ‘
`
`ENTRANCE POINT OF LOADED CODE AREA
`
`OPERATE COPROCESSOR
`
`'
`
`469
`
`FIGS
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 9 of 12
`
`US 7,203,829 B2
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`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 10 of 12
`
`US 7,203,829 B2
`
`START
`
`POWER ON? “
`
`YES
`
`COPROCESSOR'S STANDBY MODE &
`COPROCESSOR'S INTERNAL RAM INITIALIZED
`BY MAIN PROCESSORS INTERNAL RAM
`
`5‘3
`
`
`
`
`RECEIVE BOOT AND TINY FLASH FILE
`
`
`SYSTEM CODE FILES OF MAIN PROCESSOR'S
`
`
`INTERNAL ROM, & MOVE/STORE RECEIVED
`
`
`CODE FILES IN COPROCESSOR'S INTERNAL RAM
`
`
`
`¢ Y
`
`ES
`
`COMMAND COPROCESSOR TO JUMP
`TO ENTRANCE POINT OF BOOT AND
`TINY FLASH FILE SYSTEM CODE AREA
`
`519
`
`INITIALIZE COPROCESSOR
`
`521
`
`
`
`LOAD PROGRAM CODE STORED IN SECOND
`FLASH MEMORY OF COPROCESSOR IN
`
`INTERNAL RAM USING TINY FLASH FILE SYSTEM
`
`
`
`w Y
`
`ES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO
`ENTRANCE POINT OF LOADED CODE AREA
`
`527
`
`OPERATE COPROCESSOR
`
`529
`
`FIG.1O
`
`

`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 11 0f 12
`
`US 7,203,829 B2
`
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`

`U.S. Patent
`
`Apr. 10, 2007
`
`Sheet 12 0f 12
`
`US 7,203,829 B2
`
`START
`
`POWER ON? “
`
`YES
`
`COPROCESSOR'S STANDBY MODE &
`COPROCESSOR'S EXTERNAL RAM INITIALIZED
`BY MAIN PROCESSOR'S INTERNAL RAM
`
`613
`
`
`RECEIVE BOOT AND TINY FLASH FILE
`SYSTEM CODE FILES OF MAIN PROCESSOR'S
`INTERNAL ROM, & MOVE/STORE RECEIVED
`CODE FILES IN COPROCESSOR'S EXTERNAL RAM
`
`
`
`
`¢ Y
`
`ES
`
`COMMAND COPROCESSOR TO JUMP
`
`TO ENTRANCE POINT OF BOOT AND
`TINY FLASH FILE SYSTEM CODE AREA
`
`619
`
`INITIALIZE COPROCESSOR
`
`.
`
`621
`
`LOAD PROGRAM CODE STORED IN SECOND
`
`
`
`FLASH MEMORY OF COPROCESSOR IN
`EXTERNAL RAM USING TINY FLASH FILE SYSTEM
`
`
`
`
`
`YES
`
`COMMAND COPROCESSOR'S PC TO JUMP TO
`ENTRANCE POINT OF LOADED CODE AREA
`
`OPERATE COPROCESSOR
`
`629
`
`FIG' 1 2
`
`

`

`US 7,203,829 B2
`
`1
`APPARATUS AND METHOD FOR
`INITIALIZING COPROCESSOR FOR USE IN
`SYSTEM COMPRISED OF MAIN
`PROCESSOR AND COPROCESSOR
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application claims the benefit under 35 U.S.C. §
`119(a) of Korean Patent Application No. 2003-38386
`entitled “APPARATUS AND METHOD FOR INITIALIZ-
`ING COPROCESSOR FOR USE IN SYSTEM COM-
`PRISED OF MAIN PROCESSOR AND COPROCES-
`
`SOR”, filed in the Korean Intellectual Property Oflice on
`Jun. 13, 2003, the entire contents of which are incorporated
`herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to an apparatus and method
`for booting a controller. More particularly,
`the present
`invention relates to an apparatus and method for booting a
`coprocessor for use in a system comprised of a main
`processor and a coprocessor.
`2. Description of the Related Art
`Typically, in a system comprised of a main processor and
`a coprocessor, the main processor controls overall opera-
`tions of the system, and the coprocessor controls a specific
`function upon receiving a control signal from the main
`processor. The aforementioned system has been widely used
`in mobile terminals having current hybrid functions. For
`example,
`in the case of a mobile terminal provided for
`processing current video signals, a main processor controls
`overall operations of a communication or mobile terminal,
`and a coprocessor performs the processing of video signals
`upon receiving a control signal from the main processor. The
`aforementioned mobile terminal can be provided with any
`number of devices, such as a mobile terminal for a cam-
`corder, a PDA (Personal Digital Assistant), a VOD (Video
`On Demand) phone, and similar devices.
`A representative example of the aforementioned system,
`including the main processor and the coprocessor, is shown
`in FIG. 1. The following detailed description will hereinafter
`be described with reference to FIG. 1 in which, the example
`of the aforementioned system is provided as a mobile
`terminal.
`
`the main processor 100 controls
`Referring to FIG. 1,
`communication and overall operations of the mobile termi-
`nal. A first flash memory 110 is comprised of a NOR flash
`memory for storing boot and loader programs and main
`operation programs of the main processor 100. A second
`flash memory 120 is comprised of a NAND flash memory
`for storing large amounts of nonvolatile data, for example,
`content data, font data, bitmap data, phonebook data, and
`similar data.
`
`The second flash memory 120 has a limited number of
`correction times associated with the same area, such that
`encounters with an unexpected error in a specified area
`results in an outcome wherein data cannot be recorded or
`
`stored any further in the second flash memory 120. There-
`fore, a flash file system is adapted to access data of the flash
`memory (i.e., 110 and 120). RAM (Random Access
`Memory) 130 can be adapted to function as a work memory
`for use in the main processor 100. Other peripheral devices
`140 are comprised of devices operated by a control signal
`generated from the main processor 100. In this case, the
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`
`peripheral devices 140 can be keypads, displays, RF (Radio
`Frequency) units, communication units, and similar devices.
`Upon receiving a control signal from the main processor
`100, the coprocessor 200 assumes direction of a specific
`function, and processes the specific function. An additional
`first flash memory 210 is comprised of a NOR flash memory
`for storing boot and loader programs and main operation
`programs of the coprocessor 200. An additional second flash
`memory 220 is comprised of a NAND flash memory for
`storing large amounts of nonvolatile data, for example,
`content data associated with functions of the coprocessor
`200. RAM 230 can be adapted as a work memory of the
`coprocessor 200. Other peripheral devices 240 are com-
`prised of devices operated by a control signal generated
`from the coprocessor 200. In this case, if the mobile terminal
`is a camcorder, the peripheral devices 240 can be devices
`such as multimedia codecs, cameras, displays (e.g., LCDs),
`and similar devices. Content data stored in the second flash
`
`memory 220 can then include video-processed and similar
`data. If the mobile terminal is a PDA terminal, substantially
`all the applications, other than a communication function,
`can be provided by the peripheral devices 240.
`The first flash memories 110 and 210 each can be pro-
`vided as a NOR flash memory. The second flash memories
`120 and 220 can be provided as a NAND flash memory.
`As stated above, the main processor 100 and the copro-
`cessor 200 each include a memory unit comprised of NOR
`and NAND flash memories and RAMs. Therefore, the main
`processor 100 and the coprocessor 200 must each include
`the aforementioned memories, resulting in increased hard-
`ware installation space and increased production cost.
`Therefore,
`it is preferable for either one of the NOR and
`NAND flash memories to be removed.
`
`The NOR flash memory is very expensive, and where it
`is configured in the form of a stable configuration,
`it can
`store boot and loader programs and flash file systems. The
`NAND flash memory has advantages in that it is relatively
`cheaper than the NOR flash memory, and has excellent
`capacity which is higher than that of the NOR flash memory.
`However, the NAND flash memory has a relatively-high
`probability of creating bad sectors in the memory, in which
`the memory stores content data for use in a corresponding
`device. Therefore, when storing the boot and loader pro-
`grams and flash filter systems in the NAND flash memory,
`it is impossible to perform operations of an overall system
`if unexpected bad sectors occur in a specific area for storing
`the programs.
`Accordingly, a need exists for an improved system for
`stably accessing the boot and loader programs and the flash
`file systems in devices wherein the costly NOR flash
`memory is removed.
`
`SUMMARY OF THE INVENTION
`
`Therefore, the embodiments of the present invention have
`been made in view of the above problems, and it is an object
`of the present invention to provide an apparatus and method
`for removing a relatively high-priced NOR flash memory
`from a coprocessor,
`in a system comprised of a main
`processor and the coprocessor, and enabling the coprocessor
`to perform a booting function upon receiving a control
`signal from the main processor.
`It is another object of the present invention to provide an
`apparatus and method for enabling a coprocessor having no
`NOR flash memory to perform a booting frmction using
`boot/loader programs stored in an internal ROM and a tiny
`
`

`

`US 7,203,829 B2
`
`3
`flash file system, in a system comprised of a main processor
`and the coprocessor including a ROM and a RAM.
`It is yet another object of the present invention to provide
`an apparatus and method for enabling a coprocessor having
`no NOR flash memory to perform a booting function using
`boot/loader programs stored in an internal ROM and a tiny
`flash file system stored in a NOR or NAND flash memory of
`a main processor,
`in a system comprised of the main
`processor and the coprocessor including a ROM and a RAM.
`It is yet another object of the present invention to provide
`an apparatus and method for enabling a coprocessor having
`no NOR flash memory to perform a booting function using
`boot/loader programs stored in an internal ROM and a tiny
`flash file system in a system comprised of a main processor
`and the coprocessor including only ROM.
`It is yet another object of the present invention to provide
`an apparatus and method for enabling a coprocessor having
`no NOR flash memory to perform a booting function using
`boot/loader programs stored in an internal ROM and a tiny
`flash file system stored in a NOR or NAND flash memory of
`a main processor,
`in a system comprised of the main
`processor and the coprocessor including only ROM.
`It is yet another object of the present invention to provide
`an apparatus and method for enabling a coprocessor having
`no NOR flash memory to perform a booting function using
`boot/loader programs and a tiny flash file system that are all
`stored in a NOR or NAND flash memory of a main proces-
`sor, in a system comprised of the main processor and the
`coprocessor and having no internal ROM.
`It is yet another object of the present invention to provide
`an apparatus and method for enabling a coprocessor having
`no NOR flash memory to perform a booting function using
`boot/loader programs and a tiny flash file system, that are all
`stored in a NOR or NAND flash memory of a main proces-
`sor, in a system comprised of the main processor and the
`coprocessor and having no internal ROM and RAM.
`In accordance with the embodiments of the present inven-
`tion, the above and other objects can be accomplished by
`providing an apparatus including a main device and an
`auxiliary device, comprising in part, the following compo-
`nents.
`
`The main device can include a main processor, including
`a ROM (Read Only Memory) and a RAM (Random Access
`Memory), for controlling overall operations of the main
`device, a first flash memory for storing principal programs
`of the main device, a second flash memory for storing
`content data of the main device, and a RAM acting as a work
`memory of the main device.
`The auxiliary device can include a second flash memory
`for storing principal programs and content data of the
`auxiliary device, an external RAM acting as a work memory
`of the auxiliary device, and a coprocessor for including a
`ROM and a RAM which store boot, loader, and tiny flash file
`system code files. The coprocessor is further provided for
`booting the auxiliary device using a boot program stored in
`the internal ROM when it is initially powered on by the main
`processor. The coprocessor is still further provided for
`controlling a loader program to load principal programs
`stored in the second flash memory by operating the tiny flash
`file system, and for controlling the operations of the auxil-
`iary device.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above and other objects, features and other advan-
`tages of the present invention will be more clearly under-
`
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`stood from the following detailed description taken in con-
`junction with the accompanying drawings, in which:
`FIG. 1 is a block diagram illustrating a conventional
`system comprised of a main processor and a coprocessor;
`FIG. 2 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with an
`embodiment of the present invention;
`FIG. 3 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with a
`first exemplary embodiment of the present invention;
`FIG. 4 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the copro-
`cessor of FIG. 3 includes a boot program and a tiny flash file
`system in accordance with the first embodiment of the
`present invention;
`FIG. 5 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the copro-
`cessor includes boot and loader programs and the other
`internal ROM of the main processor includes a tiny flash file
`system in accordance with the first embodiment of the
`present invention;
`FIG. 6 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with a
`second exemplary embodiment of the present invention;
`FIG. 7 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the copro-
`cessor of FIG. 6 includes a boot program and a tiny flash file
`system in accordance with the second embodiment of the
`present invention;
`FIG. 8 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the copro-
`cessor includes boot and loader programs and the other
`internal ROM of the main processor includes a tiny flash file
`system in accordance with the second embodiment of the
`present invention;
`FIG. 9 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with a
`third exemplary embodiment of the present invention;
`FIG. 10 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the main
`processor of FIG. 9 includes a boot program and a tiny flash
`file system in accordance with the third embodiment of the
`present invention;
`FIG. 11 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with a
`fourth exemplary embodiment of the present invention; and
`FIG. 12 is a flow chart illustrating a booting procedure for
`use in a coprocessor when an internal ROM of the main
`processor of FIG. 11 includes a boot program and a tiny flash
`file system in accordance with the third embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`EXEMPLARY EMBODIMENTS
`
`invention will be
`The embodiments of the present
`described in detail with reference to the annexed drawings.
`In the drawings, the same or similar elements are denoted by
`the same reference numerals even though they are depicted
`in different drawings. In the following description, a detailed
`description of known functions and configurations incorpo-
`rated herein will be omitted when it may make the subject
`matter of the present invention unclear.
`it should be
`Prior to describing the present invention,
`noted that the following terms will hereinafter be used in the
`detailed description of the embodiments of the present
`invention.
`
`

`

`US 7,203,829 B2
`
`5
`The coprocessor is comprised of a processor for operating
`application programs or specific functions requiring a high
`speed, for example, a GUI (Graphic User Interface), a
`multimedia codec, and similar devices.
`be main processor is comprised of a processor for
`controlling overall operations of a system. For example,in
`the case of a mobile terminal, an MSM chip may be adapted
`as the main processor.
`The boot module is comprised of a software module for
`initializing operations of a controller to enter a main soft-
`ware routine.
`
`The loader module is comprised of a software module for
`initializing a number of necessary modules after performing
`a booting function, and moving the remaining main software
`coce parts to a specific memory area capable of operating a
`controller.
`
`
`
`The boot-loader module is comprised of a software mod-
`ule wherein the boot module and the loader module are
`
`integrated in one module.
`The flash file system is comprised of a software module
`for writing data on a NAND flash memory or reading data
`from the NAND flash memory without generating errors.
`he tiny flash file system is comprised of a minimum
`sofware module for reading data from the NAND flash
`me nory without generating errors.
`It should be noted that
`the aforementioned flash file
`
`system and the tiny flash file system can be separately
`adapted to the present invention. Specifically, the tiny flash
`file system is comprised of a flash file system having a
`minimum data read function that is capable of guaranteeing
`integrity of data stored in the NAND flash memory. The
`flash file system is comprised of a file system for overcom-
`ing a variety of problems,
`for example, a problem of
`generating bad sectors of the NAND flash memory, and an
`aging problem generated when a specific position is repeat-
`edly used such that further corrections (i.e., higher than a
`predetermined number of correction times) are made
`unavailable. In doing so, the flash file system can be used for
`stably writing or reading data on/from a memory. The tiny
`flash file system can be used where a memory is an equiva-
`len to a NAND flash memory A detailed description of the
`NOR flash memory is described1n greater detail below.
`he first flash memory is comprised of a NOR flash
`me nory.
`The second flash memory is comprised of a NAND flash
`me nory.
`The embodiments of the present invention remove a flash
`me nory for storing initialization information of a coproces-
`sor from a system, the system including a main processor
`anc the coprocessor, and stores initialization information of
`the coprocessor in either another memory of the coproces-
`sor, or a memory of the main processor, such that the system
`initialization is established. The memory can be either one of
`a ROM, a RAM,
`first and second flash memories, and
`similar devices. The initialization information can be either
`
`
`
`one of a boot program module, a loader program, a boot
`loader program, and a tiny flash file system of the copro-
`cessor.
`
`In the implementation of the aforementioned configura-
`tions, a main device for use in the embodiments of the
`present invention can include a main processor for operating
`overall operations of the main device, a first flash memory
`for storing the principal programs of the main processor, and
`a second flash memory for storing content data of the main
`processor. An auxiliary device for use in the embodiments of
`the present invention can include a coprocessor for control-
`ling overall operations of the auxiliary device, and a second
`
`6
`flash memory for storing the principal programs and content
`data of the auxiliary device. Initialization information of the
`auxiliary device, for example, a boot program, a loader
`program, a boot-loader program, and tiny flash file systems,
`can be stored in an internal ROM of the coprocessor, an
`internal ROM of the main processor, the first flash memory
`or the second flash memory. A detailed description of the
`aforementioned initialization information is described in
`
`greater detail below with reference to the following pre-
`ferred embodiments.
`for
`initialization information,
`The
`aforementioned
`example, a boot program, a loader program, a boot-loader
`program, and a tiny flash file system, can be stored in the
`coprocessor’s ROM, the main processor’s ROM and/or the
`main processor’s flash memory. The flash memory of the
`main processor can be comprised of NOR and NAND flash
`memories. The boot program, the loader program, the boot-
`loader program, and the tiny flash file systems are comprised
`of programs operated in the coprocessor.
`In accordance with the system initialization operations for
`use in the system, which is comprised of the main device and
`the auxiliary device, a system booting operation can be
`performed by a boot program stored in the main processor’s
`memory or the coprocessor’s internal ROM, and the prin-
`cipal programs stored in the second flash memory of the
`coprocessor are loaded by the tiny flash file system, such that
`operations of the auxiliary device can be performed.
`FIG. 2 is a block diagram illustrating a system comprised
`of a main processor and a coprocessor in accordance with an
`embodiment of the present invention. Specifically, FIG. 2 is
`a block diagram of a system for removing a first flash
`memory from the coprocessor 200.
`Referring to FIG. 2, the remaining block diagram con-
`figurations, from which the first flash memory is removed
`from the coprocessor 200, are equal to those of FIG. 1. In
`this case,
`the first flash memory 110,
`the second flash
`memory 120, external RAM 130, and other peripheral
`devices 140 are driven by a control signal received from the
`main processor 100. The first flash memory 110 is comprised
`of a memory for storing a boot module, a loader module, a
`flash file system, and other execution program modules of
`the main processor 100. The second flash memory 120 is
`comprised of a memory for storing nonvolatile data gener-
`ated by a control signal of the main processor 100, for
`example, content data, font data, bit data, phonebook data,
`and similar data. The main processor 100 performs its
`initialization operation using individual software modules
`stored in the first flash memory 110 when it
`is initially
`powered on, and provides the coprocessor 200 with a
`power-supply voltage such that it is able to initialize the
`coprocessor 200.
`In this case, the first flash memory is removed from the
`coprocessor 200. This first flash memory removed from the
`coprocessor 200 is comprised of a memory for storing a boot
`module, a loader module, a flash file system, and other
`coprocessors’ program modules. Therefore, the embodiment
`of the present invention shown in FIG. 2 distributes the boot
`module,
`the loader module, and a tiny flash file system
`needed to read the data of the NAND flash memory from
`among the flash file system, and stores the above distributed
`parts in another memory. Further, upon receiving a control
`signal from the main processor 100, the embodiment of the
`present invention initializes the coprocessor 200, and loads/
`operates the remaining program modules, including a flash
`file system, using a tiny flash file system.
`In accordance with a first exemplary embodiment of the
`present invention which is capable of removing the first flash
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`US 7,203,829 B2
`
`7
`memory from the coprocessor 200, the coprocessor 200 can
`perform its booting operation under the following two cases,
`i.e., a first case in which the coprocessor 200 includes
`internal ROM and RAM and the internal ROM includes a
`
`8
`Referring to FIG. 4, if the coprocessor 200 is powered on
`when the main processor 100 is initialized, it detects the
`powered-on state at step 311, and gains access to the boot
`module stored in the internal ROM 203 such that
`the
`
`boot module, a loader module, and a tiny flash file system,
`and a second case in which the internal ROM includes only
`boot and loader modules and a tiny flash file system of the
`coprocessor 200 is included in either the first flash memory
`110 or the second flash memory 120.
`In accordance with a second exemplary embodiment of
`the present invention, the coprocessor 200 can perform its
`booting operation under the following two cases, i.e., a first
`case in which the coprocessor 200 includes an internal ROM
`and the internal ROM includes a boot module, a loader
`module, and a tiny flash file system, and a second case in
`which the internal ROM includes only boot and loader
`modules and a tiny flash file system of the coprocessor 200
`is included in either the first flash memory 110 or the second
`flash memory 120.
`In accordance with the first exemplary embodiment of the
`present invention, a RAM is included in the coprocessor, and
`a tiny flash file system is stored in the internal RAM of the
`coprocessor.
`In accordance with the second exemplary
`embodiment of the present invention, a RAM is not included
`in the coprocessor, but is stored in an external RAM of the
`coprocessor.
`In accordance with a third exemplary embodiment of the
`present
`invention,
`the coprocessor 200 can perform its
`booting operation in the case where it includes only a RAM,
`and wherein either the first flash memory 110 or the second
`flash memory 120 of the main processor 100 includes a boot
`module, a loader module, and a tiny flash file system of the
`coprocessor 200.
`In accordance with a fourth exemplary embodiment of the
`present
`invention,
`the coprocessor 200 can perform its
`booting operation in the case where it does not include a
`RAM and a ROM, and wherein either the first flash memory
`110 or the second flash memory 120 of the main processor
`100 includes a boot module, a loader module, and a tiny
`flash file system of the coprocessor 200.
`FIG. 3 is a block diagram illustrating an overall system
`associated with the aforementioned case in which the ROM
`
`203 and the RAM 205 are included in the coprocessor 200
`in a system comprised of the main processor 100 and the
`coprocessor 200.
`Referring to FIG. 3, the coprocessor 200 includes the
`ROM 203 and the RAM 205. The internal ROM 203 stores
`
`a boot module, a loader module, and a tiny flash file system
`of the coprocessor 200, as denoted by ‘boot+loader+tiny
`flash file system’. Also, the boot module and the loader
`module are stored in the internal ROM 203, as denoted by
`‘boot+loader’. The tiny flash file system of the coprocessor
`200 is stored in either the first flash memory 110 or the
`second flash memory 120 of the main processor 100.
`FIG. 4 is a flow chart illustrating an initialization proce-
`dure of the coprocessor 200 in the case where the ROM 203
`and the RAM 205 are included in the coprocessor 200, and
`the internal ROM 203 stores a boot module, a loader
`module, and a tiny flash file system of the coprocessor 200.
`FIG. 5 is a flow chart illustrating an initialization procedure
`of the coprocessor 200 in the case where the ROM 203 and
`the RAM 205 are included in the coprocessor 200,
`the
`internal ROM 203 stores the boot and loader modules, and
`the tiny flash file system of the coprocessor 200 is stored in
`either the first flash memory 110 or the second flash memory
`120.
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`coprocessor 200 is initialized at step 313. A loader module
`of the coprocessor 200, which is provided for storing the
`loader module in the second flash memory 220, reads a
`program code of the coprocessor 200 using a tiny flash file
`system of the internal ROM 203, and the read program data
`is stored in the internal RAM 205 at step 315.
`The aforementioned operations are repeated until a code
`that is capable of performing basic operations i