UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`
`____________________________________________
`Trial No. IPR2018-013341
`____________________________________________
`REPLY DECLARATION OF BILL LIN, PH.D. ON REMAND
`ON BEHALF OF PETITIONER
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
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`proceeding.
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`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1027
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`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`
`____________________________________________
`Trial No. IPR2018-013341
`____________________________________________
`REPLY DECLARATION OF BILL LIN, PH.D. ON REMAND
`ON BEHALF OF PETITIONER
`
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
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`proceeding.
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`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1027
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`
`QUALIFICATIONS ........................................................................................ 2
`
`PATENT OWNER’S “HARDWARE BUFFER” CONSTRUCTION IS
`WRONG. ......................................................................................................... 2
`Patent Owner’s Construction Is Not Supported by the
`Patent Specification. .............................................................................. 2
`Patent Owner’s Construction of “Hardware Buffer” Is
`Not Required for the Alleged Advance of the ’949 Patent
`Identified by Patent Owner. .................................................................. 6
`PETITIONER’S PROPOSED CONSTRUCTION OF “HARDWARE
`BUFFER” IS CORRECT. ............................................................................. 19
`
`I.
`II.
`III. RELEVANT LAW .......................................................................................... 2
`IV.
`A.
`B.
`V.
`VI. UNDER EITHER PROPOSED CONSTRUCTION, THE PRIOR ART
`VII. CONCLUSION ............................................................................................. 24
`VIII. AVAILABILITY FOR CROSS-EXAMINATION ...................................... 24
`IX. RIGHT TO SUPPLEMENT .......................................................................... 25
`X.
`
`DISCLOSES A “HARDWARE BUFFER.” ................................................. 22
`
`JURAT ........................................................................................................... 25
`
`i
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`1. I, Bill Lin, Ph.D. declare as follows:
`
`I.
`
`INTRODUCTION
`I have been retained by Intel Corporation (“Intel” or “Petitioner”) as
`2.
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`an independent expert consultant in this proceeding before the United States Patent
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`and Trademark Office. I previously prepared and submitted my Opening
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`Declarations in support of the Petitions in IPR2018-013342, IPR2018-01335, and
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`IPR2018-01336, dated July 2, 2018 and July 3, 2018 (Exs. 1002, 1020, and 1021).
`
`I also submitted my Reply Declaration (Ex. 1023) on September 27, 2019 and my
`
`Opening Remand Declaration (Ex. 1026) on April 6, 2022. I submit this
`
`Declaration in support of Petitioner’s Reply Brief on Remand.
`
`3.
`
`Since preparing my Opening, Reply, and Opening Remand
`
`Declarations, I have also reviewed the following materials:
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`• Patent Owner’s Response Brief on Remand (Paper 37);
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`• Exhibits 2011–2014 to Response Brief on Remand;
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`• Dr. Rinard’s Response Declaration on Remand (Exhibit 2015);
`
`
`2 Because IPR2018-01335 and IPR2018-01336 have been consolidated with
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`IPR2018-01334, I have cited to exhibits from IPR2018-01334 throughout, unless
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`noted otherwise.
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`1
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`• Any other document cited in this Declaration.
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`4.
`
`I am being compensated for my work on this matter, but my opinions
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`are based on my own views of the patent and the prior art. My compensation in no
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`way depends on the outcome of this proceeding or the content of my testimony.
`
`II. QUALIFICATIONS
`I described my qualifications in my Opening Declarations. Ex. 1002
`5.
`
`(Lin Op. Decl.) at ¶¶ 1-12; Ex. 1020 (Lin Op. Decl. in IPR2018-01335) at ¶¶ 1-11.
`
`III. RELEVANT LAW
`In my first Declarations, I set forth the applicable principles of patent
`6.
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`law that were provided to me by counsel. Ex. 1002 (Lin Op. Decl.) at ¶¶ 16-27;
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`Ex. 1020 (Lin Op. Decl. in IPR2018-01335) at ¶¶ 15-26. As appropriate, I have
`
`continued to apply those principles in providing my opinions in this Declaration.
`
`IV. PATENT OWNER’S “HARDWARE BUFFER” CONSTRUCTION IS
`WRONG.
`Patent Owner’s Construction Is Not Supported by the Patent
`A.
`Specification.
`Patent Owner’s construction of “hardware buffer”—“a permanent,
`
`7.
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`dedicated buffer that is distinct from system memory”—should be rejected for
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`several reasons. Notably, Patent Owner advocates for a construction that amounts
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`to defining a “hardware buffer” as “not a temporary” buffer, a construction that
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`was specifically rejected as “inadequate” by the Federal Circuit. Intel v.
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`2
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`Qualcomm, 21 F.4th 801, 811 (Fed. Cir. 2021). Moreover, this construction should
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`be rejected at least because the ’949 patent specification does not provide support
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`for (1) excluding all temporary buffers from being a “hardware buffer” or (2)
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`preventing the “hardware buffer” from being located on a system memory separate
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`from the claimed “system memory.”
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`8.
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`First, to support the exclusion of all temporary buffers from the
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`construction of “hardware buffer,” Patent Owner cites to various statements in the
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`’949 specification. See PO Resp. Br. (Paper 37) at 5 (citing Ex. 1001, 2:17-55,
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`4:43-47, 5:31-35, 7:16-30, 9:42-50, 11:17-24); see also Ex. 2015 (Rinard Remand
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`Decl.) at ¶¶ 23-26. As already discussed in my Opening Remand Declaration,
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`these statements do not evince an intent to exclude temporary buffers. Ex. 1026
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`(Lin Decl.) at ¶¶ 21-29. Rather, they distinguish only specific uses of a temporary
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`buffer, such as when a temporary stores the entire executable software image. For
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`example, the statement “the direct scatter load technique avoids use of a temporary
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`buffer” is cited by Patent Owner (PO Resp. Br. (Paper 37) at 12 (citing Ex. 1001,
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`4:46-47); see also Ex. 2015 (Rinard Remand Decl.) at ¶ 53) to supposedly
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`demonstrate that the use of a temporary buffer in system memory is distinguished
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`“without qualification.” However, as I explained previously, this statement, when
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`read in the context of the surrounding sentences, teaches against the use of a
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`temporary buffer receiving a packet that includes both a header and data
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`segments. Ex. 1026 (Lin Decl.) at ¶ 27; see also id. at ¶ 25 (explaining use of
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`“temporary buffer” in the ’949 Patent at 2:17-55); id. at ¶ 23-24 (explaining use of
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`“temporary buffer” in the ’949 Patent at 9:42-50); id. at ¶ 28 (explaining use of
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`“temporary buffer” in the ’949 Patent at 5:31-35).
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`9.
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`Further, other ’949 statements cited by Patent Owner (e.g., Ex. 1001
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`at 7:16-30, 11:17-24) discussing the supposed increased efficiency of the ’949
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`scatter loading process are inadequate to demonstrate that the “hardware buffer,”
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`instead of the other aspects of the process, is the asserted advance of the claimed
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`invention. As discussed further in Section IV.B below, the supposedly more
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`efficient scatter loading technique described by Patent Owner does not require the
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`use of a “permanent, dedicated buffer” distinct from any system memory.
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`10. Second, in addition to not limiting the “hardware buffer” to permanent
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`buffers, the ’949 specification does not require that the “hardware buffer” be
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`separate from any system memory other than the claimed “system memory.
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`Though Patent Owner suggests that allowing the “hardware buffer” to be located
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`on a separate system memory would be inconsistent with the purpose of
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`eliminating extra memory copy operations (PO Resp. Br. (Paper 37) at 6-7; see
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`also Ex. 2015 (Rinard Remand Decl.) at ¶¶ 42-43), the ’949 specification does not
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`require that the “hardware buffer” be in a memory that is not in any system
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`memory. That is nothing in the ’949 specification prohibits the “hardware buffer”
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`from being located in a system memory distinct from the claimed “system
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`memory.” Because the Board specifically found in its Final Written Decision that
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`the ’949 patent “does not foreclose the possibility of implementing a [hardware]
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`buffer in some other system memory,” FWD (Paper 30) at 13, Patent Owner’s
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`construction runs contrary to the Board’s decision, which is consistent with the
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`’949 specification.
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`11. Finally, the Patent Owner’s construction fails because it does not
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`allow for any difference in scope between claims 1 and 2. While Patent Owner
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`maintains that claim 2 should be and is narrower than claim 1 (PO Resp. Br. (Paper
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`37) at 11; see also Ex. 2015 (Rinard Remand Decl.) at ¶¶ 43-45), it does not point
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`to any way in which claim 2 is narrower under its construction. Instead, Patent
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`Owner and Dr. Rinard repeatedly refer to objectives of the claimed invention,
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`which Patent Owner and Dr. Rinard state are driven by “the elimination of ‘extra
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`memory copy operations’ in system memory,” and argue that Petitioner’s
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`construction would improperly broaden the scope of claim 1 and other dependent
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`claims. PO Resp. Br. (Paper 37) at 10; see also Ex. 2015 (Rinard Remand Decl.)
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`at ¶¶ 43-45). On the other hand, Patent Owner also argues that claim 2 is narrower
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`than claim 1 because claim 2 “expressly” excludes “copying data between system
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`memory locations on the secondary processor.” Id. However, Patent Owner
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`cannot maintain both positions. Dr. Rinard also states that claim 1 uses the term
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`“data segment” and claim 2 uses the term “data.”. Id. This alleged difference,
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`however, has nothing to do with the scatter loading process, which is limited to
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`data segments. To create a difference between the scope of claims 1 and 2, claim 1
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`must allow for copying between system memory location, as Petitioner’s
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`construction allows.
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`B.
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`Patent Owner’s Construction of “Hardware Buffer” Is Not
`Required for the Alleged Advance of the ’949 Patent Identified by
`Patent Owner.
`12. Patent Owner contends that because the ’949 patent provides “a more
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`efficient loading process” by avoiding “extra memory copy operations” through a
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`“zero copy” approach, the Board must accept Patent Owner’s construction of
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`“hardware buffer.” PO Resp. Br. (Paper 37) at 6-10; see also Ex. 2015 (Rinard
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`Remand Decl.) at ¶¶ 27-34. This, however, is not a key advance of the ’949 patent
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`as Patent Owner and its expert suggest. PO Resp. Br. (Paper 37) at 2; Ex. 2015
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`(Rinard Remand Decl.) at ¶ 44.
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`13. First, the term “zero copy” is a misnomer. There is always an
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`intermediate copying step as the executable image moves from the primary
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`processor to the “hardware buffer,” and then to the claimed “system memory.”
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`This is the case regardless of whether the hardware buffer is a permanent buffer, a
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`temporary buffer in some system memory, or an internal RAM. More particularly,
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`the ’949 patent approach requires copying of data segments from the “hardware
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`buffer” and writing them to the claimed “system memory.” In other words, claim
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`1 first requires that the “secondary processor” and its “hardware buffer” to
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`“receiv[e] an image header and at least one data segment of an executable software
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`image.” Ex. 1001 (’949 patent) at claim 1. Next, claim 1 requires “scatter
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`load[ing] each received data segment … from the hardware buffer to the system
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`memory.” Id. This means that in claim 1 of the ’949 patent, a data segment is (1)
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`first written to the hardware buffer, (2) next copied from the hardware buffer, and
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`(3) then written to the claimed system memory through the scatter loading process.
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`Without such intermediate copying of the data segment from the “hardware
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`buffer,” it would not be possible to move the data segment to the “system memory”
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`in the scatter loading process. Therefore, the supposed “zero copy” approach still
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`requires intermediate copying, regardless of what “hardware buffer” means, as I
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`described above.
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`14. The portions of the ’949 specification that Patent Owner cites to (e.g.,
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`Ex. 1001 at 7:16-30, 11:17-24) in support of the “zero copy” approach do not
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`support the proposition that the “hardware buffer” plays a role in making more
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`efficient the described direct scatter loading process. For example, column 7,
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`lines 16 to 30 state:
`
`Aspects of the present disclosure provide techniques for
`efficiently loading the executable software images from the
`primary processor's non-volatile memory to the secondary
`processor’s volatile memory. As mentioned above, traditional
`loading processes require an intermediate step where the binary
`multi-segmented image is buffered (e.g., transferred into the
`system memory) and then later scattered into target locations
`(e.g., by a boot loader). Aspects of the present disclosure
`provide techniques that alleviate the intermediate step of
`buffering required in traditional loading processes. Thus,
`aspects of the present disclosure avoid extra memory copy
`operations, thereby improving performance (e.g., reducing the
`time required to boot secondary processors in a multi-processor
`system).
`Ex. 1001 (’949 patent) at 7:16-30. Similarly, column 11, lines 17 to 24 state:
`
`Thus, aspects of the present disclosure may reduce the time it
`takes to boot secondary processors in a multi-processor system
`where secondary processor images are transferred from the
`primary processor. This reduction is achieved by avoiding extra
`memory copy operations and enabling concurrent image
`transfers with background data processing, such as
`authentication.
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`Id. at 11:17-24. These statements, however, do not support or even imply the
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`elimination of the intermediate step of storing the executable software image in the
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`“hardware buffer” before copying the image to the claimed “system memory.” Not
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`only is this not mentioned but, like the “zero copy” approach, this is not possible.
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`In addition, these statements do not even mention a “hardware buffer.”
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`15. Second, there is nothing in the ’949 specification that supports the
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`proposition that the “hardware buffer” is responsible for the claimed invention’s
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`allegedly more efficient, direct scatter loading process, as Patent Owner and Dr.
`
`Rinard suggest (see PO Resp. Br. (Paper 37) at 6-10; Ex. 2015 (Rinard Remand
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`Decl.) at ¶¶ 27-34). The ’949 claims do not use the term “permanent” to describe
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`the “hardware buffer.” In addition, the ’949 claims do not require a particular level
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`of performance or efficiency for the scatter loading process.
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`16. Like its use of the ’949 specification, Patent Owner’s reliance on
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`inventor testimony from Mr. Haehnichen is also irrelevant. Patent Owner provides
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`Mr. Haehnichen’s testimony to demonstrate that it wanted to develop a more
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`efficient process without “copying things around in memory.” PO Resp. Br. 8-9
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`(citing Ex. 2003, 216:16-21); see also Ex. 2015 (Rinard Remand Decl.) at ¶¶ 35-
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`40. But, this inventor testimony does not clarify the role played by the “hardware
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`buffer” in the allegedly efficient scatter loading process. Not only does Mr.
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`Haehnichen never state that a permanent buffer is necessary, but the details about
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`the claimed invention that he provides are never described in the ’949
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`specification. As such, Mr. Haehnichen’s testimony is not useful in demonstrating
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`how a POSITA would understand the scope of the ’949 patent.
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`17. Finally, beyond the fact that the ’949 patent does not describe the role
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`of the “hardware buffer” in providing a more “efficient” scatter loading technique
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`(PO Resp. Br. (Paper 37) at 6-7; Ex. 2015 (Rinard Remand Decl) at ¶¶ 27-34), the
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`use of a “permanent, dedicated buffer” distinct from any system memory is not
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`necessary to achieve this goal. If there is any efficiency as a result of the scatter
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`loading technique described in the ’949 patent it is due to the separation between
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`the “hardware buffer” and the claimed “system memory,” which allows for the
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`efficient movement of data segments from the hardware buffer to the claimed
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`system memory. This could be helpful in speeding up the scatter loading process
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`because, when moving data segments, copying from a particular memory (such as
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`Dynamic Random Access Memory, or DRAM for short) into a different location of
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`that same memory will be slower than copying from a fast memory and writing to
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`a physically separate second memory (DRAM). In this case, the fact that the
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`“hardware buffer” is located separately from the claimed “system memory” means
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`that instead of copying from the claimed “system memory” and writing back into
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`10
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`that same system memory, the data segments in the “hardware buffer” are copied
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`into the distinct claimed “system memory.”
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`18. On the other hand, use of a “permanent, dedicated buffer” would not
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`enhance the efficiency of the scatter loading process. For example, if a system
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`memory for a processor is implemented in internal RAM memory, this internal
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`RAM memory could function at or near the speed of the processor, making its use
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`very efficient, particularly compared to a permanent buffer that is slow.
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`19. Patent Owner’s argument about efficiency assumes that a temporary
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`buffer would be allocated in a system memory external to the processor chip, such
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`as external DRAM memory. While external DRAM memory is commonly used
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`for system memory, data access to this memory is much slower than the processor
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`cycle speed. Therefore, copying data between locations in external DRAM
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`memory can be slow. On the other hand, SRAM (Static Random Access Memory)
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`is commonly used for internal RAM memory, and therefore, reading and writing to
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`internal RAM memory (i.e., RAM internal to the processor chip) is much faster
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`than the same operations to an external DRAM. Therefore, if a temporary buffer
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`implemented in internal RAM instead of external DRAM is used as the “hardware
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`buffer,” it will operate faster and with greater efficiency. Because internal RAM
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`memory (implemented as SRAM) works at near the speed of the processor,
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`11
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`copying data segments from an internal RAM (even if in system memory) to an
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`external DRAM (system memory) would be faster than copying data segments
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`between external DRAM locations (in system memory), which Patent Owner and
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`Dr. Rinard suggest the ’949 patent improves upon (PO Resp. Br. (Paper 37) at 6-8;
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`see also Ex. 2015 (Rinard Remand Decl.) at ¶¶ 28-33). Since copying a data
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`segment from an internal RAM to external DRAM (system memory) would result
`
`in the same type of fast, direct scatter loading process that Patent Owner proposes,
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`the term “hardware buffer” should not be construed to preclude the use of such an
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`internal RAM as a “hardware buffer,” regardless of whether it is part of what
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`Patent Owner and Dr. Rinard might characterize as system memory. See PO
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`Resp. Br. (Paper 37) at 17-19; Ex. 2015 (Rinard Remand Decl.) at ¶¶ 68-70.
`
`Indeed, nothing in the ’949 specification precludes the “hardware buffer” from
`
`being implemented in RAM memory, such as internal RAM.
`
`20. This is evidenced by the very technological sources, the Fourth and
`
`Fifth editions of the Hennessy and Patterson textbooks, cited by Dr. Rinard as
`
`support for his construction of “hardware buffer.” See Ex. 2015 (Rinard Remand
`
`Decl.) at ¶¶ 9-15 (citing Ex. 2014 (Hennessy and Patterson 4th Ed.) and Ex. 2012
`
`(Hennessy and Patterson 5th Ed)). As explained below, Dr. Rinard uses these
`
`textbooks to explain that memory generally performs more slowly than a
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`12
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`processor. In doing so, Dr. Rinard references portions of the textbooks discussing
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`DRAM memory, and his arguments do not apply to the use of internal RAM as a
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`“hardware buffer.” As I point out, these textbooks, well-known in the field of
`
`computer architecture, discuss the efficiencies of internal RAM over external
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`DRAM and demonstrate that use of internal RAM will result in faster copying of
`
`data than copying data between locations in external DRAM.
`
`21.
`
`In his declaration, Dr. Rinard first cites Figure 5.2 from the Fourth
`
`Edition of the Hennessy and Patterson textbook to suggest that memory performs
`
`more slowly than processors. See Ex. 2015 (Rinard Remand Decl.) at ¶ 9 (citing
`
`Ex. 2014 (Hennessy and Patterson 4th Ed.) at Fig. 5.2) (“In modern computers, the
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`DRAM memory access time is too slow to keep up with processor memory reads
`
`and writes.”). The caption to Figure 5.2 (pictured below) indicates that the
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`comparison Dr. Rinard is referencing is one between “DRAM” memory and a
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`“processor.” Because external DRAM is typically implemented using a much
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`slower device technology to enable bulk memory, requires a refresh process, and
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`requires off-chip access, it functions much more slowly than circuitry on a
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`processor chip (e.g., internal memory).
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`Ex. 2014 (Hennessy and Patterson 4th Ed.) at 289.
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`22.
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`In fact, Figure 5.1 of the Fourth Edition of the Hennessy and Patterson
`
`textbook—the figure on the page immediately preceding the one cited by Dr.
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`Rinard—illustrates this point.
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`14
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`Ex. 2014 (Hennessy and Patterson 4th Ed.) at 288. This figure shows the levels in a
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`typical memory hierarchy and the speed of the circuitry at these different levels:
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`
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`• The first level is the “register reference” or the processor chip (far
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`left), which includes the CPU and its registers. The circuitry for this
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`level is depicted as operating at a speed of about 250 picoseconds
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`(ps). Id.
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`• The second level is the “cache” reference (to the right of the CPU).
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`Such cache memory, which is typically implemented using SRAM
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`memory, and which can be internal to the processor chip, will
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`function at or near the speed of the CPU. Accordingly, Figure 5.1
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`shows the speed of this cache as 1 nanosecond (ns) (about four times
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`slower than register access). Id.
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`• The third level is the “memory reference” (to the right of “cache”
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`reference). This memory reference is typically implemented as
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`external DRAM memory. It is, as I set forth above, typically much
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`slower than the processor and any memory internal to the processor.
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`Consistent with this position, Figure 5.1 depicts the speed of this
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`“memory reference” as 100 nanoseconds—100 times slower than the
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`cache memory, or the SRAM technology that it uses. Id.
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`• The final, fourth level is the “disk memory reference,” a level that is
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`also external to the processor chip, and hence, Figure 5.1 depicts its
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`speed as being much slower than the “register reference,” “cache,”
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`and “memory reference.” Id.
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`23. Further, the Hennessy and Patterson textbooks even note the
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`advantages of SRAM over DRAM and confirm that almost all computers use
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`DRAM for “main memory” or external system memory, and that SRAM is
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`typically used for cache memory. The section of the Fourth Edition of the
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`Hennessy and Patterson textbook copied below indicates that “SRAMs … [have]
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`access time [that] is very close to the cycle time,” meaning that SRAM functions at
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`or near the speed of the processor. Ex. 2014 (Hennessy and Patterson 4th Ed.) at
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`311. Indeed, on the same page 311 from Ex. 2014 copied below, the textbook
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`16
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`states that “SRAM designs are concerned with speed,” and further emphasizes that
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`“DRAM designs …” emphasize “cost per bit and capacity,” instead of speed. Id.
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`Finally, this page emphasizes that SRAM is typically much faster than DRAM. Id.
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`Ex. 2014 (Hennessy and Patterson 4th Ed.) at 311.
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`24. The Fifth Edition of the Hennessy and Patterson textbook indicates
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`that it is common to integrate cache onto the processor chip itself, meaning that the
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`17
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`use of SRAM on-chip with the processor will function at or near the speed of the
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`processor. Ex. 2012 (Hennessy and Patterson 5th Ed.) at 97. These statements are
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`consistent with and offer support for my discussion of the advantages of internal
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`RAM. Because internal RAM is typically SRAM, such internal RAM will
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`function at or near the speed of the processor.3
`
`25. Finally, it is well-known that circuitry on chip with the processor is
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`made using the same semiconductor fabrication technology as the processor chip.
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`This is typically CMOS technology. Because the same semiconductor fabrication
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`technology is used for the processor chip—including its internal RAM such as
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`SRAM—the circuitry on the chip typically functions at approximately the same
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`speed as the processor. External DRAM memory, on the other hand, is fabricated
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`on a separate chip from the processor chip, and external DRAM typically uses
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`different semiconductor fabrication technology than the processor chip. As the
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`Hennessy and Patterson textbooks indicate, DRAM technology is typically “cost
`
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`3 The Fifth Edition of the Hennessy and Patterson textbook sets forth similar
`
`information as set forth above from the Fourth Edition of the textbook. See Ex.
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`2012 (Hennessy and Patterson 5th Ed.) at 73, 72, 97.
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`18
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`per bit and capacity,” not speed. Ex. 2014 (Hennessy and Patterson 4th Ed.) at 311.
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`For this reason, DRAM is typically fabricated with semiconductor technology that
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`does not operate at the same speed as a processor chip.
`
`26.
`
`In sum, Patent Owner’s reasons for construing “hardware buffer” as a
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`“a permanent, dedicated buffer that is distinct from system memory” are
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`unpersuasive because they lack support from the intrinsic record, including the
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`’949 specification, extrinsic record, and rely on an incorrect assumption about the
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`type of memory in which the “hardware buffer” must be implemented.
`
`V.
`
`PETITIONER’S PROPOSED CONSTRUCTION OF “HARDWARE
`BUFFER” IS CORRECT.
`27. Patent Owner and Dr. Rinard also argue that Petitioner’s proposed
`
`construction is incorrect. The primary argument that Patent Owner and Dr. Rinard
`
`make is that Petitioner’s construction of “hardware buffer” would encompass a
`
`temporary buffer formed in system memory, which Patent Owner and Dr. Rinard
`
`contend is contrary to the background section of the ’949 specification. See PO
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`Resp. Br. (Paper 37) at 5, 14 (citing Ex. 1001, 2:17-22, 2:23-28, 2:29-31, 2:35-41,
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`7:20-26); Ex. 2015 (Rinard Remand Decl.) at ¶ 59. This is inaccurate because
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`Petitioner’s construction does not encompass temporary buffers in the claimed
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`“system memory,” since the “hardware buffer” must be physically separate from
`
`the claimed “system memory.”
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`19
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`Reply Declaration of Bill Lin, Ph.D. on Remand
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`28. More specifically, Patent Owner and Dr. Rinard argue that my current
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`construction is inconsistent with my prior testimony on the scope of the claimed
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`invention. See PO Resp. Br. (Paper 37) at 14-15; see also Ex. 2015 (Rinard
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`Remand Decl.) at ¶ 61. This is also incorrect because in the statement that Patent
`
`Owner quotes—“[t]he ’949 patent makes a distinction between prior art systems
`
`that used a ‘temporary buffer’ that was part of the system memory (Ex-1001, 2:23-
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`41), and the alleged invention that uses a ‘hardware buffer’ separate from the
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`system memory (id., 2:58-61, 7:20-26, Fig. 3)” (PO Resp. Br. at 14-15 (citing Ex.
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`1002 at ¶ 111))—I am only stating that the “hardware buffer” must be separate
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`from the claimed “system memory,” not memory that one might characterize as
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`system memory. This is entirely consistent with my current construction, under
`
`which the “hardware buffer” must be physically distinct from the claimed “system
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`memory.” See also Ex. 1026 (Lin Remand Decl.) at ¶ 28 (stating in connection
`
`with another section of the ’949 patent that the “specification does not teach
`
`against the use of all temporary buffers, but instead only temporary buffers that
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`reside in the same physical ‘system memory’ (i.e., RAM 112) as claimed into
`
`which the executable image is loaded for execution. Moreover, this passage is
`
`consistent with the specification passages demonstrating that the ‘hardware buffer’
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`20
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`is physically separate from the claimed ‘system memory’ that receives the
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`‘executable software image’ for execution.”)
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`29. Further, the portion of the ’949 specification (Ex-1001 at 2:23-41) that
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`I discuss in the testimony quoted by the Patent Owner (PO Resp. Br. at 14-15 (Ex.
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`1002 at ¶ 111)) does not stand for the proposition that the “hardware buffer” of the
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`’949 patent cannot be a temporary buffer allocated in a system memory. Rather, it
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`distinguishes prior art conventional techniques on other grounds. Namely, as
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`discussed in my Opening Remand Declaration, this section distinguishes use of
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`“techniques that copy data packets containing both the actual data segments (i.e.,
`
`payload) and an accompanying header that directs where the data must ultimately
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`be loaded.” Ex. 1026 (Lin Remand Decl.) at ¶ 25.
`
`30.
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`In response to this part of my Opening Remand Declaration, Dr.
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`Rinard argues that the ’949 patent “discusses at least two distinct kinds of
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`headers…. The first kind of header is image headers which ‘contains the target
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`locations for the data image segments to be scatter loaded into memory of the
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`second process’ ….[and] [t]he second kind of header is packet headers in which
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`‘each packet would have an associated packet header information along with the
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`payload.’” Ex. 2015 (Rinard Remand Decl.) at ¶¶ 50-51. Dr. Rinard contends that
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`because packet headers “typically do not contain any information about where to
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`21
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D. on Remand
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`place image data in memory,” my conclusions regarding the background section
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`are incorrect. Ex. 2015 (Rinard Remand Decl.) at ¶ 51. However, the background
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`section of the ’949 patent does not make a distinction between image and packet
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`headers as Dr. Rinard alleges. Although the term “software image” or “executable
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`image” does not appear in column 2, lines 23 to 41 of the ’949 specification, given
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`the immediately preceding paragraph in column 2 that discusses a “software
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`image,” a POSITA would understand the discussion of headers to refer to image
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`headers. Therefore, a POSITA reading the background section of the ’949 patent
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`would understand that the purpose behind the section’s discussion of temporary
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`buffers is not to exclude the use of any temporary buffers. Instead, the ’949
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`specification distinguishes the copying of the image header and data segments into
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`the hardware buffer together (and not separately, as claimed in the ’949 patent).
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`VI. UNDER EITHER PROPOSED CONSTRUCTION, THE PRIOR ART
`DISCLOSES A “HARDWARE BUFFER.”
`31. Under either of the constructions proposed by the parties, a POSITA
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`would understand that Bauer and Svensson’s ISA is a “hardware buffer” claimed
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`in the ’949 patent.
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`32. The ISA is a “hardware buffer” under Petitioner’s constructio
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