IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Chang Kwon, et al.
`In re Patent of:
`8,063,674 Attorney Docket No.: 39521-0053IP2
`U.S. Patent No.:
`November 22, 2011
`
`Issue Date:
`Appl. Serial No.: 12/365,559
`
`Filing Date:
`February 4, 2009
`
`Title:
`MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN
`DETECTORS
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 8,063,674 PURSUANT TO 35 U.S.C. §§ 311–319, 37 C.F.R. § 42
`
`
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`TABLE OF CONTENTS
`
`I. 
`
`II. 
`
`37 C.F.R. § 42.104 REQUIREMENTS ........................................................... 1 
`A.  Standing (42.104(a)) ................................................................................. 1 
`B.  Grounds (42.104(b)) ................................................................................. 1 
`SUMMARY OF THE ’674 PATENT ............................................................. 2 
`A.  Brief Description ....................................................................................... 2 
`B.  Claim Construction ................................................................................... 4 
`1. 
`“signal processor” (8 and 17) .......................................................... 5 
`2.  Means-Plus-Function Terms (17-20) .............................................. 5 
`III.  MANNER OF APPLYING CITED PRIOR ART .......................................... 9 
`A.  [GROUND 1] – Steinacker in view of Doyle and Park Render Claims 8,
`9, 12, 13, and 16-22 Obvious .................................................................. 10 
`1.  Overview of Steinacker ................................................................. 10 
`2.  Overview of Doyle ........................................................................ 12 
`3.  Overview of Park ........................................................................... 14 
`4. 
`The Combination of Steinacker, Doyle, and Park ........................ 15 
`5.  Motivation to Combine Steinacker, Doyle, and Park ................... 20 
`6. 
`Claims 8 and 17 ............................................................................. 21 
`7. 
`Claims 9 and 13 ............................................................................. 36 
`8. 
`Claim 12 ........................................................................................ 38 
`9. 
`Claims 16 and 22 ........................................................................... 40 
`10.  Claim 18 ........................................................................................ 41 
`11.  Claims 19 and 20 ........................................................................... 42 
`12.  Claim 21 ........................................................................................ 44 
`B.  [GROUND 2a] – Applicant’s Admitted Prior Art in view of
`Majcherczak Renders Claims 8, 9, 12, 13, 17-21 Obvious .................... 45 
`1.  Overview of AAPA ....................................................................... 45 
`2.  Overview Majcherczak.................................................................. 47 
`3. 
`Combination of AAPA and Majcherczak ..................................... 51 
`4.  Motivation to Combine AAPA and Majcherczak ......................... 53 
`5. 
`Claims 8 and 17 ............................................................................. 54 
`6. 
`Claims 9 and 13 ............................................................................. 63 
`7. 
`Claim 12 ........................................................................................ 66 
`8. 
`Claim 18 ........................................................................................ 68 
`9. 
`Claims 19 and 20 ........................................................................... 70 
`10.  Claim 21 ........................................................................................ 73 
`C.  [GROUND 2b] – AAPA, Majcherczak, and Matthews Render Claims
`16 and 22 Obvious .................................................................................. 74 
`
`i
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`IV.  CONCLUSION .............................................................................................. 76 
`V.  MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1) ......................... 76 
`A.  Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1) .............................. 76 
`B.  Related Matters Under 37 C.F.R. § 42.8(b)(2) ....................................... 76 
`C.  Lead And Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ................... 77 
`D.  Service Information ................................................................................ 77 
`
`
`
`
`
`
`ii
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`
`
`
`EXHIBITS
`
`APPLE-1001
`
`U.S. Patent No. 8,063,674 to Kwon et al. (“the ’674 patent”)
`
`APPLE-1002
`
`Excerpts from the Prosecution History of the ’674 Patent (“the
`Prosecution History”)
`
`APPLE-1003
`
`Declaration of Dr. Robert Horst
`
`APPLE-1004
`
`Curriculum Vitae of Dr. Robert Horst
`
`APPLE-1005
`
`U.S. Patent No. 7,279,943 to Steinacker (“Steinacker”)
`
`APPLE-1006
`
`U.S. Patent No. 4,717,836 to Doyle (“Doyle”)
`
`APPLE-1007
`
`Jun Cheol Park and Vincent J. Mooney, Sleepy Stack Leakage
`Reduction, 14 IEEE Transactions On Very Large Scale Integra-
`tion (VLSI) Systems 1251 (2006) (“Park”)
`
`APPLE-1008
`
`U.S. Pat. Appl. Pub. No. 2002/0163364 to Majcherczak et al.
`(“Majcherczak”)
`
`APPLE-1009
`
`U.S. Patent No. 6,646,844 to Matthews (“Matthews”)
`
`APPLE-1010
`
`APPLE-1011
`
`APPLE-1012
`
`G. W. Griffiths, “A Review of Semiconductor Packaging and
`Its Role in Electronics Manufacturing,” 8th IEEE/CHMT Inter-
`national Conference on Electronic Manufacturing Technology
`Symposium (1990)
`
`Wang-Chang Albert Gu, “RF Front-End Modules in Cellular
`Handsets,” 2004 IEEE Compound Semiconductor Integrated
`Circuit Symposium (2005)
`
`Kaushik Roy et al., “Leakage current mechanisms and leakage
`reduction techniques in deep-submicrometer CMOS circuits,”
`91 Proceedings of the IEEE 2, pp. 305-327 (Apr. 2003) (“Roy”)
`
`iii
`
`

`

`APPLE-1013
`
`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Yangyang Ye et al., “A new technique for standby leakage re-
`duction in high-performance circuits,” 1998 Symposium on
`VLSI Circuits. Digest of Technical Papers (Cat.
`No.98CH36215), Honolulu, HI, USA, 1998, pp. 40-41
`(“Borkar”)
`
`APPLE-1014
`
`U.S. Patent No. 7,049,865 to Parker et al. (“Parker”)
`
`APPLE-1015
`
`Qadeer A. Khan et al., “A Sequence Independent Power-on-Re-
`set Circuit for Multi-Voltage Systems,” 2006 IEEE Interna-
`tional Symposium on Circuits and Systems (Sep. 2006)
`
`APPLE-1016
`
`Declaration of Jacob Munford (with attachments)
`
`
`
`
`iv
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Apple Inc., (“Apple”) petitions for Inter Partes Review (“IPR”) under 35
`
`U.S.C. §§ 311–319 and 37 C.F.R. § 42 of claims 8, 9, 12, 13, and 16-22 (“the
`
`Challenged Claims”) of U.S. Patent No. 8,063,674 (“the ’674 patent”). There ex-
`
`ists a reasonable likelihood that Apple will prevail with respect to at least one of
`
`the Challenged Claims.
`
`I.
`
`37 C.F.R. § 42.104 REQUIREMENTS
`A.
`Standing (42.104(a))
`Apple certifies that the ’674 Patent is available for IPR. Apple is not barred
`
`or estopped from requesting this review challenging the Challenged Claims on the
`
`below-identified grounds.
`
`B. Grounds (42.104(b))
`
`
`Grounds
`Ground 1
`
`Claims
`8-9, 12-13, 16-22
`
`Ground 2a 8-9, 12-13, 17-21
`
`Ground 2b 16, 22
`
`Basis
`§103: Steinacker in view of Doyle and
`Park
`§103: Applicants Admitted Prior Art
`(AAPA) in view of Majcherczak
`§103: AAPA in view of Majcherczak
`and Matthews
`
`
`Steinacker, Doyle, Park1, Majcherczak, and Matthews each qualify as prior
`
`art under 35 U.S.C § 102(b).
`
`
`
`
`1 See generally APPLE-1016.
`
`1
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`
`II.
`
`SUMMARY OF THE ’674 PATENT
`A. Brief Description
`Generally, the ’674 patent relates to “power up/down detectors for multiple
`
`supply voltages devices.” APPLE-1001, 1:6-8. These multiple supply voltage de-
`
`vices may include a “core network” of newer circuits (e.g., microprocessors) that
`
`are “smaller and have lower voltage requirements, while still operating at high-
`
`speeds.” APPLE-1001, 1:14-17, 1:22-25. These core devices can be powered
`
`down when no device operations are pending or in progress. APPLE-1001, 1:29-
`
`34.
`
`However, these lower-voltage core devices still have to interface with older,
`
`higher-voltage I/O devices. See APPLE-1001, 1:17-22. Level shifters can be used
`
`to permit communication between circuits operating at different supply voltages.
`
`APPLE-1001, 1:28-29. These level shifters facilitate communication of the logic
`
`signals between the core and I/O devices by translating the signals into the appro-
`
`priate voltage levels. APPLE-1003, ¶ 57.
`
`The ’674 Patent identifies a problem that may arise in communications be-
`
`tween the core and I/O devices: transmission of erroneous signals into the external
`
`environment during transitions in the core network’s power supply. APPLE-1001,
`
`1:29-40. To avoid this problem, the ’674 Patent suggests utilizing a “power-
`
`on/off-control (POC)” device. See APPLE-1001, 1:41-57.
`
`2
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`A POC device effectively monitors the core network supply voltage and
`
`sends a signal to the I/O devices and/or level shifters indicating when the core net-
`
`work supply voltage is powered down or power collapsed. See APPLE-1001,
`
`1:55-57; see also APPLE-1003, ¶ 59. This signal can be leveraged by the recipient
`
`devices to trigger a transition into a “known state” in which those devices will not
`
`process erroneous signals output by the powered down core network devices. See
`
`APPLE-1001, 1:34-57; see also APPLE-1003, ¶ 59.
`
`In its background section, the ’674 Patent acknowledges that a “standard”
`
`POC system 10 for multiple supply voltage devices was known at the time of the
`
`filing of the ’674 Patent. See APPLE-1001, 1:57-2:39. This prior art POC system
`
`10 includes a power-up/down detector 100, a signal amplifier 101, and an output
`
`stage 102. See APPLE-1001 FIG. 1, 1:57-62. The main difference between this
`
`prior art POC system 10 and the purported invention of the ’674 Patent is the addi-
`
`tion of a feedback network 310. APPLE-1003, ¶ 60. A comparison of FIG. 1 and
`
`FIG. 4 illuminates this straightforward difference. Id.
`
`3
`
`

`

`power up/
`down detector
`
`signal processor
`
`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`feedback 
`network
`signal processor
`
`power up/
`down detector
`
`
`
`The feedback network 310 increases the current capacity when it is “on,” re-
`
`sulting in increased sensitivity. See APPLE-1001, 5:16-23; see also APPLE-1003,
`
`¶ 61. Conversely, the feedback network 310 decreases the current capacity when it
`
`is “off,” which “will limit and reduce the amount of leakage current that may be
`
`dissipated through the power up/down detector.” See APPLE-1001, 5:29-38; see
`
`also APPLE-1003, ¶ 61. Notably, each of the three disclosed implementations of
`
`feedback network 310—corresponding to FIGS. 4, 5, and 6 of the ’674 Patent—
`
`will increase and decrease the current capacity in this manner. APPLE-1003, ¶¶
`
`62-63.
`
`Dr. Horst provides a more fulsome overview of the ’674 Patent and the tech-
`
`nology underlying it in his declaration. See APPLE-1003, ¶¶ 36-63.
`
`B. Claim Construction
`Unless otherwise noted below, Apple submits that all terms should be given
`
`their plain meaning, but reserves the right to respond to any constructions that may
`
`4
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`later be offered by the Patent Owner or adopted by the Board. Apple is not waiv-
`
`ing any arguments concerning indefiniteness or claim scope that may be raised in
`
`litigation.
`
`1.
`“signal processor” (8 and 17)
`The ’674 Patent does not define the term “signal processor,” but it provides
`
`examples of its implementation, which include an inverting amplifier. See AP-
`
`PLE-1003, ¶ 66. While expressly caveating “that each of the figures is provided
`
`for the purpose of illustration and description only and is not intended as a defini-
`
`tion of the limits of the present disclosure,” the ’674 Patent describes that the “pro-
`
`cessing circuitry 307 is made up of a signal processor 308 and an output buffer
`
`309” and that “signal processor 308 [as shown in FIGS. 4-6] comprises an invert-
`
`ing amplifier 400.” See APPLE-1001, 4:7-10, 5:5-6, 6:35-37, 8:14-42. Thus, at
`
`least an inverting amplifier constitutes a “signal processor,” as that term is used in
`
`the ’674 Patent.
`
`Therefore, the term “signal processor” should be construed at least broadly
`
`enough to encompass the embodiment described in the ’674 Patent, which is an
`
`amplifying inverter. APPLE-1003, ¶¶ 66-69.
`
`2. Means-Plus-Function Terms (17-20)
`Each of claims 17-20 recites one or more limitations that employ the phrase
`
`“means for,” creating a presumption that § 112 ¶ 6 applies. See TriMed, Inc. v.
`
`5
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Stryker Corp., 514 F. 3d 1256, 1259 (Fed. Cir. 2008). The following table identifies
`
`the limitations for which this presumption applies, as well as the structure set forth
`
`in the ’674 Patent corresponding to function that is bolded for each limitation:
`
`Means-Plus-Function Limitation
`
`Corresponding ‘674 Patent Structure
`
`17: means for detecting a power-on of
`
`power up/down detector 100 illustrated
`
`a second supply voltage while a first
`
`in FIG. 1 (including transistors M1, M2,
`
`supply voltage is already on
`
`and M3), power up/down detector 306
`
`illustrated in FIGS. 4, 5, and 6 (includ-
`
`ing four transistors M4, M5, M6, and
`
`M7), or equivalents thereof. See AP-
`
`PLE-1001, 2:8-13, 5:24-27; see also
`
`APPLE-1003, ¶¶ 70-71.
`
`17: means, responsive to said power-
`
`feedback network 310 as illustrated in
`
`on detection, for decreasing a current
`
`any one of FIGS. 4, 5, or 6, or equiva-
`
`capacity of a power on/off detector of
`
`lents thereof. See APPLE-1001, 5:29-
`
`said POC network
`
`34, 6:15-18, 7:4-7, 7:30-35; see also
`
`APPLE-1003, ¶¶ 72-73.
`
`17: means for detecting a power-down
`
`power up/down detector 100 illustrated
`
`of said second supply voltage while
`
`in FIG. 1 (including transistors M1, M2,
`
`said first supply voltage is on
`
`and M3), power up/down detector 306
`
`6
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`illustrated in FIGS. 4, 5, and 6 (includ-
`
`ing four transistors M4, M5, M6, and
`
`M7), or equivalents thereof. See AP-
`
`PLE-1001, 1:65-2:7, 5:6-10; see also
`
`APPLE-1003, ¶¶ 74-75.
`
`17: means, responsive to said power-
`
`feedback network 310 as illustrated in
`
`down detection, for increasing said
`
`any one of FIGS. 4, 5, or 6, or equiva-
`
`current capacity of said power on/off
`
`lents thereof. See APPLE-1001, 5:29-
`
`detector
`
`34, 6:21-28, 7:4-7, 7:30-35; see also
`
`APPLE-1003, ¶¶ 76-77.
`
`18: means for providing a feedback
`
`Signal processor 308 or equivalents
`
`signal associated with at least one of:
`
`thereof. See APPLE-1001, 5:12-15,
`
`said detected power-on or said de-
`
`5:29-32; see also APPLE-1003, ¶¶ 81-
`
`tected power-down, wherein said feed-
`
`82.
`
`back signal is used in said means for de-
`
`creasing and said means for increasing
`
`
`
`In addition, as noted by the following table, claims 17, 19, and 20 recite addi-
`
`tional “means for” terms for which the presumption may be overcome. TriMed, Inc.,
`
`514 F. 3d at 1259. As before, the function is bolded for each limitation and the
`
`7
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`recited corresponding structure is underlined. Under the assumption that the pre-
`
`sumption for § 112 ¶ 6 may still apply, however, the structure disclosed by the ’674
`
`Patent for performing the bolded function has also been identified.
`
`Means-Plus-Function Limitation
`
`Corresponding ‘674 Patent Structure
`
`Claim 17: means for receiving a logic-
`
`(1) PMOS transistor M1 and NMOS
`
`high signal at a control gate of at least
`
`transistors M2-M3 of power-up/down
`
`one first transistor, at least one sec-
`
`detector 100; (2) PMOS transistor M4,
`
`ond transistor and at least one third
`
`NMOS transistor M7, and one or both
`
`transistor coupled in series between
`
`of transistors M5 and M6 of power
`
`the at least one first transistor and the
`
`up/down detector 306; or (3) equiva-
`
`at least one second transistor, the at
`
`lents of either of these. See APPLE-
`
`least one first transistor being config-
`
`1001, 1:62-2:1, 2:8-11, 5:46-58, 6:31-
`
`ured to switch off in response to said
`
`35, 7:13-14; see also APPLE-1003, ¶¶
`
`logic-high signal, and the at least one
`
`78-79.
`
`second transistor being configured to
`
`switch on in response to said logic-high
`
`signal
`
`Claim 17: means for transmitting a de-
`
`(1) connection between transistor M3
`
`tection signal to a signal processor
`
`via transistor M2 to the input of signal
`
`from the at least one second transistor
`
`processor 101; (2) connection between
`
`8
`
`

`

`based on said received logic-high sig-
`
`nal
`
`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`transistor M7 via transistor M6 to the in-
`
`put of signal processor 308; or (3)
`
`equivalents of either of these. See AP-
`
`PLE-1001, 1:65-2:2, 2:8-11, 5:58-67,
`
`6:47-60, 7:17-20; see also APPLE-
`
`1003, ¶ 80.
`
`Claims 19 and 20: means, responsive to
`
`(1) connection between inverting ampli-
`
`said feedback signal, for switching
`
`fier 400 and the gate of transistor M8;
`
`[on/off] one or more transistors of a
`
`(2) connection between inverting buffer
`
`plurality of transistors, wherein said
`
`401 and the gate of transistor M9; (3)
`
`plurality of transistors define said cur-
`
`both (1) and (2); or (4) equivalents of
`
`rent capacity of said power on/off detec-
`
`any one of these three. See APPLE-
`
`tor
`
`
`
`1001, 6:4-18, 6:44-7:7, 7:23-35; see
`
`also APPLE-1003, ¶¶ 83-84.
`
`III. MANNER OF APPLYING CITED PRIOR ART
`As detailed below, this request shows a reasonable likelihood that the Re-
`
`quester will prevail with respect to the Challenged Claims.
`
`
`
`
`
`9
`
`

`

`A.
`
`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`[GROUND 1] – Steinacker in view of Doyle and Park Ren-
`der Claims 8, 9, 12, 13, and 16-22 Obvious
`1. Overview of Steinacker2
`Steinacker describes “a circuit arrangement having at least two circuit blocks
`
`operated at different supply voltages which is able to ensure reliable operation of
`
`the circuit arrangement regardless of turn-on profiles for the different supply volt-
`
`ages in the circuit blocks.” APPLE-1005, 2:14-19. Steinacker acknowledges the
`
`problem addressed by the ’674 Patent, as Steinacker likewise notes, “[t]he fact that
`
`the circuit blocks operate at different supply voltages and that the supply voltages
`
`can be turned on and off independently of one another means that reliable opera-
`
`tion of the circuit arrangement is not always ensured.” APPLE-1005, 1:49-52. In-
`
`deed, consistent with the approach proposed by the ’674 Patent, “[a] basic concept
`
`behind [Steinacker’s] invention is that the second circuit block is deactivated [i.e.,
`
`put in a known state] when the first supply voltage is still too low in order to en-
`
`sure safe operation of the first circuit block.” APPLE-1005, 2:35-38. In other
`
`words, Steinacker describes a similar solution to the same problem as the power-
`
`on/off-control (POC) described in the ’674 Patent. APPLE-1003, ¶ 86.
`
`
`2 Apple hereby expressly incorporates the entirety of the discussion of the
`
`Steinacker, Doyle, and Park combination set forth in Sections III.A.1-5 into the el-
`
`ement-by-element analysis of Ground 1, infra.
`
`10
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Particularly, Steinacker describes a “circuit arrangement 1 [that] has a first
`
`supply voltage domain 1.1 and a second supply voltage domain 1.2.” APPLE-
`
`1005, 4:5-7. “In the case of a mixed-signal circuit, for example, the voltage level
`
`of the first supply voltage is lower than the value of the second supply voltage.”
`
`APPLE-1005, 4:14-16. In circuit arrangement 1, a first circuit block 2 is supplied
`
`by the first supply voltage and a second circuit block 3 is supplied by the second
`
`supply voltage. See APPLE-1005, FIG. 1, 4:23-27. In order to interface between
`
`the first circuit block 2 and the second circuit block 3, the circuit arrangement 1 in-
`
`cludes a voltage level shifting unit 4. See APPLE-1005, FIG. 1, 4:23-35.
`
`Steinacker’s circuit arrangement 1 also includes a voltage level detector 5.
`
`APPLE-1005, FIG. 1, 4:45-64. The voltage level detector 5 perform a commensu-
`
`rate function to the POC network described in the ’674 Patent. APPLE-1003, ¶ 91.
`
`Specifically, Steinacker describes that “the voltage level detector 5 sends a first
`
`control signal in the form of a voltage level at the level of the second supply volt-
`
`age—that is to say a logic value ‘l’—to the voltage level shifting unit 4 if the first
`
`supply voltage is lower than a threshold value from the voltage level detector 5.”
`
`APPLE-1005, 4:56-61. Like the POC network of the ’674 Patent, the signal output
`
`by the voltage level detector 5 indicates “when the logic gates in the first supply
`
`voltage domain 1.1 or in the second supply voltage domain 1.2 are not yet operat-
`
`ing reliably.” APPLE-1005, 4:61-64; see also APPLE-1003, ¶ 92.
`
`11
`
`

`

`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`As for voltage level detector 5, Steinacker provides a list of the types of cir-
`
`cuits that can be used as the voltage level detector 5 and describes how such a cir-
`
`cuit would be connected into the circuit arrangement 1. APPLE-1003, ¶ 93. In
`
`particular, Steinacker describes that voltage detector 5 can take “the form of a
`
`Schmitt trigger with an inverting output . . . an inverter circuit, a comparator circuit
`
`or comparable circuits.” APPLE-1005, 4:49-55. Additionally, Steinacker de-
`
`scribes how the voltage level detector 5 to the first and second supply voltages.
`
`See APPLE-1005, 4:45-49. This is the same general manner of connecting the
`
`supply voltages as shown in FIGS. 1, 4, 5, and 6 of the ’674 Patent. APPLE-1003,
`
`¶ 93. Yet, Steinacker assumes a person of ordinary skill in the art as of the Critical
`
`Date (hereinafter “POSITA”) capable of identifying a Schmitt trigger, inverter cir-
`
`cuit, a comparator circuit or comparable circuit to implement the voltage detector
`
`5. Id.
`
`2. Overview of Doyle
`Doyle describes an improved CMOS inverter circuit. See APPLE-1006, Ab-
`
`stract, 1:7-13, 2:37-40. In FIG. 2A, Doyle illustrates a “basic well-known CMOS
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`inverter structure” and describes various reasons why its trip point (i.e., the thresh-
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`old at which a rising or falling input voltage causes the output of the inverter to
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`change) can be unstable. See APPLE-1006, 4:3-5:59. Accordingly, as illustrated
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`in FIG. 2 (reproduced below with comparable labels from the ’674 Patent), Doyle
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`describes “a CMOS inverter circuit having a trip point that is relatively stable with
`
`respect to temperature and/or to certain CMOS manufacturing process parame-
`
`ters.” APPLE-1006, 2:37-40.
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`
`
`Specifically, “P channel MOSFET 17 and N channel MOSFET 16 have their
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`gates connected to Vin and their drains connected to conductor 21.” APPLE-1006,
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`5:61-64. “[A] second inverter including P channel MOSFET 19 and N channel
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`MOSFET 20 has its input connected to Vout conductor 21,” and the output of the
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`second inverter is connected to conductor 25. APPLE-1006, 6:9-14. “Feedback is
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`provided from the output conductor 25 to the gate of a P channel MOSFET 18 con-
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`nected in parallel with P channel MOSFET 17.” APPLE-1006, 6:14-17. Addition-
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`ally, “the input of an inverter driver can be provided, which inverter driver includes
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`P channel MOSFET 22 and N channel MOSFET 23.” APPLE-1006, 6:19-21.
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`The circuit shown in FIG. 2 of Doyle is nearly identical to the POC network
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`shown in FIG. 4 of the ’674 Patent, except that Doyle’s first inverter (i.e., the
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`power up/down detector highlighted in green) includes only one P channel
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`MOSFET and only one N channel MOSFET. See APPLE-1003, ¶¶ 96-102. Yet,
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`as described by Park, it was well known at the time of the ’674 Patent to split each
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`of the P channel MOSFET 17 and N channel MOSFET 16 into two MOSFETs. Id.
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`3. Overview of Park
`Park describes that “power consumption is one of the top concerns of VLSI
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`circuit design, for which CMOS is the primary technology.” APPLE-1007, p. 1.
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`As part of discussing ways to reduce power consumption, Park begins by describ-
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`ing certain “low-power techniques that primarily target reducing leakage power
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`consumption of CMOS circuits.” Id. One “technique to reduce leakage power is
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`transistor stacking.” APPLE-1007, 2. According to Park, “[t]ransistor stacking ex-
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`ploits the stack effect; the stack effect results in substantial subthreshold leakage
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`current reduction when two or more stacked transistors are turned off together.”
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`Id. In other words, to decrease leakage current, it was known to replace a single
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`transistor with two stacked transistors. Id.
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Park illustrates this stacking technique in FIG. 11, which is reproduced be-
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`low at left. APPLE-1007, 7. “Fig. 11 shows the forced stack technique, which
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`forces a stack structure by breaking down an existing transistor into two half size
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`transistors.” APPLE-1007, 5-6. Furthermore, FIG. 1(a), which is reproduced be-
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`low at right, illustrates this forced stack technique applied to an inverter. APPLE-
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`1007, 2.
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`
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`4.
`The Combination of Steinacker, Doyle, and Park
`As described in Section III.A.1, supra, Steinacker describes that the voltage
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`level detector 5 can take the form of an inverter. APPLE-1005, 4:49-55. As to im-
`
`plementation of the inverter, a POSITA would have understood from Doyle and
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Park the claimed details. See APPLE-1003, ¶¶ 103-108, 111-122. Specifically,
`
`Doyle describes “a CMOS inverter circuit having a trip point that is relatively sta-
`
`ble with respect to temperature and/or to certain CMOS manufacturing process pa-
`
`rameters.” APPLE-1006, 2:37-40.
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`
`
`Notably, Doyle refers to Vdd as the “power supply voltage” and Vin as the
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`“input voltage.” APPLE-1006, 2:57-58, 4:23-24 (emphasis added). When con-
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`necting the inverter taught by Doyle into the circuit arrangement 1 of Steinacker as
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`the voltage detector 5, Steinacker teaches that the “first supply voltage [i.e., a
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`lower supply voltage—or Vcore in the terminology of the ’674 Patent] is supplied to
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`it via a first input.” APPLE-1005, 4:48-49 (emphasis added). Thus, a POSITA
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`would have found it obvious that the lower supply voltage (Vcore) would be con-
`
`nected to the VIN (i.e., “input voltage”) terminal of Doyle’s inverter. APPLE-
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`1003, ¶ 105. Furthermore, Steinacker teaches that the inverter “is supplied with
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`[a] second supply voltage” (i.e., a higher supply voltage—or VI/O in the terminol-
`
`ogy of the ’674 Patent). APPLE-1005, 4:47-48 (emphasis added). Thus, a
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`POSITA would have found it obvious that the higher supply voltage (VI/O) would
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`be connected to the Vdd (i.e., “power supply voltage”) terminal of Doyle’s inverter,
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`which is the only terminal other than the “input” to which a voltage can be “sup-
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`plied.” APPLE-1003, ¶ 105.
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`Based on these combined teachings of Steinacker and Doyle, a POSITA
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`would have understood the voltage detector 5 of Steinacker’s circuit arrangement 1
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`to be implemented as shown in the following reproduction of Doyle’s FIG. 2 in
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`which black annotations describing how the inverter would be connected in the cir-
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`cuit arrangement have been added. APPLE-1003, ¶ 106.
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`
`
`
`Doyle describes its inverter as a CMOS circuit, and Park describes tech-
`
`niques for further improving CMOS circuits. APPLE-1006, 2:37-40; APPLE-
`
`1007, p. 1. One such technique is the forced stack technique, which replaces each
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`transistor with two stacked transistors. APPLE-1007, 2, 5-7. Employing Park’s
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`forced stacking technique in the inverter taught by Doyle, a POSITA would have
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`understood that the P channel MOSFET 17 of Doyle’s inverter could be replaced
`
`by two P channel MOSFETs having half the size, and the N channel MOSFET 16
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`of Doyle’s inverter could be replaced by two N channel MOSFETs having half the
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`size. APPLE-1003, ¶ 111.
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`Based on the combined teachings of Steinacker, Doyle, and Park, a POSITA
`
`would have understood the voltage detector 5 to be implemented as follows. AP-
`
`PLE-1003, ¶ 113.
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`
`
`
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`5. Motivation to Combine Steinacker, Doyle, and Park
`Steinacker describes that the voltage level detector 5 of circuit arrangement
`
`1 can take the form of an inverter, but leaves selection of an appropriate inverter to
`
`a POSITA. See APPLE-1005, 4:49-55. A POSITA seeking to implement the volt-
`
`age level detector 5 of circuit arrangement 1 would have been motivated to utilize
`
`the inverter shown in FIG. 2 of Doyle, because Steinacker is without details re-
`
`garding the implementation of an inverter and Doyle describes that its inverter “has
`
`a trip point that is relatively stable with respect to temperature and/or to certain
`
`CMOS manufacturing process parameters,” particularly as compared to the basic
`
`well-known CMOS inverter shown in FIG. 2A. See APPLE-1006, 2:37-40, 5:60-
`
`61; see also APPLE-1003, ¶ 108. Moreover, using Doyle’s inverter for the in-
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`verter Steinacker says could be used to implement the voltage level detector 5
`
`would have been simple substitution of one known element (basic well-known
`
`CMOS inverter) for another (Doyle’s improved inverter) to obtain predictable re-
`
`sults. APPLE-1003, ¶ 108.
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`In addition, a POSITA would have found it obvious to utilize the techniques
`
`described by Park to further improve Doyle’s inverter. APPLE-1003, ¶ 112.
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`Doyle’s inverter is a CMOS inverter and Park describes techniques for “reducing
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`leakage power consumption of CMOS circuits.” APPLE-1007, p. 1. Specifically,
`
`Park describes that one “technique to reduce leakage power is transistor stacking.”
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`Attorney Docket No. 39521-0053IP2
`IPR of U.S. Patent No. 8,063,674
`APPLE-1007, 2. As noted by Park, “the stack effect results in substantial sub-
`
`threshold leakage current reduction when two or more stacked transistors are
`
`turned off together.” Id. Thus, seeking to reduce subthreshold leakage current in
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`Doyle’s inverter, a POSITA would have been motivated to replace the individual P
`
`channel transistor 17 and N channel transistor 16 with two transistors each. AP-
`
`PLE-1003, ¶ 112. Again, using Park’s forced stack technique would have been
`
`simple substitution of one known element (a two-transistor inverter) for another (a
`
`four-transistor inverter) to obtain predictable results (improve leakage current). Id.
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`6.
`Claims 8 and 17
`[8.0/17.0] A [method/system] for reducing power consumption in a power on/off
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`control (POC) network of a multiple supply voltage device, said [method/system]
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`comprising:
`
`The combination set forth in Sections III.A.1-5 renders this limitation obvi-
`
`ous. Steinacker describes that, “[i]n communications technology, particularly in
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`mobile radio technology, a circuit arrangement frequently has two circuit blocks
`
`which operate at two different supply voltages.” APPLE-1005, 1:18-20 (emphasis
`
`added). Moreover, as described above in Section III.A.5, supra, the combination
`
`of Steinacker, Doy