United States Patent
`
`[19]
`
`Doyle
`
`[11] Patent Number:
`
`4,717,836
`
`[45] Date of Patent:
`
`Jan. 5, 1988
`
`[54] CMOS INPUT LEVEL SHIFTING CIRCUIT
`WITH TEMPERATURE-COMPENSATING
`N-CHANNEL FIELD EFFECT TRANSISTOR
`STRUCTURE
`
`[75]
`
`Inventor:
`
`James T. Doyle, Tucson, Ariz.
`
`[73] Assignee: Burr-Brown Corporation, Tucson,
`Ariz.
`
`[21] Appl. No.: 825,863 -
`
`[22] Filed:
`
`Feb. 4, 1986
`
`Int. Cl}, ............................................. H03K 17/14
`[51]
`[52] US. Cl. ................................ 307/310; 307/200 B;
`307/443; 307/450; 307/451; 307/475; 307/579;
`307/297; 357/41; 357/51
`[58] Field of Search ............................. 357/28, 41, 51;
`307/200 B, 443, 446, 448, 450, 451, 475, 491,
`570, 572, 573—577, 579, 531, 584—585, 264, 296
`R, 297, 310,290
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`...... 307/450
`4,072,868 2/1978 De La Moneda et a1
`357/20 X
`4,205,342 5/1980 Darwish et a1.
`..
`
`. 307/200 B
`4,209,713 6/1980 Satou et a1.
`..
`4,242,604 12/1980 Smith .................. 307/443
`4,264,874 4/1981 Young .......
`307/451 X
`
`........ 368/87
`4,333,171
`6/1982 Nishikubo
`4,481,521 11/1984 Okumura .............................. 357/23
`
`4,563,601
`4,612,461
`
`.................... 307/443x
`1/1986 Asauo et a1.
`9/1986 Sood ............................... 307/443x
`
`OTHER PUBLICATIONS
`
`“Noise Immunity Improvement of CMOS-CVC Logic
`Circuits”, IBM T.D.B., vol. 27, No. 11, Apr. 1985, p.
`6794.
`
`Primary Examiner—Stanley D. Miller
`Assistant Examiner—D. R. Hudspeth
`Attorney, Agent, or Firm—Cahill, Sutton & Thomas
`
`[57]
`
`ABSTRACT
`
`A CMOS input level shifting circuit includes a tempera-
`ture-compensating N-channel
`field effect
`transistor
`structure wherein a resistance in series with the source
`region includes an extension of a lightly doped P-type
`region in which the source and drain regions are dif-
`fused. This structure produces a temperature-compen-
`sating variation in the drain current proportional to the
`square of the series resistance without requiring modifi-
`cation of standard processes for manufacturing CMOS
`integrated circuits. The relatively large, temperature-
`dependent variation of the series resistance produces a
`corresponding temperature-dependent variation in the
`drain current that effectively temperature-compensates
`the switching point of the CMOS input level shifting
`circuit.
`
`9 Claims, 13 Drawing Figures
`
`
`
`APPLE 1006
`
`APPLE 1006
`
`1
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`

`

`US. Patent
`
`Jan. 5, 1988
`
`Sheet 1 of3
`
`4,717,836
`
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`2
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`

`

`US. Patent
`
`Jan. 5, 1988
`
`Sheet 2 of 3
`
`4,717,836
`
`
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`US. Patent
`
`Jan. 5, 1988
`
`Sheet 3 of 3
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`4,717,836
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`
`

`

`1
`
`4,717,836
`
`CMOS INPUT LEVEL SHIFI'ING CIRCUIT WITH
`
`'I'EMPERATURE-COMPENSATING NoCHAN'NEL '
`FIELD EFFECT TRANSISTOR STRUCTURE
`
`BACKGROUND OF THE INVENTION
`The invention relates to field effect transistor struc-
`tures, and more particularly to temperature-compen-
`sated field effect transistor circuits and to inverting
`CMOS circuits having trip points or switching points
`that are compensated for variations in temperature and
`are relatively independent of certain manufacturing
`process parameter variations.
`MOS field effect transistors (MOSFETs) produce
`drain currents that vary considerably with temperature.
`The MOSFET threshold voltages are heavily depen-
`dent on various manufacturing process parameters,
`especially the thicknesses of the gate oxide and the
`doping levels of the semiconductor region in which the
`MOSFET source and drain regions are diffused. MOS-
`FET threshold voltages also are quite dependent upon
`the temperature of the device. Those skilled in the art
`know that MOSFETs are widely used in manufacture
`of high density, high performance integrated circuits.
`CMOS (complementary metal oxide semiconductor)
`integrated structures include both P-channel and N-
`channel MOSFETs configured to produce very high
`speed, low power, high performance integrated circuits.
`It is usually desirable to interface CMOS integrated
`circuits with input circuitry and output circuitry that is
`implemented in other integrated circuit technologies,
`especially the TTL (transistor-transistor logic) technol-
`ogy, which is capable of producing large output cur-
`rents that may be necessary to drive large line capaci-
`tances and large output loads. The logical “0” and 1"
`levels of standard 'ITL circuits vary considerably. The
`typical range of values for a TTL logical “0” level is 0.3
`volts to zero volts. A typical range of values for a TTL
`“1" level is 3.5 volts to 2.7 volts. Those skilled in the art
`. know that it is very difficult to design an economical
`CMOS input buffer that is of adequately high speed and
`can properly respond to “worst case” values of the
`above ranges of 'I'I'L input levels. This is because the
`“trip point” or “switching point” of a typical CMOS
`inverter structure varies considerably with circuit tem-
`perature and CMOS manufacturing parameters, so that
`“worst case” circuit design of TTL compatible CMOS
`input inverters is very difficult. Further compounding
`the problem is the fact that sometimes it is desirable to
`operate CMOS circuits at power supply voltages other
`than ground and +5 volts, which is the standard TTL
`power supply voltage. CMOS circuits have the charac-
`teristic that they can operate effectively over a wide
`range of power supply voltages, but the percentage
`variation in a CMOS inverter switching point or trip
`point is almost proportional to the percentage variation
`in the power supply voltage. As soon as the power
`supply voltage (Von) of a typical CMOS circuit is in-
`creased, it becomes impossible to drive that circuit with
`standard TTL logic levels. In order to provide good
`noise immunity for a logic circuit, including a CMOS
`logic circuit, it is sometimes desirable to provide hyste-
`resis in the input circuitry of an integrated circuit chip.
`This is commonly done by using input latch circuits
`instead of non-latching input buffers. However, latch
`circuits are more complex and more expensive, espe-
`cially if they are to be responsive to worst case TTL
`input voltage levels. Those skilled in the art know that
`
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`providing hysteresis in a CMOS input circuit further
`complicates the already-difficult design problems en-
`countered in making any CMOS circuit TTL compati-
`ble.
`Those skilled in the art have utilized various modifi-
`cations of standard MOS and CMOS manufacturing
`processes to selectively alter MOS threshold devices to
`achieve effective interfacing of TTL input signals to
`MOS and/or CMOS integrated circuits. However, al-
`teration of any standard manufacturing process to ac-
`complish a specific goal, for example, selectively alter-
`ing MOS threshold voltages of a production process, is
`generally viewed as unacceptably costly and disruptive.
`Despite 15 years of progress in the industry in the
`area of effectively interfacing TTL logic levels to M05
`and CMOS circuitry, there still remains a largely unmet
`need for a truly economical, fast, TTL CMOS input
`circuit for shifting TTL input signals, which input cir-
`cuit is quite independent of MOS manufacturing param-
`eters (such as gate oxide thickness and channel doping
`levels) that affect MOSFET threshold voltages, which
`is relatively independent of temperature, which is rela-
`tively independent of MOS power supply voltages ap-
`plied thereto, and which also has relatively high noise
`immunity.
`
`SUMMARY OF THE INVENTION
`
`Accordingly, it is an object of the invention to pro-
`vide a MOSFET circuit that effectively provides a
`self-compensating MOSFET characteristic.
`It is another object of the invention to provide a
`MOSFET circuit structure that, in effect, produces a
`MOSFET drain current having a predetermined
`amount or range of variation with respect to tempera-
`ture and/or certain MOS processing parameters.
`It is another object of the invention to provide a
`CMOS inverter circuit having a trip point that is rela-
`tively stable with respect to temperature and/or to
`certain CMOS manufacturing process parameters.
`It is another object of the invention to provide a
`stable TTL compatible input circuit in a CMOS inte-
`grated circuit and which provides reliable translation of
`the input 'ITL logic levels over a wide range of temper-
`ature, CMOS processing parameters, and power supply
`voltages.
`.
`Briefly described, and in accordance with one em-
`bodiment thereof, the invention provides a self-compen-
`sating MOS circuit wherein a series resistance that com-
`prises an extension of the region in which the source
`and drain regions of a MOS field effect
`transistor
`(MOSFET) are diffused provides effective compensa-
`tion of the drain current of the field effect transistor
`with respect to the temperature of the circuit and also
`with respect to variations in MOS manufacturing pa-
`rameters, such as gate oxide thickness and doping of the
`channel region, that effect the MOS threshold voltage.
`In the described structure, the voltage drop across the
`series resistance due to flow of drain current therein
`results in an increase in the effective MOSFET thresh-
`old voltage of the “composite” MOSFET in which the
`series resistance is “lumped" with the intrinsic source
`resistance. An increase in the temperature, which nor-
`mally increases the MOS threshold voltage, produces a
`decrease in the series resistance, causing a temperature-
`compensating decrease in the effective MOSFET
`threshold voltage of the MOSFET. In the described
`embodiment of the invention,
`the self-compensating
`
`5
`
`

`

`‘
`
`3
`MOS circuit is contained in a CMOS inverting circuit as
`an inverter pull-down MOSFET having its drain elec-
`trode connected to the drain electrode of a P-channel
`pull-up MOSFET, the gates of both the pull-up MOS-
`FET and the pull-down MOSFET being connected to
`an input conductor to which a 'ITL logic signal is ap-
`plied. A second P—channel pullup MOSFET is provided
`in parallel with the first, and has its gate coupled to a
`feedback signal produced by a second CMOS inverting
`stage in order to provide a “polarized” hysteresis char-
`acteristic of the MOS level shifting circuit, making the
`trip point or switching point of the MOS level shifting
`circuit relatively independent of the power supply volt-
`age applied across the CMOS level shifting circuit. The
`lightly doped P-type “well” or “tu ” region in which
`the heavily doped N-type source and drain of the N-
`channel MOSFET are diffused is electrically shdrted to
`the source of the N-channel MOSFET transistor by
`means of a source contact to a heavily doped P—type
`contact region formed in the lightly doped P—type tub
`region. The described circuit provides a TTL-compati-
`ble CMOS input circuit that provides effective, inex-
`pensive, high speed interfacing to worst case applied
`TTL levels despite wide ranges in the P-channel MOS
`threshold voltages, N-channel MOS threshold voltages
`and despite wide variations in temperature. The CMOS
`input circuit also can be designed to properly respond to
`'ITL input levels when high power supply voltages are
`applied to the CMOS input level shifting circuit.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram of a typical CMOS inverter trans-
`fer characteristic.
`FIG. 2 is a schematic circuit diagram of a self adjust-
`ing TTL compatible input circuit according to the pres—
`ent invention.
`FIG. 2A is a circuit diagram of a conventional
`CMOS inverter.
`FIGS. 3A and 3B are inverter transfer chracteristics
`useful in describing the operation and advantage of the
`circuit of FIG. 2.
`FIG. 4A is a circuit diagram of a self-adjusting MOS-
`FET circuit used in the circuit of FIG. 2.
`FIG. 4B is a schematic diagram of a prior art source
`follower circuit included for explaining, by way of
`comparison, the operation of the circuit of FIG. 4A.
`FIG. 5 is a plan view of a integrated circuit CMOS
`layout of the circuit of FIG. 4A.
`FIG. 5A is a plan view of an integrated circuit mask
`CMOS layout wherein the resistor R is external to the
`P’ well region transistors are used.
`FIG. 6 is a graph illustrating the variation in the trip
`point of the circuit of FIG. 2 as a function of tempera-
`ture and value of the resistance connected in series with
`the source of the input MOSFET.
`FIG. 7 is a graph illustrating variation of the trip
`point of the circuit of FIG. 2 as a function of variation
`in the series resistance connected to the source of the
`input MOSFET of the circuit of FIG. 2.
`FIG. 8 is a graph illustrating the value of change in
`the trip point as a function of the resistance in series
`with the source of the input MOSFET.
`FIG. 9 is a graph illustrating the resistivity of the
`resistance connected in series with the source of the
`integrated circuit structure of FIG. 5 as a function of
`temperature for two different MOS manufacturing pro-
`cesses.
`
`4,717,836
`
`4
`
`DESCRIPTION OF THE INVENTION
`
`In describing the present invention, it may be helpful
`to first describe the basic well-known CMOS inverter
`structure and its transfer characteristic and to also de-
`fine its “trip point” or switching point. Referring to
`FIG. 2A, the CMOS inverter includes an N channel
`MOSFET l6 and a P channel MOSFET 17, each hav-
`ing its source connected to its “bulk” or “substrate”
`terminal, i.e., to the relative lightly doped region in
`which its heavily doped source and drain regions are
`different. Reference number 17A designates the bulk
`terminal of P channel MOSFET 17 and reference nu-
`meral 16A designates the bulk terminal of N channel
`MOSFET 16. The sources of MOSFETs 16 and 17 are
`connected, respectively, to ground and +VDD. The
`gates of MOSFETs 16 and 17 are both connected to
`V9,. The drains of MOSFETs 16 and 17 are both con-
`nected to V0,“.
`A “transfer characteristic” useful in understanding
`the switching operation of the CMOS inverter of FIG.
`2A is shown in FIG. 1. It is assumed that the input
`voltage V9. is very slowly increased from O to +5 volts,
`so that any delay between Vin and V0,” is negligible. It
`is further assumed that VDD is equal to +5 volts. The
`plot of Vm versus time is designates by curve 1. It is
`assumed that the geometries of MOSFET 16 and 17 are
`designed so that they have essentially equal, but com-
`plementary drain current characteristics.
`As the Vin curve 2 increases from 0 volts toward +5
`volts, as indicated by reference numeral 2A, a point is
`reached at which Va,“ decreases sharply (with respect
`to time) from +5 volts to 0 volts, as indicated by seg-
`ment 1A of V0,“ curve 1. The point at which Va.“ is
`equal to Vin is designated by reference numeral 3, and is
`defined as the trip point or switching point of the
`CMOS inverter.
`In CMOS integrated circuits, the trip point is often
`defined to be midway between VDD and ground, which,
`in the present example, would be +2.5 volts, source
`VDD is +5.0 volts.
`Those skilled in the art know that the actual value of
`the trip point of a CMOS inverter is highly dependent
`upon certain CMOS manufacturing process parameters,
`especially the threshold voltages of the P and N channel
`MOSFETS, and of course, the parameters that deter-
`mine those threshold voltages, including the doping
`levels in the channel regions and gate oxide thicknesses.
`The value of the trip point of a particular CMOS in-
`verter circuit also varies considerably as its temperature
`varies over the typical specification range, about ~50‘
`Centigrade to 150‘ Centigrade, in which CMOS inte~
`grated circuits are expected to reliably operate. Varia-
`tions in the source-to-drain spacing (i.e., the channel
`length), which can be affected by photo etching param-
`eters and diffusion parameters, cause variations in the
`trip point voltage of a CMOS inverter.
`The range within which the trip point voltage of
`point 3 of FIG. 1 can be expected to vary for a typical
`CMOS manufacturing process is bounded by dotted
`lines 4A and 4B in FIG. 1, Le, between about +1.5
`volts and about +3.5 volts. The 2 volt difference desig-
`nated by reference numeral 40 represents a 40% varia-
`tion in the trip point voltage of a typical CMOS inte-
`grated circuit inverter resulting from normal CMOS
`process parameter variations, expressed as a percentage
`of the VDD value of 5 volts.
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`4,717,836
`
`5
`interfacing CMOS inte-
`As previously explained,
`grated circuits with TTL logic circuitry, which usually
`produces a maximum logical “0” level of 0.8 volts and
`a minimum “1” level of +2.0 volts, is a longstanding
`problem. Note that the 1.2 volt difference between
`those two levels is much less than the 2 volt range for
`the trip point of a typical CMOS inverter of FIG. 1.
`Also note that the 1.5 bolt lower end of the 2 volt trip
`point voltage range for a typical CMOS inverter is
`shifted upward about 0.7 volts from the upper worst
`case TTL “0” level of 1.2 volts. These considerations
`obviously may cause difficulty in applying 'I'I‘L output
`levels directly to inputs of CMOS integrated circuits
`operating between the same power supply voltage lev-
`els.
`By varying the ratio of the channel widths of the P
`channel and N channel MOSFETs 16 and 17, the volt-
`age of trip point 3 can be lowered to the middle of the
`preferred 0.8 volt to 2.0 volt range that is desirable for
`interfacing with TTL logic circuits, but even if this is
`done, the variation of the trip point of the CMOS in-
`verter with normal processing parameters may result in
`non-symmetrical noise margins, which usually is unde-
`sirable, and sometimes may result in circuit inoperabil‘
`ity even in the absence of noise.
`Those skilled in the art know that CMOS integrated
`circuits have a theoretical advantage in that they can be
`operated over a wide range-of power supply voltages.
`This is because the trip point of a conventional CMOS
`inverter increases proportionally to increases in Vpp.
`However, the above-mentioned “window” or range of
`variation in the trip point voltage with respect to nor-
`mal CMOS manufacturing process variations also in-
`creases. For example, if the VDD voltage of the CMOS
`inverter of FIG. 3A is increased from +5 volts to + 15
`volts, the trip point voltage 3 would increase from 2.5
`volts to 7.5 volts, and the voltage of dotted line 4A
`would increase from 3.5 volts to 10.5 volts and the
`voltage of dotted line 4B would increase from 1.5 volts
`to +4.5 volts. Obviously, the CMOS inverter circuit
`would no longer have any possibility of being driven by
`TTL logic levels.
`Referring to FIG. 3A, what would be desirable
`would be to have a CMOS input level shifter circuit
`that could operate with VDD equal to + 15 volts and
`have the shown transfer characteristic. The dotted lines
`4A' and 4B’ in FIG. 3A designate the trip point range
`for the same CMOS inverter (or the one whose transfer
`circuit is shown in FIG. 1) with VDD equal + 15 volts
`instead of +5 volts. Dotted lines 8A and 8B, at voltage
`levels of +2.0 volts and +0.8 volts, respectively, desig-
`nate the desired maximum range of the trip point for
`good interfacing with TTL logic levels.
`The problem faced in designing such a TTL-compati-
`ble CMOS interface circuit,
`then (with VDD= + 15
`volts), is to reduce the CMOS inverter minimum trip
`point voltage from 4.5 volts to +0.8 volts, to reduce the
`maximum CMOS inverter trip point from 10.5 volts to
`2.0 volts.
`
`With this background in mind, the CMOS input cir-
`cuit 15 of the present invention is shown in FIG. 2. P
`channel MOSFET 17 and N channel MOSFET 16 have
`their gates connected to Vin and their drains connected
`to conductor 21. Their respective structures and func-
`tions are similar to those of P channel MOSFET 17 and
`N channel MOSFET 16 in the conventional CMOS
`inverter of FIG. 2A. However, and in accordance with
`the present invention, the bulk terminal 16A of the N
`
`6
`channel MOSFET 16 is not connected to ground. In-
`stead, bulk terminal 16A and the source of N channel
`MOSFET are connected to one terminal of resistor R,
`the other terminal of which is connected to ground.
`The portion of FIG. 2 just described constitutes the
`most basic embodiment of the input level shifting circuit
`of the present invention. However, in accordance with
`a more preferred embodiment of the CMOS input level
`shifting circuit, a second inverter including P channel
`MOSFET 19 and N channel MOSFET 20 has its input
`connected to V0.“ conductor 21. The structure of in-
`verter 19, 20 can be identical to the structure of the
`conventional CMOS inverter of FIG. 2A. Its output is
`connected to conductor 25. Feedback is provided from
`the output conductor 25 to #the gate of a P channel
`MOSFET 18 connected in parallel with P channel
`MOSFET 17. The bulk terminal 18A of P channel
`MOSFET 18 is connected to +Vpp.
`If desired, the input of an inverter driver can be pro-
`vided, which inverter driver includes P channel MOS-
`FET 22 and N channel MOSFET 23, connected as
`shown. Those skilled in the art will recognize that the
`bulk electrodes of the N channel MOSFETs such as 20,
`23 can be connected to a reference voltage below
`ground. The “ground” reference shown in FIG. 2 can
`be lower than the “ground” or common reference of the
`'ITL circuits supplying the input voltages.
`The transfer characteristics shown in FIGS. 3A and
`3B show the V;,, and V9... voltages of input level shifting
`circuit 15, assuming that VDD is +15 volts and also
`assuming that the slopes of the input signal Vin are such
`that delay between Vin and V0.“ is negligible. The
`curves of FIG. 3A show V9. and V0.“ when V1,. is re-
`duced slowly from + 15 volts to 0 volts. Vin decreases
`slowly, as indicated by segment 6A, until a first trip
`point 8 is reached, at which time V0,“ increases sharply
`(with respect to time) from 0 volts to +15 volts, as
`indicated by segment 7A of Van: Waveform 7. The
`MOSFET device geometries are selected so that the
`trip point voltage, designated by dotted line 41, has a
`nominal value of 1.5 volts.
`The operation of input level translating circuit 15 is
`such that initially P channel MOSFETs 17 and 18 are
`both off. P channel MOSFET 17 is off because Vb. is
`equal to VDD. P channel MOSFET 18 is off because
`Vmis 0 volts, so the voltage on conductor 25 is +VDD
`volts. Initially, N channel MOSFET 16 fully on. As Vin
`decreases, P channel MOSFET 17 bedomes gradually
`turned on, while N channel MOSFET 16 is gradually
`turned off, causing V9.“ to increase slightly. By the time
`the voltage of trip point 8 is reached Vmis increasing
`rapidly. CMOS inverter 19, 20 subsequently switches,
`causing the voltage of conductor 25 to go to ground,
`fully turning on P channel MOSFET 18. Parallel P
`channel MOSFETs 17 and 18 then rapidly pull Va.“ up
`to + 15 volts.
`V
`Referring now to FIG. 3B, the opposite switching of
`input level shifting circuit 15 occurs, wherein V,-,, is
`initially 0 volts and slowly increases to +15 volts. N
`channel MOSFET 16 initially is completely off, and P
`channel MOSFET 17 initially is completely on. V0,,“ is
`at +15 volts, so the voltage on conductor 25 is at 0
`volts, causing P channel MOSFET 18 also to be on. As
`Vin gradually increases from 0 volts up to trip point 8A,
`N channel MOSFET 16 begins to turn on, at a rapid
`rate with respect to time while P channel MOSFET 17
`begins to turn off. However, until trip point 8A is
`reached, P channel MOSFET 18 remains fully on. It
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`4,717,836
`
`7
`can be seen that the voltage level of trip point 8A in
`FIG. 3B, designated by dotted line 42, is significantly
`higher than the voltage of trip point 8 in FIG. 3A, since
`both P channel MOSFETs 17 and 18 are on, rather than
`only P channel MOSFET 17.
`The voltage level of trip point 8 designated by dotted
`line 41 in FIG. 3A is also superimposed on FIG. 3B, and
`the voltage difference between the two trip point volt-
`ages 8 (FIG. 3A) and 8A (FIG. 3B) is designated by
`reference numeral 43, and represents the hysteresis of
`input level translating circuit 15.
`As V,-,, increases past trip point 8A in FIG. 3B, V0.“
`decreases further; by then, the voltage V0,“, on conduc-
`tor 25 has risen high enough to turn P channel MOS-
`FET 18 completely off, and V;,. has also decreased
`enough to turn P channel MOSFET 17 completely off.
`In accordance with the present invention, the circuit
`consisting of N channel MOSFET 16 with both its
`source and bulk terminals connected to resistor R, func-
`tions as a “self-compensating” MOSFET, wherein the
`resistance of resistor R can be selected to cause trip
`points 8 and 8A (FIGS. 3A and 3B, respectively), to be
`very independent of temperature and certain processing
`parameter variations. In order to understand the opera-
`tion of the combination of N channel MOSFET 16 and
`resistor R, it will be helpful to refer to FIG. 4A, which
`repeats the connection of N channel MOSFET 16 and
`resistor R shown in FIG. 2, and to compare the opera—
`tion of that circuit with the similar, but significantly
`different, configuration shown in FIG. 4B. The differ-
`ence between the configuration shown in FIGS. 4A and
`4B is that the bulk terminal 16A of MOSFET 16 is
`connected to the source of N channel MOSFET 16 in
`FIG. 4A but is connected to ground in FIG. 4B. This is
`a subtle but important difference, because the “bulk
`term” in the equation for the threshold voltage of N
`channel MOSFET 16 during circuit operation increases
`as the voltage of the source of MOSFET 16 increases.
`Those skilled in the art know that the threshold voltage
`_ of MOSFET 16 in FIG. 4B rises sharply as the source
`voltage rises (due to the well known “body effect” on
`.,the threshold voltage, given by the equation:
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`8
`to temperature variations and process parameter varia-
`tions that affect the P channel MOSFET threshold and
`the N channel MOSFET threshold. Before further ex-
`plaining this statement, however, it will be helpful to
`now describe CMOS integrated circuit layout the struc-
`ture shown in FIG. 5, which is a basic CMOS integrated
`circuit implementation of the self-adjusting MOSFET
`circuit shown in FIG. 4A.
`In FIG. 5, reference numeral 27 designates the self-
`compensating MOSFET circuit, wherein a P- type
`“we ”' or “tub” region is formed in an N type substrate
`29. In the upper portion of P- well 28, a pair of N +
`drain and source regions 30A and 303, respectively, are
`formed, using any of a variety of well-known silicon
`gate CMOS manufacturing processes, in order to form
`N channel MOSFET 16. Gate electrode 32, which may
`be doped polycrystalline silicon, overlies the channel
`region 32A extending between the drain 30A and the
`source 3013 of the N channel MOSFET 16. Reference
`numeral 33 designates a metal drain contact conductor
`that makes ohmic connection through an oxide opening
`34 to N+ drain region 30A. The drain current In flows
`through metal conductor 33.
`A P+ region 31 is diffused in P“ well 28 adjacent to
`the lower end of N+source region 30B, hence making
`ohmic electrical contact to P‘ well 28. A metal conduc-
`tor 35 electrically connects N+ source region 308 to
`P+ region 31 and hence to P- well 28, which forms the
`bulk terminal of N channel MOSFET 16, thereby short—
`ing it to the source, as shown in FIG. 4A.
`In accordance with a preferred embodiment of the
`present invention, the P— well region 28 extends down-
`ward a predetermined distance to a point at which a P +
`contact region 38 is diffused in the lower portion of P-
`well 28. An electrical conductor 39 connected to
`ground also makes ohmic contact to P+ region 38, and
`hence to the lower portion of P— well 28 through oxide
`opening 40. The region 37 of P" well 28 constitutes the
`resistor R, as indicated by dotted line distributed resis-
`tors 37A.
`Those skilled in the art will realize that the resistance
`of the distributed resistor R decreases as the doping or
`impurity concentration of P— well 28 increases. Such
`increases in the impurity concentration also increase the
`threshold voltage VTN of N channel MOSFET 16.
`Thus, if an increase in the impurity concentration or the
`nominal or design value occurs for P* well 28, the
`threshold voltage of N channel MOSFET 16 will in-
`crease. Ordinarily, this would decrease the drain cur-
`rent ID by an amount proportional to the square of the
`resulting increase in the threshold voltage VTN. How-
`ever, since the resistance of resistor R also decreases, it
`can be seen that the value of gate-to-source voltage
`VGS of N channel MOSFET 16 increases, offsetting or
`compensating the decrease in VTN caused by the corre-
`sponding increase in impurity concentration of P— well
`28.
`In accordance with the present invention, the nomi-
`nal value of resistance of resistor R can be selected to
`provide an optimal amount of compensation of the vari-
`ation of Vm caused by normal variations in the impu-
`rity concentration of P— well 28, and to also provide
`controlled variation of ID necessary to compensate the
`trip point of the circuit of FIG. 2 for variations in the N
`channel MOSFET threshold VTN and the P channel
`MOSFET threshold VTP that are in turn caused by
`
`,
`
`VT= VTo+ 7( iZtPF-l- Vss — q2951")
`
`(I)
`
`45
`
`0X
`where'y = 124W (73L) ,
`
`(bfbeing the Fermi potential of the material, Cox being
`the gate oxide capacitance per unit area, N being the
`impurity concentration of the'bulk material, and V55
`being the source—to-bulk voltage, which is zero for FIG.
`4A, and is greater than zero for FIG. 4B), whereas the
`threshold voltage of MOSFET 16 in FIG. 4A remains
`constant and independent of the source voltage of
`MOSFET 16.
`Those skilled in the art also know that the drain cur—
`rent ID is proportional to the square of the difference
`between the gate-to-source voltage and the threshold
`voltage. Therefore, the drain current I]; of the self-com-
`pensating MOSFET circuit of FIG. 4A is more sensi-
`tive to changes in VGs than the circuit in FIG. 4B.
`In accordance with the present invention, and as
`explained in more detail hereinafter, this phenomena is
`used to great advantage in order to provide automatic
`adjustment for or compensation of the trip point voltage
`of a CMOS inverter or inverter-like circuit with respect
`
`50
`
`55
`
`60
`
`65
`
`8
`
`

`

`4,717,836
`
`9
`variations in temperature and certain processing param-
`eters.
`Those skilled in the art know that the resistance of the
`resistor R in FIG. 5 increases as the temperature in-
`creases. If the N channel MOSFET threshold voltage 5
`VTN were constant, this increase in the resistance of
`resistor R would cause an undesirable decrease in ID.
`However, the value of VTN actually decreases with
`temperature, so the above-mentioned increase in the
`resistance of resistor R automatically tends to compen-
`sate for the normal decrease in an with temperature.
`As a practical matter, the resistance of resistor R can
`be selected to produce a partial or predetermined “com-
`pensation" of changes in the threshold voltage VTN
`with temperature to produce a desired variation in ID 15
`with temperature. In accordance with the present in-
`vention, this variation in In is used to compensate for
`the variation in the threshold voltage of the P channel
`MOSFET 17 with variations in temperature.
`The equation for the currents in the circuit of FIGS.
`4A and 4B is
`
`10
`
`20
`
`ID:
`
`
`Zan
`II
`L
`
`(VG-IoR — V732
`
`(2)
`
`25
`
`where Vris given by equation (1), Zn and L" are the
`channel width and channel length of the MOSFET 16,
`and B. is a constant that is proportional to the mobility
`of the bulk material. My simulations of the operation of
`the circuits of FIGS. 4A and 4B using the above equa- 30
`tions show that the effect of the direct source-to-bulk
`connection of FIG. 4A, with the resistor R being
`formed in the bulk material in which the source and
`drain are formed, is to effectively compensate the cur-
`rent Ip for increases in the threshold voltage and de-
`creases in the mobility of the bulk material with respect
`to temperature.
`.
`In accordance with the present invention, the varia-
`tion in the resistivity of the region 37 of P- well 28 can
`be controlled by controlling the doping level of P- well
`28. Those skilled in the art know that high resistivity
`semiconductor material has a greater variation with
`respect to temperature than low resistivity semiconduc-
`tor material. As a result of this phenomena, and in ac-
`cordance with the present invention, it may be desirable
`to provide substantially higher resistivity material in a
`region 37 of P- well 28 than elsewhere therein. In this
`event, an alternate manufacturing technique can be
`provided wherein the I" well region 28 is diff