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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-01316
`Patent 8,063,674
`______________________
`
`PATENT OWNER RESPONSE TO PETITION FOR INTER PARTES
`REVIEW PURSUANT TO 37 C.F.R. § 42.220
`
`
`
`
`
`

`

`A. 
`
`
`TABLE OF CONTENTS
`INTRODUCTION ......................................................................................... 1 
`I. 
`II.  THE ALLEGED GROUNDS OF UNPATENTABILITY ........................ 4 
`III.  OVERVIEW OF THE ’674 PATENT ......................................................... 4 
`IV.  CLAIM CONSTRUCTION .......................................................................... 8 
`V. 
`LEVEL OF ORDINARY SKILL IN THE ART ........................................ 9 
`VI.  OVERVIEW OF THE CITED REFERENCES ......................................... 9 
`A.  Overview of Steinacker ....................................................................... 9 
`B.  Overview of Doyle ............................................................................. 11 
`C.  Overview of Park ............................................................................... 13 
`D.  Overview of Majcherczak ................................................................. 16 
`E.  Overview of Matthews ...................................................................... 17 
`VII.  GROUNDS 2(a) AND 2(b) ARE IMPROPER BECAUSE INTER
`PARTES REVIEW CANNOT BE BASED ON AAPA ............................ 18 
`
`VIII. 
`AAPA AND MAJCHERCZAK DO NOT RENDER CLAIMS 8, 9,
`
`12, 13 AND 17-21 OBVIOUS (GROUND 2a) ................................. 20 
`The POSA Would Not Combine the Alleged AAPA and
`Majcherczak as Proposed by Petitioner .......................................... 21 
`The Addition of Majcherczak’s Transistor M6 to the AAPA
`1. 
`
`Results in Increased Leakage Current, and the POSA
`
`Would Therefore Not Make This Combination ................... 22 
`2. 
`The Proposed Combination of the AAPA and Majcherczak
`
`Also Results in Increased Leakage Current Compared to
`
`Majcherczak. ........................................................................... 26 
`3. 
`The Combination of AAPA and Majcherczak Proposed by
`
`Petitioner Would Result in a DC Fighting Condition and
`
`Increased Glitch Current During Turn-On Transitions. .... 28 
`IX.  AAPA, MAJCHERCZAK, AND MATTHEWS DO NOT RENDER
`
`CLAIMS 16 AND 22 OBVIOUS (GROUND 2b) ..................................... 31 
`X. 
`STEINACKER, DOYLE, AND PARK DO NOT RENDER CLAIMS 8,
`
`9, 12, 13 AND 16-22 OBVIOUS (GROUND 1) ......................................... 32 
`The Petition Does Not Sufficiently Articulate Why a POSA Would
`A. 
`
`Have Been Motivated to Combine Steinacker, Doyle, and Park. . 33 
`The Proposed Combination of Steinacker, Doyle and Park
`1. 
`
`is Based On Impermissible Hindsight Reconstruction ........ 33 
`2. 
`The Reasons Given by Petitioner for Combining Steinacker,
`
`Doyle and Park are Generic Statements Divorced from the
`
`Prior Art Elements .................................................................. 42 
`
`

`

`The POSA Would Not Have Selected the Forced Stack
`3. 
`Technique Over the Sleepy Stack Technique Described in
`
`Park .......................................................................................... 45 
`
`The POSA Would Not Combine Steinacker, Doyle, and Park as
`B. 
`Proposed by Petitioner Because the Resulting Circuit Would be
`
`Unsuitable for Power-Sensitive Applications ................................. 46 
`
`XI.  CONCLUSION ............................................................................................ 51 
`
`
`

`

`Pursuant to the Board’s Decision – Institution of Inter Partes Review (Paper 7)
`
`(“Institution Decision”), entered January 18, 2019 – Patent Owner Qualcomm, Inc.
`
`(“Qualcomm” or “Patent Owner”) submits this Response in opposition to the
`
`Petition for Inter Partes Review of U.S. Patent No. 8,063,674 (the “’674 Patent”)
`
`filed by Apple Inc. (“Apple” or “Petitioner”).
`
`I.
`
`INTRODUCTION
`Petitioner challenged claims 8, 9, 12, 13 and 16-22 of the ’674 Patent based
`
`on two primary obviousness combinations: (i) Applicant’s Admitted Prior Art
`
`(AAPA) in view of Majcherczak, and (ii) Steinacker in view of Doyle and Park. In
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`its Institution Decision (“Decision”), the Board instituted trial on all grounds and all
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`claims challenged in the Petition. (Paper 7 at 41.) But despite instituting trial, the
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`Board indicated that it agrees with Qualcomm’s Patent Owner Preliminary Response
`
`(POPR) arguments (Paper 6 at 16) that the petition fails to sufficiently articulate why
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`the person of ordinary skill in the art (POSA) allegedly would have been motivated
`
`to combine Steinacker, Doyle, and Park (Paper 7 at 36-40).
`
` For the
`
`AAPA/Majcherczak grounds, however, Qualcomm’s POPR was limited to
`
`procedural arguments (Paper 6 at 27, 34), and the Board found these arguments
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`insufficient to deny institution (Paper 7 at 26-27). As explained in this Response,
`
`Petitioner cannot show that any of the challenged claims are unpatentable.
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`
`
`1
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`

`

`The AAPA/Majcherczak grounds are improper because the America Invents
`
`Act (AIA) only permits inter partes review on the basis of prior art consisting of
`
`patents or printed publications, which literally does not include allegations of
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`admitted prior art. 35 U.S.C. § 311(b). And even if “admitted prior art” were
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`permitted in inter partes review, the POSA would not combine the AAPA and
`
`Majcherczak as Petitioner proposes because the resulting combination would
`
`operate significantly worse than either the AAPA or Majcherczak had they been left
`
`unmodified. There is no legitimate reason why the POSA would make such a
`
`combination. The AAPA/Majcherzcak grounds therefore fail for these reasons and
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`those explained fully below.
`
`The Steinacker/Doyle/Park ground—for which the Board has already
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`“question[ed] the sufficiency of Petitioner’s evidence”—fares no better. In its
`
`Decision, the Board recognized that this ground is deficient, and nothing has
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`changed. Petitioner’s supposed motivation to combine Steinacker, Doyle, and Park
`
`is a textbook example of impermissible hindsight reconstruction, supported only by
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`generic statements that are divorced from the specific references being combined.
`
`Petitioner cannot fix the problems of this deficient ground, and the Board should
`
`reject any attempts by Petitioner to do so. See Intelligent Bio-Systems, Inc. v.
`
`Illumina Cambridge Ltd., 821 F.3d 1359, 1369-70 (Fed. Cir. 2016) (petitioner must
`
`
`
`2
`
`

`

`“make [its] case” in the petition). Moreover, testimony of Qualcomm’s expert, Dr.
`
`Massoud Pedram, further supports the Board’s initial determinations.1
`
`Further, in stark contrast to the testimony of Dr. Pedram, the declaration (Ex.
`
`1003) of Petitioner’s expert, Dr. Robert Horst, provides nothing more than a vague
`
`prior art analysis without addressing the language of a single claim or reaching any
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`conclusions about obviousness. In fact, Dr. Horst readily admits that his declaration
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`fails to provide any conclusions about patentability or any analysis of the specific
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`claims of the ’674 Patent. See Ex. 2003 at 7 (“this document relates to that [‘674]
`
`patent. It’s not specifically calling for conclusions about the patentability… but I
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`did not go through a claim-by-claim analysis and haven’t reported conclusions on
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`each claim in this document.”) Significantly, Petitioner relies on Dr. Horst’s vague
`
`and non-specific declaration testimony in support of its allegations of obviousness –
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`without which Petitioner’s analysis amounts to little more than lawyer rhetoric. But
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`an allegation of obviousness cannot be supported without reference to the specific
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`language of the claims, read in the context of the claim as a whole. See Stratoflex,
`
`Inc. v. Aeroquip Corp., 713 F.2d 1530, 1537 (Fed. Cir. 1983) (In determining the
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`differences between the prior art and the claims, the question under 35 U.S.C. 103
`
`is not whether the differences themselves would have been obvious, but whether the
`
`
`1 The Declaration of Dr. Massoud Pedram is included at Qualcomm Exhibit
`
`2002.
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`
`
`3
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`

`

`claimed invention as a whole would have been obvious). Having admittedly failed
`
`to address any specific claim as a whole in his declaration, Dr. Horst’s testimony
`
`cannot properly support an allegation of obviousness, and should therefore be given
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`little or no weight.
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`For at least these reasons and those detailed below, the patentability of
`
`challenged claims 8, 9, 12, 13 and 16-22 of the ’674 Patent should be confirmed.
`
`II. THE ALLEGED GROUNDS OF UNPATENTABILITY
`Pursuant to the Board’s Decision (Paper 7 at 41), the alleged grounds of
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`unpatentability for this trial are:
`
` Ground 1 – Claims 8, 9, 12, 13 and 16-22 are unpatentable under 35 U.S.C.
`
`§ 103 over Steinacker in view of Doyle and Park;
`
` Ground 2a – Claims 8, 9, 12, 13 and 17-21 are unpatentable under 35
`
`U.S.C. § 103 over AAPA in view of Majcherczak; and
`
` Ground 2b – Claims 16 and 22 are unpatentable under 35 U.S.C. § 103
`
`over AAPA in view of Majcherczak and Matthews.
`
`III. OVERVIEW OF THE ’674 PATENT
`
`U.S. Patent No. 8,068,674 (“the ’674 Patent”), titled “Multiple Supply-
`
`Voltage Power-Up/Down Detectors,” generally relates to power-up/down detectors.
`
`The ’674 Patent issued on November 22, 2011, from an application filed on February
`
`4, 2009.
`
`
`
`4
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`

`

`
`
`Modern integrated circuits include multiple networks operating with different
`
`supply voltages (e.g., V1 and V2). For example, a lower voltage V1 may be used
`
`for a core logic network, while a higher voltage V2 may be used for an input/output
`
`(“I/O”) network. Multiple independent supply voltages provide flexibility in
`
`operating different networks independently, such as being able to turn off parts of
`
`the circuit that are not needed (e.g., sleep mode), which results in significant power
`
`savings. Also, because new integrated circuit devices often interface with older
`
`technology, “input/output (I/O) circuits within the integrated circuit have remained
`
`at higher operating voltages to interface with the higher voltage requirements of
`
`these older systems.” Ex. 1001 (’674 Patent) at 1:22-25.
`
`
`
`The Background section of the ’674 Patent recognizes that many previous
`
`power up/down detectors suffered from problems. For example, the ’674 Patent
`
`explains:
`
`Core devices and applications communicate with operations outside
`of the integrated component through the I/O devices. In order to
`facilitate communication between the core and I/O devices, level
`shifters are employed. Because the I/O devices are connected to the
`core devices through level shifters, problems may occur when the core
`devices are powered-down. Powering down or power collapsing is a
`common technique used to save power when no device operations are
`pending or in progress. For example, if the core network is power
`collapsed, it is possible that the lever shifters, whether through stray
`
`
`
`5
`
`

`

`current or the like, could send a signal to the I/O devices for
`transmission. The I/O devices assume that the core devices have
`initiated this communication, and will, therefore, transmit the erroneous
`signal into the external environment.
`
`Id. at 1:26-40. As another example, the Background section of the ’674 Patent
`
`describes the problem of “glitch” current caused by slow detection speeds in a
`
`previous power up/detector design shown in Fig. 1:
`
`In the situation where I/O power supply 104 is on and core power
`
`supply 103 is off, M1 is switched on with M2 and M3 switched off.
`When core power supply 103 is then powered up, M2 and M3 switch
`on, and M1 becomes very weak. However, before M1 can switch
`completely off, there is a period in which all three transistors within
`power up/down detector 100 are on. Thus, a virtual short is created to
`ground causing a significant amount of current to flow from I/O power
`supply 104 to ground. This “glitch” current consumes unnecessary
`power.
`
`Id. at 2:21-30.
`
`
`
`The ’674 Patent teaches using feedback to increase the speed of the power-
`
`up/down detection while simultaneously reducing power consumption. An example
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`implementation of that feedback is shown below in Figure 4:
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`
`
`6
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`

`

`
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`Id. at Fig. 4. During a power-up transition (i.e., Vcore transitioning from low to high),
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`M8 transitions from being on to off. When M8 is off, the current capacity of the
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`power up/down detector is decreased. See id. at 6:12-18. During a power-down
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`transition (i.e., Vcore transitioning from high to low), M8 transitions from off to on.
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`When M8 is on, the current capacity of the power up/down detector 40 is increased,
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`and the “power up/down detector 40 will detect the Vcore 301 powering down more
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`quickly than the existing POC networks.” Id. at 6:23-28. Thus, the feedback
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`technique disclosed in the ’674 Patent provides fast and energy efficient power
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`up/down detection.
`
`
`
`
`
`Claim 8 of the ‘674 Patent is exemplary:
`
`8. A method for reducing power consumption in a power on/off control
`(POC) network of a multiple supply voltage device, said method
`comprising:
`
`7
`
`

`

`detecting a power-on of a second supply voltage while a first supply
`voltage is already on;
`decreasing a current capacity of a power on/off detector of said POC
`network in response to said power-on detection;
`detecting a power-down of said second supply voltage while said first
`supply voltage is on;
`increasing said current capacity of said power on/off detector in
`response to said power-down detection;
`receiving a logic-high signal at a control gate of at least one first
`transistor, at least second transistor and at least one third transistor
`coupled in series between the at least one first transistor and the at
`least one second transistor, the at least one first transistor being
`configured to switch off in response to said logic-high signal, and the
`at least one second transistor being configured to switch on in
`response to said logic-high signal; and
`transmitting a detection signal to a signal processor from the at least
`one second transistor based on said received logic-high signal.
`
`See also Ex. 2002 at paras. 27-31.
`
`IV. CLAIM CONSTRUCTION
`
`Petitioner states that the term “signal processor” should be construed. (Petition
`
`at 5.) Qualcomm does not believe that this term needs to be construed, and the Board
`
`agreed in its Decision. (Paper 7 at 10.) To the extent the Board determines that it
`
`should construe the term “signal processor” in its Final Written Decision, Qualcomm
`
`agrees with Petitioner’s statement that this term should be construed at least broadly
`
`enough to encompass the embodiment described in the ’674 patent, which is an
`
`inverting amplifier. (Petition at 5.)
`
`
`
`8
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`

`

`
`
`Petitioner also proposes constructions for “means-plus-function” elements of
`
`claims 17-20. In its Institution Decision, the Board determined that no express claim
`
`construction is necessary for any term. (Paper 7 at 10.) For the limited purpose of
`
`these proceedings, Qualcomm does not contest the conclusion of the Board that no
`
`express claim construction is necessary.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`As the Board previously stated, the POSA for the ’674 Patent would have had
`
`an undergraduate degree in electrical engineering, or a related field, and three years
`
`of experience in circuit and system design. (Paper 7 at 13.) The POSA with less
`
`than this amount of experience could have had a correspondingly greater amount of
`
`educational training such as a graduate degree in a related field. (Id.) See also Ex.
`
`2002 at paras. 40-43.
`
`VI. OVERVIEW OF THE CITED REFERENCES
`A. Overview of Steinacker
`U.S. Patent No. 7,279,943 (“Steinacker”), titled “Circuit Arrangement
`
`
`
`Receiving Different Supply Voltages,” generally relates to a “mixed signal” circuit
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`that includes at least one analog circuit and at least one digital circuit that operate at
`
`two different supply voltages. Steinacker issued on October 9, 2007, from an
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`application filed on October 12, 2005.
`
`
`
`9
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`

`

`
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`Steinacker explains that “[t]he invention is based on the problem of providing
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`a circuit arrangement having at least two circuit blocks operating at different supply
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`voltages which is able to ensure reliable operation of the circuit arrangement
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`regardless of turn-on profiles for the different supply voltages in the circuit blocks.”
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`Ex. 1005 (Steinacker) at 2:14-19. An example of Steinacker’s circuit arrangement
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`is set forth in Figure 1 below.
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`
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`
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`Figure 1 of Steinacker (above) shows a first supply voltage domain 1.1 that
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`supplies a first circuit block 2 with a first supply voltage, and second supply voltage
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`domain 1.2 that supplies a second circuit block 3 (and possibly a third circuit block
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`10) with a second supply voltage. Id. at 4:5-12. The basic concept behind
`
`Steinacker’s design is that “the second circuit block is deactivated when the first
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`
`
`10
`
`

`

`supply voltage is still too low in order to ensure safe operation of the first circuit
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`block.” Id. at 2:35-38. This is accomplished using a voltage level detector 5 that
`
`compares the first supply voltage to a threshold and sends a control signal to a
`
`voltage level shifting unit 4, causing the voltage level shifting unit 4 to send a
`
`deactivation signal to the second circuit block 3. Id. at 4:56-5:3. “The second circuit
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`block 3 is shut down if the first supply voltage is too low to ensure the operation of
`
`the respectively supplied logic gates.” Id. at 5:1-3.
`
`
`
`Steinacker provides little detail regarding the makeup of the voltage level
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`detector 5 shown in Figure 1, stating only that “[i]n the illustration, the voltage level
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`detector 5 is in the form of a Schmitt trigger with an inverting output,” and that “it
`
`is likewise conceivable for the voltage level detector 5 to be in the form of an inverter
`
`circuit, a comparator circuit or comparable circuits.” Id. at 4:49-53. See also Ex.
`
`2002 at paras. 46-49.
`
`B. Overview of Doyle
`U.S. Patent No. 4,717,836 (“Doyle”), titled “CMOS Input Level Shifting
`
`Circuit with Temperature-Compensating N-Channel Field Effect Transistor
`
`Structure,” generally relates to an interface between a TTL circuit and a CMOS
`
`circuit. Doyle issued on January 5, 1988, from an application filed on
`
`February 4, 1986.
`
`
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`11
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`

`

`
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`Doyle describes certain objects of “the invention” including “to provide a
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`CMOS inverter circuit having a trip point that is relatively stable with respect to
`
`temperature and/or to certain CMOS manufacturing process parameters,” and “to
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`provide a stable TTL compatible input circuit in a CMOS integrated circuit.”
`
`Ex. 1006 (Doyle) at 2:37-43. An example of Doyle’s TTL compatible input circuit
`
`is shown in Figure 2 below.
`
`
`
`Id. at Fig. 2.
`
`
`
`Doyle teaches a CMOS input level shifting circuit with a temperature-
`
`compensating NFET structure. This is accomplished, as shown in Figure 2, by
`
`adding a resistor “R” in series between the source terminal of the bottom NMOS
`
`transistor 16 and ground. Id. at 5:67-6:4; 2:48-56 (“the invention provides a self-
`
`compensating MOS circuit wherein a series resistance that comprise an extension of
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`the region in which the source and drain regions of a MOS field effect transistor
`
`
`
`12
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`

`

`(MOSFET) are diffused provides effective compensation of the drain current of the
`
`field effect transistor with respect to the temperature of the circuit and also with
`
`respect to variations in MOS manufacturing parameters”). “The described circuit
`
`provides a TTL-compatible CMOS input circuit that provides effective, inexpensive
`
`high speed interfacing to worst case applied TTL levels despite wide ranges in the
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`P-channel MOS threshold voltages, N-channel MOS threshold voltages and despite
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`wide variations in temperature.” Id. at 3:22-27. See also Ex. 2002 at paras. 50-54.
`
`
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`Doyle does not teach or suggest using the disclosed CMOS input level shifting
`
`circuit as a power up/down detector. See Ex. 2002 at para. 54.
`
`C. Overview of Park
`The Park reference is a 2006 IEEE article by Jun Cheol Park and Vincent J.
`
`Mooney III, titled “Sleepy Stack Leakage Reduction.” Park generally relates to a
`
`CMOS circuit structure for reducing leakage power consumption, which the authors
`
`refer to as a “sleepy stack” structure.
`
`
`
`Park claims that their “sleepy stack” CMOS circuit structure provides a
`
`“remedy for static power consumption” existing in prior designs. See Ex. 1007 (Park)
`
`at 1. Specifically, Park’s “sleepy stack” structure combines and improves upon “two
`
`major prior approaches, the sleep transistor technique and the forced stack technique.”
`
`Id. Fig. 1 of Park (reproduced below) illustrates the previous “forced stack” and
`
`
`
`13
`
`

`

`“sleep transistor” techniques that its new “sleepy stack” structure allegedly improves
`
`upon.
`
`Id.
`
`
`
`
`
`
`
`With reference to the “forced stack technique” shown above in Fig. 1, Park
`
`explains that its new “sleepy stack” design “can achieve more power savings than
`
`the forced stack technique,” and more particularly can achieve an improvement of
`
`“up to two orders of magnitude leakage power reduction compared to the forced
`
`stack.” Id. at 1-2. An example of Park’s “sleepy stack” implemented in an inverter
`
`is illustrated in Fig. 2, reproduced below.
`
`
`
`14
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`

`

`
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`Id. at 3.
`
`
`
`
`
`As shown in Fig. 2 (above), Park’s “sleepy stack technique has a structure
`
`merging the forced stack technique and the sleep transistor technique,” where “sleep
`
`transistors are added in parallel to one of the transistors in each set of two stacked
`
`transistors.” Id. Park explains, “The sleepy stack technique has a combined
`
`structure of the forced stack technique and the sleep transistor technique. However,
`
`unlike the sleep transistor technique, the sleepy stack technique retains exact logic
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`state when in sleep mode; furthermore, unlike the forced stack technique, the sleepy
`
`stack technique can utilize high-Vth transistors without 5x (or greater) delay penalties.
`
`Therefore, far better than any prior approach known to the authors of this paper, the
`
`sleepy stack technique can achieve ultra-low leakage power consumption while
`
`saving state.” Id. at 2. See also Ex. 2002 at paras. 55-58.
`
`
`
`15
`
`

`

`
`
`Park includes no teaching or suggestion to use the disclosed “sleepy stack”
`
`transistor structure (or the older “forced stack” structure) as a power up/down
`
`detector. See Ex. 2002 at para. 58.
`
`D. Overview of Majcherczak
`U.S. Patent Application No. 2002/0163364 (“Majcherczak”), titled “Power
`
`
`
`Supply Detection Device,” relates generally to a device that detects the drop in the
`
`supply voltage of the core of an integrated circuit. Apple’s Petition relies on the
`
`power supply detection device of Majcherczak Fig. 2:
`
`
`
`Ex. 1008 (Majcherczak) at Fig. 2.
`
`
`
`The power supply detection device of Fig. 2 is configured to be used with an
`
`integrated circuit having two power supply voltages. In the above figure, the core
`
`supply voltage Vdd “is for a core of the integrated circuit,” and the interface supply
`
`
`
`16
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`

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`voltage Vdd3 “is applied to external interfaces of the integrated circuit and to
`
`input/output interface circuits within the integrated circuit.” Id. at ¶ 0001. The
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`embodiment of Fig. 2 includes a power supply stage E2, an input stage E1 that
`
`receives the core supply voltage Vdd, and an output stage E3. Id. at ¶¶ 0025-26,
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`0037. The output stage E3 includes an inverter IV powered by the interface supply
`
`voltage Vdd3. Id. at ¶ 0037. The output stage E3 further includes “a pull-down
`
`transistor M6 for pulling the output node Nin of the inverter of the input stage to the
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`interface power supply voltage Vdd3. This pull-down transistor M6 is typically a P-
`
`type MOS transistor . . . .” Id. See also Ex. 2002 at paras. 59-63.
`
`E. Overview of Matthews
`Matthews discloses a comparator comparing two voltages, VDD and VDDH.
`
`
`
`If the difference between VDD and VDDH exceeds a threshold, the control outputs
`
`a signal preventing certain pads from operating. See Ex. 1009 (Matthews) at 2:63-
`
`3:4 (“the difference between VDD and VDDH may be greater than any difference
`
`typically present during subsequent operation of system 100 when system 100 is
`
`processing data, possibly by more than a selected threshold amount. In the event of
`
`substantially different inputs, the enable override is asserted to prevent the pads 120,
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`130, and 140 from operating until the VDD input reaches an operational level. ”).
`
`Matthews does not disclose a voltage detector. See also Ex. 2002 at paras. 64-65.
`
`
`
`17
`
`

`

`VII. GROUNDS 2(a) AND 2(b) ARE IMPROPER BECAUSE INTER
`PARTES REVIEW CANNOT BE BASED ON AAPA
`Grounds 2(a) and 2(b) are improper because the America Invents Act (AIA)
`
`does not permit inter partes review based on so-called applicants admitted prior art
`
`(AAPA). The statute is clear, requiring that inter partes review be available “only
`
`on the basis of prior art consisting of patents or printed publications.” See 35 U.S.C.
`
`§ 311(b) (“a petitioner in an inter partes review may request to cancel as
`
`unpatentable 1 or more claims of a patent only on a ground that could be raised under
`
`section 102 or 103 and only on the basis of prior art consisting of patents or printed
`
`publications.”) Portions of the patent under review – which the Petitioner has
`
`characterized as the AAPA – cannot be considered “prior art consisting of patents or
`
`printed publications” within the plain meaning of the statute.
`
`Likewise, the regulations governing inter partes review require that the
`
`petition “specify where each element of the claim is found in the prior art patents or
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`printed publications relied upon.” 37 C.F.R. § 42.104(b)(4). Petitioner relies on
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`portions of the Background section of the ’674 patent as the alleged AAPA in
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`grounds 2(a) and 2(b). But nothing in the portions of the Background section relied
`
`on by Petitioner refers to a prior art patent or printed publication. The Institution
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`Decision concludes that the use of this alleged AAPA is proper because the ’674
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`patent is itself a “patent or printed publication.” See Paper 7 at 21-22. However, the
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`18
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`patent under review cannot reasonably be considered a “prior art patent or printed
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`publication” because the patent is not prior art to itself.
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`In its Institution Decision, the Board relies on prior PTAB decisions in which
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`alleged “AAPA” has been considered in inter partes review, despite the plain
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`meaning of the statute. See Paper 7 at 21-22. The Institution Decision fails, however,
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`to recognize other PTAB decisions that have correctly held that AAPA does not
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`qualify as prior art under Section 311(b). See LG Electronics, Inc. v. Core Wireless
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`Licensing S.A.R.L., IPR2015-01987, Paper 7 at 18 (PTAB Mar. 24, 2016) (ground
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`based on AAPA “does not identify any patents or printed publications” and thus
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`“fails to comply with Section 311(b) or Rule 42.104(b)(4)”); Sony Corp. v. Collabo
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`Innovations, Inc., IPR2016-00940, Paper 7 at 30 (PTAB Oct. 24, 2016) (same).
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`Further, counsel for Petitioner agrees that AAPA is not eligible for inter partes
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`review, as evidenced by arguments recently made by Petitioner’s counsel in
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`IPR2017-00126. See Ex. 2004 (Patent Owner’s Request for Rehearing in IPR2017-
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`00126), see also Ex. 2005 (Patent Owner’s Response in IPR2017-00126) at 41-54.
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`Notably, after having already filed this petition relying on alleged AAPA as
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`Petitioner’s primary reference in Grounds 2(a) and 2(b), Petitioner’s counsel has
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`taken the position with this Board, with a pending appeal to the United States Court
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`of Appeals for the Federal Circuit, that AAPA is “not ‘prior art consisting of patents
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`or printed publications’ and, thus is ineligible for inter partes review.” Ex. 2004 at
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`19
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`3. Petitioner’s counsel further agrees that “37 C.F.R. § 42.104(b)(4) confirms that
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`‘prior art consisting of patents’ refers to ‘prior art patents,’ which cannot include the
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`patent being challenged.” Id. at 5. For these same reasons, Petitioner’s reliance on
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`the alleged AAPA in this petition is improper, and grounds 2(a) and 2(b) should be
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`dismissed.
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`At the very least, in view of the apparent inconsistency between PTAB panels,
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`along with the inconsistent positions taken by Petitioner’s own counsel, this issue
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`should be elevated for Precedential Opinion Panel review should the Board continue
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`its improper consideration of the alleged AAPA.
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`Because the alleged AAPA is not a patent or printed publication, the
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`challenged claims should be held patentable over the combination of AAPA and
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`Majcherczak.
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`VIII. AAPA AND MAJCHERCZAK DO NOT RENDER CLAIMS 8, 9,
`12, 13 AND 17-21 OBVIOUS (GROUND 2a)
`Even if the Board considers the alleged AAPA in these proceedings, despite
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`
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`the plain meaning of the statute limiting inter partes review to patents and printed
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`publications, the challenged claims are not obvious in view of the AAPA and
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`Majcherczak.
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`A. The POSA Would Not Combine the Alleged AAPA
`and Majcherczak as Proposed by Petitioner
`Ground 2a proposes a hypothetical circuit combination (shown below), based
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`on the combination of the power-on/off-control (POC) system shown in Fig. 1 of
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`the ’674 Patent (which the Petitioner refers to as AAPA) and Majcherczak.
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`
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`But as explained below, Petitioner’s proposed combination results in a circuit with
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`numerous operational flaws. In fact, far from an obvious improvement, Petitioner’s
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`proposed AAPA/Majcherczak combination would operate significantly worse than
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`either the AAPA or Majcherczak had they been left unmodified. See Ex. 2002 at
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`paras. 67-85. The POSA would therefore have had no reason to combine the alleged
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`AAPA and Majcherczak as Petitioner proposes, and challenged claims 8, 9, 12, 13
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`and 17-21 are not obvious.
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`21
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`1.
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`The Addition of Majcherczak’s Transistor M6 to the AAPA
`Results in Increased Leakage Current, and the POSA
`Would Therefore Not Make This Combination
`The feedback circuits described and claimed in the ’674 Patent are intended
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`to reduce leakage current while also improving power-up/down detection speed. See
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`Ex. 1001 (’674 Patent) at Abstract (“For reducing the leakage current while also
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`improving the power-up/down detection speed, the feedback circuit(s) are coupled
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`to the adjustable current power up/down detector ....”); 3:10-11 (“[T]he conventional
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`solutions still have problems with leakage and Switching times.”); 5:34-36 (“This
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`decrease in current capacity will limit and reduce the amount of leakage current that
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`may be dissipated through the power up/down detector ....”); 6:67-7:4 (“Thus, the
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`configuration of the POC ... operates to detect the Vcore 301 powering on faster than
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`the existing POC networks, while still reducing the amount of leakage current while
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`the Vcore 301 is on.”).
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`By contrast, Petitioner’s proposed addition of Majcherczak’s transistor M6 to
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`Fig. 1 of the ’674 Patent (the alleged AAPA) results in increased leakage current,
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`and the POSA would not be motivated to make Petitioner’s proposed combination
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`for at least this reason. See Ex. 2002 at para. 70. Petitioner argues that “[b]ased on
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`the teachings of Majcherczak, a POSITA would have found it obvious to integrate
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`the feedback transistor M6 from Majcherczak’s voltage detector into the POC
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`system 10 of the AAPA.” Petition at 51. But during periods when the Vcore voltage
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`22
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`in Fig. 1 of the ’674 Patent is on, i.e., in a high state, the power U/D detector design
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`shown in Fig. 1 of the ’674 Patent (the alleged AAPA) would result in a large amount
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`of leakage current from VI/O to VSS. See Ex. 2002 at para. 70. Moreover, the addition
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`of Majcherczak’s transistor M6 would result in increased leakage current in the
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`power-up/down detector 100 because the transistor M6 adds a leakage path. See id.
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`As shown in the diagram below, Apple’s proposed combination includes a
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`“feedback network” from Majcherczak (highlighted in blue) that is coupled in
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`parallel with the single PMOS transistor (M1) in the pull-up portion of the power
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`U/D