Trials@uspto.gov
`Tel: 571-272-7822
`
`Paper 7
`Entered: January 18, 2019
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Cases IPR2018-01316
`Patent 8,063,674 B2
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`HOWARD, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`Tel: 571-272-7822
`
`Paper 7
`Entered: January 18, 2019
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Cases IPR2018-01316
`Patent 8,063,674 B2
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`HOWARD, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`IPR2018-01316
`Patent 8,063,674 B2
`
`I.
`
`INTRODUCTION
`
`Apple Inc. (“Petitioner”) filed a Petition to institute an inter partes
`
`review of claims 8, 9, 12, 13, and 16–22 of U.S. Patent No. 8,063,674 B2
`
`(Ex. 1001, “the ’674 patent”) pursuant to 35 U.S.C. §§ 311–319. Paper 2
`
`(“Petition” or “Pet.”). Qualcomm Incorporated (“Patent Owner”) filed a
`
`Patent Owner Preliminary Response. Paper 6 (“Preliminary Response” or
`
`“Prelim. Resp.”).
`
`We have authority, acting on the designation of the Director, to
`
`determine whether to institute an inter partes review under 35 U.S.C. § 314
`
`and 37 C.F.R. § 42.4(a). Inter partes review may not be instituted unless
`
`“the information presented in the petition filed under section 311 and any
`
`response filed under section 313 shows that there is a reasonable likelihood
`
`that the petitioner would prevail with respect to at least 1 of the claims
`
`challenged in the petition.” 35 U.S.C. § 314(a). On April 24, 2018, the
`
`Supreme Court held that a decision to institute under 35 U.S.C. § 314 may
`
`not institute on fewer than all claims challenged in the petition. SAS Inst.,
`
`Inc. v. Iancu, 138 S. Ct. 1348, 1359–60 (2018).
`
`For the reasons set forth below, upon considering the Petition,
`
`Preliminary Response, and evidence of record, we determine that the
`
`information presented in the Petition establishes a reasonable likelihood that
`
`Petitioner will prevail with respect to at least one of the challenged claims.
`
`Accordingly, we institute inter partes review on all of the challenged claims
`
`based on the all of the grounds identified in the Petition.
`
`A.
`
`Real Party-In-Interest
`
`Petitioner identifies Apple, Inc. as the real party-in-interest. Pet. 76.
`
`2
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`Patent 8,063,674 B2
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`B.
`
`Related Proceedings
`
`The parties identify the following currently pending patent litigation
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`proceedings in which the ’674 patent is asserted: In re Certain Mobile
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`Electronic Devices and Radio Frequency and Processing Components
`
`Thereof (ITC Inv. No. 337-TA-1093) and Qualcomm Inc. v. Apple Inc., Case
`
`No. 3:17-cv-02398 (S.D. Cal.). Id. at 76–77; Paper 3, 2. Patent Owner
`
`identifies a second inter partes review for the ’674 patent: Apple Inc. v.
`
`Qualcomm Inc., Case IPR2018-01315. Paper 3, 2.
`
`C.
`
`The ’674 Patent
`
`The ’674 patent is titled “Multiple Supply-Voltage Power-Up/Down
`
`Detectors.” Ex. 1001, [54]. According to the ’674 patent, “many newer
`
`integrated circuit devices include dual power supplies: one lower-voltage
`
`power supply for the internally operating or core applications, and a second
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`higher-voltage power supply for the I/O circuits and devices.” Id. at 1:22–
`
`25.
`
`The ’674 patent further states that “[i]n order to facilitate
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`communication between the core and I/O devices, level shifters are
`
`employed.” Id. at 1:28–29. However, “[b]ecause the I/O devices are
`
`connected to the core devices through level shifters, problems may occur
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`when the core devices are powered-down.” Id. at 1:29–32. An example of
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`such a problem described in the ’674 patent is how stray currents while the
`
`core is powering down can cause the level shifters to “send a signal to the
`
`I/O devices for transmission” resulting in the I/O devices “transmit[ting] the
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`erroneous signal into the external environment.” Id. at 1:34–40.
`
`One prior art solution identified in the ’674 patent is the use of
`
`“power-up/down detectors to generate a power-on/off-control (POC) signal
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`3
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`Patent 8,063,674 B2
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`internally [which] instructs the I/O devices when the core devices are shut
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`down.” Id. at 1:55–58. Figure 1 of the ’674 patent is reproduced below.
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`Figure 1 “is a circuit diagram illustrating a conventional POC system for
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`multiple supply voltage devices” which is identified as being prior art. Id. at
`
`
`
`4:18–19, Fig. 1.
`
`The ’674 patent identifies a number of issues associated with the
`
`Figure 1 design. For example, when I/O power supply 104 is on and core
`
`power supply 103 is off, powering on the core power supply results in “a
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`period in which all three transistors within power up/down detector 100 are
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`on,” resulting a virtual short “to ground causing a significant amount of
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`current to flow from I/O power supply 104 to ground.” Id. at 2:21–29.
`
`“This ‘glitch’ current consumes unnecessary power.” Id. at 2:29–30.
`
`Although the glitch current can be reduced by reducing the size of transistors
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`M1-M3, such a reduction limits “the actual amount of current that can pass
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`through the transistors” and reduces their switching speeds, which
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`“translates into less sensitivity in detecting power-up/down of core supply
`
`4
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`Patent 8,063,674 B2
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`voltage 103 or longer processing time for power-up/down events.” Id. at
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`2:31–39; see also id. at 2:63–3:11.
`
`According to the ’674 patent, these problems can be solved by using
`
`“one or more feedback circuits coupled to the up/down detector” that “are
`
`configured to provide feedback signals to adjust a current capacity of said
`
`up/down detector.” Id. at 3:31–34. An example of such a feedback circuit is
`
`shown in Figure 4, reproduced below:
`
`Figure 4 “is a circuit diagram illustrating another POC network configured
`
`according to the teachings of the present disclosure.” Id. at 4:28–30. The
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`’674 patent describes the operation of the feedback circuit in Figure 4 as
`
`
`
`follows:
`
`The feedback network 310 comprises a transistor M8
`connected in parallel to the transistor M4. The transistor M8 is
`also configured as a p-type transistor, such that when the
`feedback signal from the inverting amplifier 400 is high, the
`transistor M8 is switched off, and when the feedback signal is
`low, the transistor M8 is switched on. Thus, when the Vcore 301
`is off, producing a high detection signal, the inverting amplifier
`400 inverts that signal to a logic low which causes the transistor
`M8 to switch on. As the Vcore 301 is powered-on, the detection
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`5
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`signal changes to a logic low, which changes the feedback
`signal from the inverting amplifier 400 to a logic high, which,
`in turn, turns the transistor M8 off. While the transistor M8 is
`off, the power up/down detector 306 has a decreased current
`capacity, i.e., smaller current will flow through the transistor
`M8 because of the amplified low signal. The voltage level
`caused by the Vcore 301 on the gate terminals of M4 and M5
`could in some glitch or stray signal situations, cause leakage
`through M4 and M5. Because the feedback signal for the
`transistor M8 is received from the inverting amplifier 400,
`when the Vcore 301 powers-down, the feedback signal will
`switch quickly from a logic high to a logic low, which will then
`switch the transistor M8 on. Thus, in the circuit configuration
`depicted in FIG. 4, the power up/down detector 40 will detect
`the Vcore 301 powering down more quickly than the existing
`POC networks.
`
`Id. at 6:4–28
`
`D.
`
`The Challenged Claims
`
`Petitioner challenges claims 8, 9, 12, 13, and 16–22 of the ’674 patent.
`
`Pet. 1. Claims 8 and 17 are independent. Claim 8 is illustrative of the
`
`subject matter of the challenged claims and reads as follows:
`
`A method for reducing power consumption in a
`8.
`power on/off control (POC) network of a multiple supply
`voltage device, said method comprising:
`
`detecting a power-on of a second supply voltage while a
`first supply voltage is already on;
`
`decreasing a current capacity of a power on/off detector
`of said POC network in response to said power-on detection;
`
`detecting a power-down of said second supply voltage
`while said first supply voltage is on;
`
`increasing said current capacity of said power on/off
`detector in response to said power-down detection;
`
`receiving a logic-high signal at a control gate of at least
`one first transistor, at least one second transistor and at least
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`6
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`one third transistor coupled in series between the at least one
`first transistor and the at least one second transistor, the at least
`one first transistor being configured to switch off in response to
`said logic-high signal, and the at least one second transistor
`being configured to switch on in response to said logic-high
`signal; and
`
`transmitting a detection signal to a signal processor from
`the at least one second transistor based on said received logic-
`high signal.
`
`Ex. 1001, 9:48–10:3.
`
`E.
`
`Asserted Grounds of Unpatentability
`
`Petitioner asserts the following grounds of unpatentability:
`
`Reference(s)
`
`Basis1
`
`Challenged Claim(s)
`
`Steinacker2 in view of Doyle3 and
`Park4
`AAPA5 in view of Majcherczak6
`
`§ 103(a) 8, 9, 12, 13, and 16–22
`
`§ 103(a) 8, 9, 12, 13, and 17–21
`
`
`1 The Leahy-Smith America Invents Act (“AIA”) included revisions to 35
`U.S.C. § 103 that became effective on March 16, 2013. Because the ’674
`patent issued from an application filed before March 16, 2013, we apply the
`pre-AIA versions of the statutory bases for unpatentability.
`
`2 U.S. Patent No. 7,279,943 B2 (issued Oct. 9, 2007) (Ex. 1005).
`
`3 U.S. Patent No. 4,717,836 (issued Jan. 5, 1988) (Ex. 1006).
`
`4 Jun Cheol Park and Vincent J. Mooney III, Sleepy Stack Leakage
`Reduction, IEEE Transactions on Very Large Scale Integration (VLSI)
`Systems, Vol. 14, No. 11, 1250–63 (Nov. 2006) (Ex. 1007).
`
`5 Petitioners identify Figure 1 and the text at column 1, line 22 through
`column 2, line 39 of the ’674 patent as Applicant Admitted Prior Art. See
`Pet. 37, 43, 46
`
`6 U.S. Published Patent Application No. 2002/0163364 A1 (published Nov.
`7, 2002) (Ex. 1008).
`
`7
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`Patent 8,063,674 B2
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`Reference(s)
`
`Basis1
`
`Challenged Claim(s)
`
`AAPA in view of Majcherczak
`and Matthews7
`
`§ 103(a) 16 and 22
`
`Pet. 1. In its analysis, Petitioner relies on the declaration testimony of
`
`Robert W. Horst, Ph.D. (Ex. 1003) and Jacob Robert Munford (Ex. 1016).
`
`II. ANALYSIS
`
`A.
`
`Claim Construction
`
`In this inter partes review, we construe claim terms in an unexpired
`
`patent according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b)
`
`(2016).8 “Under a broadest reasonable interpretation, words of the claim
`
`must be given their plain meaning, unless such meaning is inconsistent with
`
`the specification and prosecution history.” Trivascular, Inc. v. Samuels, 812
`
`F.3d 1056, 1062 (Fed. Cir. 2016). In addition, the Board may not “construe
`
`claims during [an inter partes review] so broadly that its constructions are
`
`unreasonable under general claim construction principles.” Microsoft Corp.
`
`v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015) (emphasis
`
`omitted). An inventor may provide a meaning for a term that is different
`
`from its ordinary meaning by defining the term in the specification with
`
`
`7 U.S. Patent No. 6,646,844 B1 (issued Nov. 11, 2003) (Ex. 1009).
`
`8 Per recent regulation, the Board will apply the Phillips claim construction
`standard to petitions filed on or after November 13, 2018. See Changes to
`the Claim Construction Standard for Interpreting Claims in Trial
`Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51340
`(Oct. 11, 2018) (to be codified at 37 C.F.R. pt. 42). Because Petitioner filed
`the Petition before November 13, 2018, we apply the BRI standard.
`
`8
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`Patent 8,063,674 B2
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`reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d
`
`1475, 1480 (Fed. Cir. 1994).
`
`Petitioner proposes a claim construction for “signal processor,”
`
`“means for detecting a power-on of a second supply voltage while a first
`
`supply voltage is already on,” “means, responsive to said power-on
`
`detection, for decreasing a current capacity of a power on/off detector of said
`
`POC network,” “means for detecting a power-down of said second supply
`
`voltage while said first supply voltage is on,” “means, responsive to said
`
`power-down detection, for increasing said current capacity of said power
`
`on/off detector,” “means for providing a feedback signal associated with at
`
`least one of: said detected power-on or said detected power-down, wherein
`
`said feedback signal is used in said means for decreasing and said means for
`
`increasing,” “means for receiving a logic-high signal at a control gate of at
`
`least one first transistor, at least one second transistor and at least one third
`
`transistor coupled in series between the at least one first transistor and the at
`
`least one second transistor, the at least one first transistor being configured
`
`to switch off in response to said logic-high signal, and the at least one
`
`second transistor being configured to switch on in response to said logic-
`
`high signal,” “means for transmitting a detection signal to a signal processor
`
`from the at least one second transistor based on said received logic-high
`
`signal,” “means, responsive to said feedback signal, for switching off one or
`
`more transistors of a plurality of transistors, wherein said plurality of
`
`transistors define said current capacity of said power on/off detector,” and
`
`“means, responsive to said feedback signal, for switching on one or more
`
`transistors of a plurality of transistors, wherein said plurality of transistors
`
`define said current capacity of said power on/off detector.” Pet. 5–9.
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`9
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`Having considered the evidence presented, we conclude that no
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`express claim construction of any term is necessary for our determination of
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`whether to institute review of the challenged claims. See Vivid Techs., Inc.
`
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those
`
`terms need be construed that are in controversy, and only to the extent
`
`necessary to resolve the controversy.”).
`
`B.
`
`Legal Principles
`
`Section 103(a) forbids issuance of a patent when “the differences
`
`between the subject matter sought to be patented and the prior art are such
`
`that the subject matter as a whole would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations, including (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art; (3)
`
`the level of ordinary skill in the art; and (4) when available, evidence such as
`
`commercial success, long felt but unsolved needs, and failure of others.
`
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966); see KSR, 550 U.S. at
`
`407 (“While the sequence of these questions might be reordered in any
`
`particular case, the [Graham] factors continue to define the inquiry that
`
`controls.”). The Court in Graham explained that these factual inquiries
`
`promote “uniformity and definiteness,” for “[w]hat is obvious is not a
`
`question upon which there is likely to be uniformity of thought in every
`
`given factual context.” 383 U.S. at 18.
`
`The Supreme Court made clear that we apply “an expansive and
`
`flexible approach” to the question of obviousness. KSR, 550 U.S. at 415.
`
`10
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`Whether a patent claiming the combination of prior art elements would have
`
`been obvious is determined by whether the improvement is more than the
`
`predictable use of prior art elements according to their established functions.
`
`Id. at 417. To reach this conclusion, however, it is not enough to show
`
`merely that the prior art includes separate references covering each separate
`
`limitation in a challenged claim. Unigene Labs., Inc. v. Apotex, Inc., 655
`
`F.3d 1352, 1360 (Fed. Cir. 2011). Rather, obviousness additionally requires
`
`that a person of ordinary skill at the time of the invention “would have
`
`selected and combined those prior art elements in the normal course of
`
`research and development to yield the claimed invention.” Id.
`
`Moreover, in determining the differences between the prior art and the
`
`claims, the question under 35 U.S.C. § 103 is not whether the differences
`
`themselves would have been obvious, but whether the claimed invention as a
`
`whole would have been obvious. Litton Indus. Prods., Inc. v. Solid State
`
`Sys. Corp., 755 F.2d 158, 164 (Fed. Cir. 1985) (“It is elementary that the
`
`claimed invention must be considered as a whole in deciding the question of
`
`obviousness.” (citation omitted)); see also Stratoflex, Inc. v. Aeroquip Corp.,
`
`713 F.2d 1530, 1537 (Fed. Cir. 1983) (“[T]he question under 35 U.S.C.
`
`§ 103 is not whether the differences themselves would have been obvious.
`
`Consideration of differences, like each of the findings set forth in Graham,
`
`is but an aid in reaching the ultimate determination of whether the claimed
`
`invention as a whole would have been obvious.” (citation omitted)).
`
`“A reference must be considered for everything it teaches by way of
`
`technology and is not limited to the particular invention it is describing and
`
`attempting to protect.” EWP Corp. v. Reliance Universal Inc., 755 F.2d 898,
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`907 (Fed. Cir. 1985). Additionally, “the question under 35 USC § 103 is not
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`merely what the references expressly teach but what they would have
`
`suggested to one of ordinary skill in the art at the time the invention was
`
`made.” Merck & Co. v. Biocraft Laboratories, Inc., 874 F.2d 804, 807–08
`
`(Fed. Cir. 1989) (quoting In re Lamberti, 545 F.2d 747, 750 (CCPA 1976)).
`
`“Every patent application and reference relies to some extent upon
`
`knowledge of persons skilled in the art to complement that [which is]
`
`disclosed . . . .” In re Bode, 550 F.2d 656, 660 (CCPA 1977) (quoting In re
`
`Wiggins, 488 F.2d 538, 543 (CCPA 1973)). Those persons “must be
`
`presumed to know something” about the art “apart from what the references
`
`disclose.” In re Jacoby, 309 F.2d 513, 516 (CCPA 1962).
`
`As a factfinder, we also must be aware “of the distortion caused by
`
`hindsight bias and must be cautious of arguments reliant upon ex post
`
`reasoning.” KSR, 550 U.S. at 421. This does not deny us, however,
`
`“recourse to common sense” or to that which the prior art teaches. Id.
`
`Against this general background, we consider the references, other
`
`evidence, and arguments on which the parties rely.
`
`C.
`
`Level of Ordinary Skill in the Art
`
`The level of ordinary skill in the art is “a prism or lens” through which
`
`we view the prior art and the claimed invention. Okajima v. Bourdeau, 261
`
`F.3d 1350, 1355 (Fed. Cir. 2001).
`
`Factors pertinent to a determination of the “level of ordinary skill in
`
`the art include (1) educational level of the inventor; (2) type of problems
`
`encountered in the art; (3) prior art solutions to those problems; (4) rapidity
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`with which innovations are made; (5) sophistication of the technology; and
`
`(6) educational level of workers active in the field.” Envtl. Designs, Ltd. v.
`
`Union Oil Co., 713 F.2d 693, 696–697 (Fed. Cir. 1983) (citing Orthopedic
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`12
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`Equip. Co. v. All Orthopedic Appliances, Inc., 707 F.2d 1376, 1381–82 (Fed.
`
`Cir. 1983)). Not all such factors may be present in every case, and one or
`
`more of these or other factors may predominate in a particular case. Id.
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`Moreover, “[t]hese factors are not exhaustive but are merely a guide to
`
`determining the level of ordinary skill in the art.” Daiichi Sankyo Co. Ltd,
`
`Inc. v. Apotex, Inc., 501 F.3d 1254, 1256 (Fed. Cir. 2007). In determining a
`
`level of ordinary skill, we also may look to the prior art, which may reflect
`
`an appropriate skill level. Okajima, 261 F.3d at 1355. Additionally, the
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`Supreme Court informs us that “[a] person of ordinary skill is also a person
`
`of ordinary creativity, not an automaton.” KSR, 550 U.S. at 421.
`
`Dr. Horst testifies that a person having ordinary skill in the art would
`
`have had “at least an undergraduate degree in electrical engineering, or a
`
`related field, and three years of experience in circuit and system design.”
`
`Ex. 1003 ¶ 33. Additionally, Dr. Horst testifies that “a person of ordinary
`
`skill with less than the amount of experience noted above could have had a
`
`correspondingly greater amount of educational training such a graduate
`
`degree in a related field.” Id.
`
`Patent Owner does not dispute that definition in its Preliminary
`
`Response. Additionally, Patent Owner does not rely on any testimonial
`
`evidence on the level of ordinary skill in the art.
`
`Accordingly, we adopt Dr. Horst’s definition of the level of ordinary
`
`skill in the art, with the exception of the language “at least,” for purposes of
`
`this Decision.9
`
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`9 If Patent Owner proposes a different level of ordinary skill in the art in the
`Patent Owner’s Response, the parties are encouraged to address whether
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`D. Obviousness over AAPA in View of Majcherczak
`
`Petitioner argues the subject matter of claims 8, 9, 12, 13, and 17–21
`
`would have been obvious to a person of ordinary skill in the art at the time
`
`of the invention in light of the teachings of AAPA in view of Majcherczak
`
`(Ex. 1008). Based on the current record, we are persuaded that Petitioner
`
`has established a reasonable likelihood of prevailing on its asserted
`
`obviousness ground with respect to claims 8, 9, 12, 13, and 17–21.
`
`1.
`
`Summary of AAPA
`
`The ’674 patent describes a prior art “power-up/down detector[] to
`
`generate a power-on/off-control (POC) signal internally.” Ex. 1001, 1:55–
`
`57, Fig. 1. The prior art design is shown in Figure 1, reproduced below.
`
`Id. at Fig. 1. “FIG. 1 is a circuit diagram illustrating a conventional POC
`
`system for multiple supply voltage devices” and is identified as prior art. Id.
`
`at 4:18–19, Fig. 1. According to the ’674 patent, the POC “is made up of
`
`three functional blocks: power-up/down detector 100, signal amplifier 101,
`
`
`
`
`there are any material differences between the two proposals and what
`impact, if any, the different level has on the obviousness analysis.
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`and output stage 102. Power-up/down detector 100 has PMOS transistor M1
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`and NMOS transistors M2-M3.” Id. at 1:60–63.
`
`2.
`
`Summary of Majcherczak
`
`Majcherczak is titled “Power Supply Detection Device” and relates
`
`“to a power supply detection device for an integrated circuit using at least
`
`two power supply voltages.” Ex. 1008, [54], ¶ 1. Majcherczak describes a
`
`voltage detection device that detects when the core voltage is powered down
`
`or there is an excessively slow build-up of the voltage. Id. at [57], ¶¶ 8–11.
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`Figure 2 of Majcherczak is shown below.
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`Figure 2 shows a detection device “compris[ing] an output stage E3
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`following the input stage E1, to obtain the desired output levels for the
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`inverse detection signal CORE-OFFn.” Id. ¶¶ 35–37.
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`3.
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`Claim 8
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`a.
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`Petitioner’s Arguments
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`Petitioner argues that the combination of AAPA and Majcherczak
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`teaches all of the limitations recited in claim 8. See Pet. 45–70.
`
`Specifically, Petitioner argues a person of ordinary skill in the art would
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`have combined the feedback circuit of Majcherczak with the POC described
`
`in AAPA as shown in the annotated figure reproduced below.
`
`
`
`Id. 51–52. The figure reproduced above shows Majcherczak’s Figure 2
`
`annotated by Petitioner (right) and a version of Figure 1 of the ’674 patent
`
`(AAPA) modified by Petitioner to integrate the feedback transistor M6 from
`
`Majcherczak’s Figure 2 (left). Id. at 52. Petitioner also provides a
`
`differently annotated version of its proposed combination (id. at 56) as
`
`reproduced below.
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`The figure above shows what Petitioner contends is the combination of the
`
`feedback network of Majcherczak with the POC of AAPA. Id. Petitioner’s
`
`annotations show what Petitioner argues is the power up/down detector in
`
`green, the signal processor in yellow, and the feedback network from
`
`Majcherczak in blue. Id.
`
`More specifically, Petitioner argues that the combination of AAPA
`
`and Majcherczak teaches “[a] method for reducing power consumption in a
`
`power on/off control (POC) network of a multiple supply voltage device” as
`
`recited in claim 8. Id. at 54. Specifically, Petitioner argues AAPA teaches a
`
`standard POC system for multiple voltages and that the addition of
`
`Majcherczak’s feedback transistor M6 modifies the POC so that it “is
`
`configured to adjust the current capacity of the power up/down detector.”
`
`Id. (citing Ex. 1001:55–58; Ex. 1003 ¶¶ 142–143).
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`Petitioner further argues AAPA teaches “detecting a power-on of a
`
`second supply voltage while a first supply voltage is already on” as recited
`
`in claim 8. Id. at 54–55. Specifically, Petitioner argues AAPA teaches a
`
`power up/down detector 100 in Figure 1, including transistors M1, M2, and
`
`M3, which performs the step of detecting a power-on of a second supply
`
`voltage while a first supply voltage is already on. Id. at 6 (citing Ex. 1001,
`
`2:8–13, 5:24–27; Ex. 1003 ¶¶ 70–71), 55.
`
`Petitioner further argues the combination of AAPA and Majcherczak
`
`teaches “decreasing a current capacity of a power on/off detector of said
`
`POC network in response to said power-on detection” as recited in claim 8.
`
`Id. at 55–57. Specifically, Petitioner argues transistor M8 in Figure 4 of the
`
`’674 patent performs “the function of decreasing a current capacity of a
`
`power on/ off detector of said POC network in response to said power-on
`
`detection.” Id. at 56. Petitioner further directs us to a comparison of
`
`transistor M6 in the combination of AAPA and Majcherczak with transistor
`
`M8 in Figure 4 of the ’674 patent, and argues both transistors perform the
`
`same function. Id. at 56–57.
`
`Petitioner also argues AAPA teaches “detecting a power-down of said
`
`second supply voltage while said first supply voltage is on” as recited in
`
`claim 8. Id. at 57–58. Specifically, Petitioner argues power up/down
`
`detector 100 in AAPA performs that step. Id. at 6–7 (citing Ex. 1001, 1:65–
`
`2:7, 5:6–10; Ex. 1003 ¶¶ 74–75), 57–58.
`
`Petitioner also argues the combination of AAPA and Majcherczak
`
`teaches “increasing said current capacity of said power on/off detector in
`
`response to said power-down detection” as recited in claim 8. See id. at 58–
`
`60. Specifically, Petitioner argues transistor M8 in Figure 4 of the ’674
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`patent performs “the function of increasing a current capacity of a power on/
`
`off detector of said POC network in response to said power-on detection.”
`
`Id. at 58. Petitioner further directs us to a comparison of transistor M6 in the
`
`combination of AAPA and Majcherczak with transistor M8 in Figure 4 of
`
`the ’674 patent, and argues both transistors perform the same function. Id. at
`
`59–60.
`
`Petitioner further argues that the combination of AAPA and
`
`Majcherczak teaches “receiving a logic-high signal at a control gate of at
`
`least one first transistor, at least one second transistor and at least one third
`
`transistor coupled in series between the at least one first transistor and the at
`
`least one second transistor, the at least one first transistor being configured
`
`to switch off in response to said logic-high signal, and the at least one
`
`second transistor being configured to switch on in response to said logic-
`
`high signal” as recited in claim 8. See Pet. at 60–61. Specifically, Petitioner
`
`argues:
`
`transistor M1 . . . is a first transistor configured to switch off in
`response to said logic-high signal, the transistor M3 . . . is a
`second transistor configured to switch on in response to said
`logic-high signal, and transistor M2 . . . is a third transistor
`coupled in series between the first transistor (M1) and the
`second transistor (M3).
`
`Id. at 60. Petitioner further argues that AAPA teaches “that the core power
`
`supply 103, Vcore, can be turned on to a logic high voltage, which causes to
`
`M1 become very weak and M2 and M3 both to switch strongly on, pulling
`
`the input node to amplifier 105 to VSS (logic low).” Id. at 61.
`
`Petitioner also argues AAPA teaches “transmitting a detection signal
`
`to a signal processor from the at least one second transistor based on said
`
`received logic-high signal” as recited in claim 8. See id. at 62–63.
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`Specifically, Petitioner relies on the “connection between transistor M3 via
`
`transistor M2 to the input of signal processor 101” to teach this limitation.
`
`Id. at 62–63 (citing Ex. 1001, 1:65–2:13, Fig. 1; Ex. 1003 ¶ 147); see also id.
`
`at 8–9 (citing Ex. 1001, 1:65–22, 2:8–11, 5:58–67, 6:47–60, 7:17–20; Ex.
`
`1003 ¶ 80).
`
`Finally, Petitioner argues that a person of ordinary skill in the art
`
`“would have been motivated to integrate the feedback transistor M6 from
`
`Majcherczak’s voltage detector into the POC system 10 of AAPA in order to
`
`‘enable[] the proper stabilizing of the detection device.’” Id. at 53 (quoting
`
`Ex. 1008 ¶ 37) (citing Ex. 1003 ¶ 150). According to Petitioner, the
`
`“combination would result in AAPA’s POC system 10 observing the
`
`‘hysteresis detection’ described by Majcherczak, facilitating controlled
`
`operation of the I/O devices instructed by the POC signal on
`
`communications from the core devices when the core supply voltage is
`
`stably on.” Id. (citing Ex. 1003 ¶ 150). Moreover, according to Petitioner, a
`
`person of ordinary skill in the art would have a reasonable expectation of
`
`success:
`
`A POSITA would have perceived a reasonable
`expectation of success in making this modification to the POC
`system 10 of AAPA, because the POC system 10 and
`Majcherczak’s voltage detector share many functionally
`commensurate elements, operate in a corresponding manner,
`and are used in the similar types of multiple supply voltage
`devices. [Ex. 1003] ¶ 151. Indeed, the integration of the
`feedback transistor M6 from Majcherczak’s voltage detector
`would have simply been the use of a known technique (a
`feedback transistor to improve hysteresis) to improve similar
`devices (detection circuits in multiple supply voltage devices)
`in the same way. Id.
`
`Id.
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`b.
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`Patent Owner’s Arguments
`
`Patent Owner does not dispute Petitioner’s contention that claim 1
`
`would have been obvious to a person of ordinary skill in the art in over the
`
`combination of AAPA and Majcherczak. See Prelim. Resp. 27–35. Instead,
`
`Patent Owner argues (1) that we should exercise our discretion and deny
`
`institution on the basis of 35 U.S.C. § 325(d) and (2) that we cannot consider
`
`applicant admitted prior art during an inter partes review.
`
`Specifically, Patent Owner argues that the Examiner was required to
`
`review and consider the specification, including AAPA. Id. at 28. Patent
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`Owner further argues the Examiner not only considered Majcherczak, but
`
`the Examiner also considered “an [International Search Report (ISR)] and
`
`Written Opinion of the International Searching Authority that provided a
`
`detailed discussion of how Majcherczak allegedly reads on the claims.” Id.
`
`According to Patent Owner, “because the Office considered both the alleged
`
`AAPA and Majcherczak and found the claims to be patentable over them,”
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`we should exercise our discretion and deny institution. Id. at 29–34.
`
`Additionally, Patent Owner argues because “[n]either the alleged
`
`AAPA nor
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