7/18/2019
`
`http://www.ece.umd.edu/courses/enee359a.S2007/
`
`10 captures
`4 Jul 2008 - 8 Nov 2018
`
`ENEE 359A: Digital VLSI Design by B. Jacob
`JUN JUL MAR
`04
`2007 2008 2016
`
`Go
`
`(cid:66) ⍰ ❎
`
`
`f (cid:64)
`
`▾ About this capture
`
`ENEE 359A: Digital VLSI Circuits by B. Jacob
`Spring 2007
`
`Course Information:
`
`Lecture:
`Mailing List:
`Required Text:
`Recommended
`Texts:
`
`Tue Thu 2:00 - 3:15, EGR-3114
`enee359a-0101-spring07@coursemail.umd.edu
`Digital Integrated Circuits: A Design Perspective, 2nd Ed., by Rabaey, Chandrakasan,
`and Nikolic
`Dally & Poulton: Digital Systems Engineering
`Johnson & Graham: High-Speed Digital Design
`Uyemura: Introduction to VLSI Circuits and Systems
`Baker, Li, & Boyce: CMOS: Circuit Design, Layout, and Simulation
`
`Instructor Information:
`
`Bruce L. Jacob, Associate Professor, Electrical & Computer Engineering
`Professor:
`1325 A.V. Williams Building
`Office:
`(301) 405-0432
`Phone:
`Email:
`blj@ece.umd.edu
`Office Hours: Open door policy (for now ...)
`
`Elliott Cooper-Balis
`TA:
`ecc17@umd.edu
`Email:
`Recitations: Tue 3:30 - 4:30pm, ???
`
`Course Handouts and General Information:
`
`Syllabus.pdf
`A great Verilog tutorial on-line, and PDF of that same tutorial.
`verilog-handbook.pdf. This is a concise overview of the Verilog programming language.
`realize-verilog.pdf. Gives a functional view of Verilog; i.e. if you want to build a processor model, this
`shows how. However, it confuses blocking/non-blocking assignments (calls "=" non-blocking and "<="
`blocking). Otherwise, it is a decent overview.
`scaling.gif. A very interesting picture illustrating the degree to which VLSI designs have reduced in size
`since the Intel 4004.
`2007-midterm-solutions.pdf. Midterm exam, grade distribution, solutions.
`
`https://web.archive.org/web/20080704133703/http://www.ece.umd.edu/courses/enee359a.S2007/
`
`1/2
`
`1
`
`Exhibit 1025
`Apple v. Qualcomm
`IPR2018-01316
`
`

`

`ENEE 359A: Digital VLSI Design by B. Jacob
`JUN JUL MAR
`
`Go
`
`04
`Topics
`2007 2008 2016
`CCCCoCoCoururursesese ooovevevervrvrviiiieieiewww iiiininin aaa nnn tttututut hhhshshsh lllelelelllllll
`Course overview in a nutshell
`
`Readings
`ChChChChChCh 111111
`Ch. 1
`
`(cid:66) ⍰ ❎
`
`
`f (cid:64)
`
`▾ About this capture
`
`7/18/2019
`Lectures:
`http://www.ece.umd.edu/courses/enee359a.S2007/
`10 captures
`Week
`4 Jul 2008 - 8 Nov 2018
`Weeks
`WWWeWeWeWe kkekekekekssss
`1/2
`Weeks
`2/3
`Week 4
`Week 5
`
`Slides
`
`enee359a-eneneneneneneeeeeeeeeeee3535353535353535353599999a9a9a9a9a9a-
`overview.pdf
`enee359a-devices.pdf Ch. 3.1-3.3.2,
`5.1-5.3
`enee359a-CMOS.pdf Ch. 6-6.2
`enee359a-
`manufacturing.pdf
`Week 6
`enee359a-sizing.pdf Ch. 5.4-5.7
`Week 7
`enee359a-wires.pdf Ch. 4
`Week 8 Review and
`Midterm
`Week 9
`SPRING BREAK
`Weeks
`enee359a-
`10/11
`sequential.pdf
`Week 12 enee359a-
`parasitics.pdf
`enee359a-timing.pdf Ch. 10
`
`Intro to (Verilog) design, P/N junctions, MOS
`transistors, CMOS inverter
`Static CMOS Design
`Cadence tools & manufacturing processes
`
`Transistor Sizing & Logical Effort
`Interconnects (i.e., wires)
`
`Sequential Circuits: Latches, Registers, Pipelines
`
`Capacitive, Resistive, and Inductive Parasitics
`
`System Timing: Synchronous, Asynchronous, etc.
`
`Low-Power SRAM Circuits
`
`DRAM Systems & Circuits ... pictures of cells
`
`Ch. 7
`
`Ch. 9
`
`not really in
`book
`not really in
`book
`
`Weeks
`13/14
`Weeks
`enee359a-SRAM-
`15
`i.pdf
`Week 16 enee359a-DRAM-
`i.pdf
`enee359a-DRAM-
`ii.pdf
`
`Assignments:
`
`Write-up Homework Solution/Project Distribution
`Due
`Out
`ID
`Project 1 01-Feb-2007 13-Feb-2007 p1.pdf
`Project 1 Distribution
`HW-1
`15-Feb-2007 20-Feb-2007 hw1.pdf
`Project 2 20-Feb-2007 06-Mar-2007 p2.pdf
`HW-2
`20-Feb-2007 27-Feb-2007 hw2.pdf
`Project 3 01-Mar-2007 29-Mar-2007 p3.pdf
`HW-3
`09-Mar-2007 13-Mar-2007 hw3.pdf
`Project 4 12-Apr-2007 24-Apr-2007 p4.pdf
`HW-4
`01-May-2007 10-May-2007 hw4.pdf DFF-sim.pdf
`
`Project 3 Distribution
`
`Project 2 Distribution
`
`https://web.archive.org/web/20080704133703/http://www.ece.umd.edu/courses/enee359a.S2007/
`
`2/2
`
`2
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 1
`
`ENEE 359a
`Digital VLSI Design
`
`Transistor Sizing
`& Logical Effort
`Prof. Bruce Jacob
`blj@ece.umd.edu
`
`Credit where credit is due:
`Slides contain original artwork (© Jacob 2004) as well as material taken liberally
`from Irwin & Vijay’s CSE477 slides (PSU), Schmit & Strojwas’s 18-322 slides
`(CMU), Dally’s EE273 slides (Stanford), Wolf’s slides for Modern VLSI Design,
`and/or Rabaey’s slides (UCB).
`
`UNIVERSITY OF MARYLAND
`
`3
`
`

`

`Overview
`• Sizing of transistors to balance
`performance of single inverter
`• More on RC time constant, first-order
`approximation of time delays
`• Sizing in complex gates, examples
`• Sizing of inverter chains for driving high
`capacitance loads (off-chip wires)
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 2
`
`UNIVERSITY OF MARYLAND
`
`4
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 3
`
`Resistance
`WOULD LIKE BALANCED NETWORKS:
`VDD
`
`“Dual” networks
`
`Pull-up
`Network
`(pFET network)
`
`INPUT/S
`
`OUTPUT
`
`Pull-down
`Network
`(nFET network)
`
`UNIVERSITY OF MARYLAND
`
`5
`
`

`

`Resistance
`Resistance of MOSFET:
`1
`---------------------------------------------- L
`⎛
`⎞
`
`----⎝ ⎠
`(
`)
`μnCox VGS VTn
`–
`Increasing W decreases the resistance;
`allows more current to flow
`
`Rn
`
`=
`
`•
`
`W-
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 4
`
` [F/cm2]
`
`εox tox⁄
`=
` [F]
`CoxWL
`⎛
`⎞
`μnCox
`
`-----⎝ ⎠
`
`WL
`
`⎛
`⎞
`
`-----⎝ ⎠
`
`=
`
`k'n
`
`WL
`
`Oxide capacitance
`Cox
`Gate capacitance
`=
`CG
`βn
`
`Transconductance
`
`=
`
`(units [A/V2])
`
`UNIVERSITY OF MARYLAND
`
`6
`
`

`

`WL
`
`⎛
`⎞
`
`-----⎝ ⎠
`
`βn
`
`=
`
`μnCox
`
`βp
`
`=
`
`μpCox
`
`n
`⎛
`⎞
`
`-----⎝ ⎠
`
`p
`
`WL
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 5
`
`Resistance
`nFET vs. pFET
`
`Rn
`
`=
`
`Rp
`
`=
`
`1
`-------------------------------------
`(
`)
`βn VDD VTn
`–
`1
`----------------------------------------
`(
`)
`βp VDD VTp
`–
`
`μn
`-----
`μp
`(μ is the carrier mobility through device)
`
`Typically
`(2 .. 3)
`
`r=
`
`UNIVERSITY OF MARYLAND
`
`7
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 6
`
`UNIVERSITY OF MARYLAND
`
`Transistor Sizing
`SIMPLE CASE: Inverter
`
`VDD
`
`Rp
`
`CL
`
`VDD
`
`VOUT
`CL
`
`Rn
`
`VOUT
`CL
`
`Charging: Vout rising
`
`Discharging: Vout falling
`
`If (W/L)p = r(W/L)n then ßn = ßp
`(and Rn = Rp)
`… symmetric inverter
`Make pFET bigger (wider) by factor of r
`
`8
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 7
`
`UNIVERSITY OF MARYLAND
`
`Transistor Sizing
`SIMPLE CASE: Inverter
`
`VDD
`
`Rp
`
`CL
`
`VDD
`
`VOUT
`CL
`
`Rn
`
`VOUT
`CL
`
`Charging: Vout rising
`
`Discharging: Vout falling
`
`tpLH = ln(2) Rp CL = 0.69 Rp CL
`tpHL = ln(2) Rn CL = 0.69 Rn CL
`tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2
`(note: the ln(2)RC term comes from first-order analysis of simple
`RC circuit’s respose to step input ... time for output to reach 50% value
`… more detail on this in a moment, after we discuss capacitance …)
`
`9
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 8
`
`UNIVERSITY OF MARYLAND
`
`Wire Resistance
`
`l
`
`w
`
`l
`
`r
`h
`• R = ρρρρl/A = ρρρρl/(wh) for rectangular wires
`(on-chip wires & vias, PCB traces)
`• R = ρρρρl/A = ρρρρl/(ππππr2) for circular wires
`(off-chip, off-PCB)
`Material
`Silver (Ag)
`Copper (Cu)
`Gold (Au)
`Aluminum (Al)
`Tungsten (W)
`
`Resistivity ρρρρ (ΩΩΩΩ-m)
`1.6 x 10-8
`1.7 x 10-8
`2.2 x 10-8
`2.7 x 10-8
`5.5 x 10-8
`
`10
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 9
`
`UNIVERSITY OF MARYLAND
`
`Sheet Resistance
`
`R = ρρρρl/(wh) = l/w•ρρρρ/h for rectangular wires
`Sheet resistance Rsq = ρρρρ/h (h=thickness)
`Sheet resistance Rsq (ΩΩΩΩ/sq)
`Material
`n, p well diffusion
`1000 to 1500
`n+, p+ diffusion
`50 to 150
`polysilicon
`150 to 200
`polysilicon with silicide
`4 to 5
`Aluminum
`0.05 to 0.1
`
`11
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 10
`
`More on Resistance
`Sheet resistance Rsq
`
`12 squares
`
`6 squares
`
`UNIVERSITY OF MARYLAND
`
`= 1sq + 1sq + 0.56sq
`
`= 1sq + 1sq + 0.2sq
`
`12
`
`

`

`More on Resistance
`
`(it’s not just the channel that counts)
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 11
`
`UNIVERSITY OF MARYLAND
`
`13
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 12
`
`And Now … Capacitance (CL)
`Vout
`Vout2
`CL
`
`Vin
`
`Vin
`
`M2
`
`CDB2
`
`pdrain
`ndrain
`
`CGD12
`
`M1
`
`CDB1
`
`Vout
`Cw
`
`CG4
`
`CG3
`
`Vout2
`
`M4
`
`M3
`
`•
`•
`•
`
`intrinsic MOS transistor capacitances
`extrinsic MOS transistor (fanout) capacitances
`wiring (interconnect) capacitance
`
`UNIVERSITY OF MARYLAND
`
`14
`
`

`

`CW, a Large Example
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 13
`
`UNIVERSITY OF MARYLAND
`
`15
`
`

`

`CW, a Large Example
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 14
`
`UNIVERSITY OF MARYLAND
`
`16
`
`

`

`Two Chained Inverters
`
`PMOS
`1.125/0.25
`
`In
`
`Polysilicon
`
`NMOS
`0.375/0.25
`
`VDD
`
`1.2μm
`=2λλλλ
`
`Out
`
`Metal1
`
`0.125 spacing
`
`GND
`0.5 width
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 15
`
`UNIVERSITY OF MARYLAND
`
`17
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 16
`
`Gate-Drain Capacitance CGD
`
`VDD
`
`PMOS
`1.125/0.25
`
`In
`
`Polysilicon
`
`NMOS
`0.375/0.25
`
`1.2μm
`=2λλλλ
`
`Out
`
`Metal1
`
`poly
`0.125 spacing
`SiO2
`
`GND
`Overlaps
`0.5 width
`
`Scales with transistor width W
`
`UNIVERSITY OF MARYLAND
`
`18
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 17
`
`Diffusion Capacitance CDB
`
`PMOS
`1.125/0.25
`
`In
`
`Polysilicon
`
`NMOS
`0.375/0.25
`
`VDD
`
`1.2μm
`=2λλλλ
`
`Out
`
`Metal1
`
`Reverse-Biased
`P/N Junction
`
`p+
`
`GND
`n-doped substrate or well
`
`•
`
`Drain is reverse-biased diode, non-linear C dependent
`on drain voltage (approx. nonlinearity with linear eqn,
`using K terms for bottom plate and sidewalls)
`
`UNIVERSITY OF MARYLAND
`
`19
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 18
`
`Gate/Fan-out Capacitance CG
`
`PMOS
`1.125/0.25
`
`In
`
`Polysilicon
`
`poly
`SiO2
`NMOS
`0.375/0.25
`
`VDD
`
`1.2μm
`=2λλλλ
`
`Out
`
`Metal1
`
`0.125 spacing
`
`GND
`
`Overlaps + Parallel Plate
`0.5 width
`
`Scales with both W and L
`
`UNIVERSITY OF MARYLAND
`
`20
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 19
`
`Two Chained Inverters: CL
`
`C Term Expression
`
`CGD1
`CGD2
`CDB1
`CDB2
`CG3
`CG4
`CW
`CL
`
`Value (fF)
`H →→→→ L
`0.23
`2 Con Wn
`0.61
`2 Cop Wp
`KeqbpnADnCj + KeqswnPDnCjsw 0.66
`KeqbppADpCj + KeqswpPDpCjsw 1.50
`0.76
`2 Con Wn + Cox Wn Ln
`2 Cop Wp + Cox Wp Lp
`2.28
`From extraction
`0.12
`Sum
`6.1
`
`Value (fF)
`L →→→→ H
`0.23
`0.61
`0.90
`1.15
`0.76
`2.28
`0.12
`6.0
`
`•
`•
`
`Terms in red: under control of designer
`CL split between intrinsic and extrinsic/wire sources
`
`UNIVERSITY OF MARYLAND
`
`21
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 20
`
`MOSFET Switching
`
`Parallel switching (all switch at same time):
`VDD
`A
`
`B
`
`t PLH
`
`=
`
`0.7
`
`•
`
`Rp
`N-------
`Series switching (all switch at same time):
`
`•
`
`(
`
`•
`N C oxp
`
`+
`
`C load
`
`C
`
`)
`
`Cload
`
`Cload
`
`t PHL
`
`=
`
`0.35 RnC oxn N 2
`•
`•
`0.7 N R•
`•
`•
`n C load
`+
`
`A B
`
`C
`
`UNIVERSITY OF MARYLAND
`
`22
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 21
`
`RC Delay, Two Inverters
`3
`Vin
`2.5
`2
`
`tf
`
`tpHL
`
`tr
`
`tpLH
`
`0.5
`
`1
`
`1.5
`t (sec)
`
`2
`
`x 10-10
`2.5
`
`1.5
`1
`0.5
`0
`
`Vout(V)
`
`-0.5
`
`0
`
`VDD=2.5V, 0.25mm
`•
`• W/Ln = 1.5, W/Lp = 4.5
`Reqn= 13 kΩΩΩΩ (÷ 1.5)
`•
`Reqp= 31 kΩΩΩΩ (÷ 4.5)
`•
`
`tpHL = 0.69 RnC = 36 ps
`tpLH = 0.69 RpC = 29 ps
`From SPICE simulation:
`tpHL = 39.9 ps, tpLH = 31.7 ps
`
`UNIVERSITY OF MARYLAND
`
`23
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 22
`
`Transistor Sizing I
`
`W
`
`2W
`
`L
`
`Source
`
`Drain
`
`L
`
`The electrical characteristics of transistors
`determine the switching speed of a circuit
`•
`Need to select the aspect ratios (W/L)n and (W/L)p of
`every FET in the circuit
`Define Unit Transistor (R1, C1)
`•
`L/Wmin-> highest resistance (needs scaling)
`•
`R2= R1 ÷ 2 and C2= 2 • C1
`•
`Separate nFET and pFET unit transistors
`•
`Unit devices are not restricted to individual transistors
`
`UNIVERSITY OF MARYLAND
`
`24
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 23
`
`Sizing I: Complex Gates
`Critical transistors: those in series
`VDD
`
`B
`
`E
`
`Two devices
`in series: scale
`each by 2x
`
`OUT
`
`CA
`
`D
`
`2 nets in series:
`scale each by 2x
`
`•
`•
`•
`
`N FETs in series => scale each by factor of N
`Ignore FETs in parallel (assume worst case: only 1 on)
`Ultimate goal: total resistance of net = 1 square
`
`UNIVERSITY OF MARYLAND
`
`25
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 24
`
`Sizing I: Complex Gates
`Critical transistors: those in series
`VDD
`
`Two devices
`in series: scale
`each by 2x
`
`OUT
`
`B
`
`E
`
`2x1
`
`2x1
`
`2x1
`
`4x1
`
`4x1
`
`CA
`
`D
`
`2 nets in series:
`scale each by 2x
`
`•
`•
`•
`
`N FETs in series => scale each by factor of N
`Ignore FETs in parallel (assume worst case: only 1 on)
`Ultimate goal: total resistance of net = 1 square
`
`UNIVERSITY OF MARYLAND
`
`26
`
`

`

`Examples
`
`VDD
`
`B
`
`E
`
`OUT
`
`E
`
`C
`
`D
`
`CA
`
`D
`
`A B
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 25
`
`UNIVERSITY OF MARYLAND
`
`27
`
`

`

`VDD
`
`B
`
`E
`
`6 6
`
`OUT
`
`E
`
`2
`
`2
`
`2
`
`D
`
`6
`
`12
`
`12
`
`C
`
`2 2
`
`CA
`
`D
`
`A B
`
`Assuming Wp = 3Wn
`
`Examples
`
`VDD
`
`B
`
`E
`
`2 2
`
`OUT
`
`E
`
`2
`
`C
`
`2
`
`2
`
`D
`
`2
`
`4 4
`
`2 2
`
`CA
`
`D
`
`A B
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 26
`
`UNIVERSITY OF MARYLAND
`
`28
`
`

`

`C
`
`OUT
`
`B
`
`D
`
`A B
`
`C
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 27
`
`Examples
`
`VDD
`A
`
`B
`
`C
`
`D
`
`A
`
`B
`
`UNIVERSITY OF MARYLAND
`
`29
`
`

`

`C
`
`OUT
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 28
`
`Examples
`
`VDD
`A
`
`6
`
`6
`
`18 6
`
`B
`
`6
`
`D
`
`A B
`
`C
`
`333
`
`B
`
`C
`
`D
`
`18
`
`18
`
`2
`
`A
`
`2
`
`2
`
`B
`
`2
`
`UNIVERSITY OF MARYLAND
`
`30
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 29
`
`UNIVERSITY OF MARYLAND
`
`•
`
`•
`
`•
`
`•
`
`Ways to Improve Gate Delay
`tp ≈≈≈≈ (tpHL + tpLH) ≈≈≈≈ [CL ÷ (k’ W/L VDD)]
`Reduce CL
`internal diffusion capacitance of the gate itself
`(keep the drain diffusion as small as possible)
`other terms: interconnect capacitance & fanout
`Increase W/L ratio of the transistor
`the most powerful and effective performance
`optimization tool in the hands of the designer
`watch out for self-loading! – when the intrinsic
`capacitance dominates the extrinsic load
`Increase VDD
`can trade-off energy for performance
`increasing VDD above a certain level yields only very
`minimal improvements
`reliability concerns enforce a firm upper bound on VDD
`
`•
`•
`
`•
`
`31
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 30
`
`UNIVERSITY OF MARYLAND
`
`Gate Delay, Revisited
`
`VDD
`
`Rp
`
`CL
`
`VDD
`
`VOUT
`CL
`
`Rn
`
`VOUT
`CL
`
`LH scenario
`
`HL Scenario
`
`tp ≈≈≈≈ (tpHL + tpLH) ≈≈≈≈ 0.7RrefCref (1 + Cext/SCiref)
`•
`widening the PMOS improves tpLH (Rp is lower)
`but degrades tpHL (increases intrinsic capacitance
`GGD and GDB)
`widening the NMOS improves tpHL (Rn is lower)
`but degrades tpLH (increases intrinsic capacitance
`GGD and GDB)
`
`•
`
`32
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 31
`
`UNIVERSITY OF MARYLAND
`
`Gate Delay, Revisited
`So far have sized the PMOS and NMOS so
`that the Req’s match (ratio between 2 & 3.5)
`•
`symmetrical VTC
`•
`equal high-to-low and low-to-high propagation delays
`If speed is the only concern, reduce the
`width of the PMOS device!
`•
`widening the PMOS degrades tpHL due to larger
`parasitic capacitance (intrinsic capacitance)
`B = (W/Lp)/(W/Ln)
`•
`r = Reqp/Reqn (resistance ratio of identically-sized
`PMOS and NMOS)
`Bopt ≈≈≈≈ √√√√r if wiring capacitance negligible
`
`•
`
`33
`
`

`

`Gate Delay, Revisited
`5
`
`x 10-11
`
`tpLH
`
`tpHL
`
`tp
`
`4.5
`
`4
`
`3.5
`
`3
`
`tp(sec)
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 32
`
`1
`
`•
`
`•
`
`UNIVERSITY OF MARYLAND
`
`4
`
`5
`
`3
`2
`β = (W/Lp)/(W/Ln)
`ß of 2.4 (Rp/Rn = 31 kΩΩΩΩ/13 kΩΩΩΩ) [what we’ve looked at]
`gives symmetric response
`ß of 1.6 to 1.9 gives optimal performance
`
`34
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 33
`
`UNIVERSITY OF MARYLAND
`
`Inverter Delay
`tp ==== 0.7RrefCref (1 + Cext/SCiref)
`γγγγC g
`=
`C int
`C ext
`⎛
`⎞
`-----------
`
`t p0 1 +⎝
`⎠
`γγγγ C g
`t p0 1 f
`⎞
`⎛
`γγγγ--+⎝
`⎠
`
`t p
`
`=
`
`t p
`
`=
`
`Propagation time is function of ratio of
`external to internal capacitance
`
`This ratio is called fan-out, f
`Gamma term is function of technology, γγγγ ≈≈≈≈ 1
`
`35
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 34
`
`Sizing & Big Gates
`Sizing for Large Capacitive Loads
`A3(Wp1/Wn1)
`A1(Wp1/Wn1)
`
`Cin1
`
`A0(Wp1/Wn1)
`
`A2(Wp1/Wn1)
`
`Cload
`
`•
`
`Supose Cload large (e.g. off-chip wires)
`•
`Scale each inverter (both FETs in the circuit) by a
`factor A (input capacitances scale by A)
`if input C to last inverter * A = Cload
`(i.e., Cload looks like N+1th inverter) then we have:
`Input C of last inverter = Cin1 AN = Cload
`Rearranging:
`A = [Cload ÷ Cin1]1/N
`
`•
`
`UNIVERSITY OF MARYLAND
`
`36
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 35
`
`Sizing & Big Gates
`Sizing for Large Capacitive Loads
`A3(Wp1/Wn1)
`A1(Wp1/Wn1)
`
`Cin1
`
`A0(Wp1/Wn1)
`
`A2(Wp1/Wn1)
`
`Cload
`
`•
`•
`•
`
`•
`
`Capacitances increase by factor of A left to right
`Resistances decrease by factor of A left to right
`Total delay (tpHL + tpLH):
`(Rn1+Rp1) • (Cout1+ACin1) +
`(Rn1+Rp1)/A • (ACout1+A2Cin1) + …
`= N (Rn1+Rp1) • (Cout1+ACin1)
`Find optimal chain length:
`Nopt = ln(Cload ÷ Cin1)
`
`UNIVERSITY OF MARYLAND
`
`37
`
`

`

`Sizing & Big Gates
`
`I/O Pad: large structures are ESD diodes
`and inverter chains (scale: pad is ~65 μm)
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 36
`
`UNIVERSITY OF MARYLAND
`
`38
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 37
`
`Example
`
`2/1
`
`Cin = 2.5fF
`
`Cload = 20pF
`
`Load is ~8000x that of single inverter’s
`input capacitance: find optimal solution.
`
`UNIVERSITY OF MARYLAND
`
`39
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 38
`
`UNIVERSITY OF MARYLAND
`
`Example
`
`.5/.25
`
`1.4/.7
`
`3.6/1.8
`
`9.8/4.9
`
`27/13
`
`72/36
`
`194/97
`
`523/262 1412/706
`
`(sizes in microns)
`
`Cload = 20pF
`
`Nopt = ln(20pF/2.5fF) = 8.98 => 9 stages
`Scaling factor A = (20pF/2.5fF)1/9 = 2.7
`Total delay = (tpHL + tpLH)
`= N (Rn1+Rp1) • (Cout1+ACin1)
`= N (Rn1+Rp1) • (Cout1 + [Cload ÷ Cin1]1/N Cin1)
`(assume Cin1 = 1.5Cout1 = 2.5 fF)
`= 9 • (31/9 + 13/3) • (1.85fF + 2.7 • 2.5fF)
`= 602 ps (0.6 ns)
`
`40
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 39
`
`Generalize: Logical Effort
`Want to find minimum delay for chains:
`
`Cin
`
`Cload
`
`Main Points:
`• Path length is (maybe) fixed; find scaling
`• Want constant scaling factor along path
`[ this gives same gate effort at each stage ]
`• RC delay of a gate uses sum of internal C
`(its own Cout) and input of next gate (Cin)
`
`UNIVERSITY OF MARYLAND
`
`41
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 40
`
`Definitions
`g = Gate-level logical effort
`= ratio of its input capacitance
`to that of INVERTER
`
`4r
`4r
`
`4r
`4r
`
`BA
`
`DC
`
`1
`
`B
`
`11
`
`1
`
`C
`
`D
`
`A
`
`gnor
`
`=
`
`1 nr+
`1 r+----------------
`
`A
`
`B
`
`r
`
`r
`
`2
`
`2
`
`UNIVERSITY OF MARYLAND
`
`gnand
`
`=
`
`n r+
`1 r+-------------
`
`42
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 41
`
`Definitions
`Total Path Effort H = GFB
`HN
`
`Optimal gate effort h =
`
`G = Path Logical Effort
`
`Cin
`
`Cload
`⋅⋅⋅⋅
`⋅⋅⋅⋅
`⋅⋅⋅⋅
`⋅⋅⋅⋅
`ginv gnand gnand gnor ginv
`
`Gpath
`
`=
`
`UNIVERSITY OF MARYLAND
`
`43
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 42
`
`Definitions
`Total Path Effort H = GFB
`HN
`
`Optimal gate effort h =
`
`F = Effective Fan-Out of Chain
`
`Cin
`
`F
`
`=
`
`C load
`-------------
`C in
`
`Cload
`
`Also called Electrical Effort
`
`UNIVERSITY OF MARYLAND
`
`44
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 43
`
`Definitions
`Total Path Effort H = GFB
`HN
`
`Optimal gate effort h =
`
`B = Path Branching Effort
`
`Cin
`
`B
`
`bnode∑=
`
`Cload
`
`bnode
`
`=
`
`C on-path C off-path
`+
`----------------------------------------------
`C on-path
`
`UNIVERSITY OF MARYLAND
`
`45
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 44
`
`Definitions
`Total Path Effort H = GFB
`HN
`
`Optimal gate effort h =
`
`Redefine inverter delay:
`t p0 1 f
`⎛
`⎞
`=
`γγγγ--+⎝
`t p
`⎠
`
`=>
`
`t p
`
`=
`
`t p0 p fg
`⎛
`⎞
`γγγγ------+⎝
`⎠
`
`Total delay through path:
`∑=
`⎛
`+
`D
`t p0
`pi
`⎝
`
`f igi
`⎞
`γγγγ----------
`⎠
`
`Minimum delay through path:
`N HN
`pi∑
`⎛
`⎞
`=
`+
`γγγγ----------------
`D
`t p0
`⎠
`⎝
`
`UNIVERSITY OF MARYLAND
`
`46
`
`

`

`Definitions
`Total Path Effort H = GFB
`HN
`
`si
`
`=
`
`⎛
`⎝
`
`Optimal gate effort h =
`Gate effort hi = gifi
`Sizing si for gate i in chain:
`i 1–∏
`g1s1
`⎞
`-------------
`⎠
`gi
`
`f j
`⎛
`⎞
`
`-----⎝ ⎠
`b j
`
`j
`
`1=
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 45
`
`UNIVERSITY OF MARYLAND
`
`47
`
`

`

`Analysis
`Find minimum delay for chain (assume r=2):
`4/3
`
`4/3
`
`7/3
`Cload = 500fF
`G = (1)(4/3)(4/3)(7/3)(1) = 4.15
`F = 500/20 = 25
`B = 1 (no branching)
`5
`HN
`=
`=
`103.75
`=
`h
`
`Cin = 20fF
`
`2.53
`
`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 46
`
`UNIVERSITY OF MARYLAND
`
`48
`
`

`

`ENEE 359a
`Lecture/s 9
`Transistor Sizing
`
`Bruce Jacob
`
`University of
`Maryland
`ECE Dept.
`
`SLIDE 47
`
`UNIVERSITY OF MARYLAND
`
`4/3
`fi = h / gi
`
`7/3
`Cload = 500fF
`
`Analysis
`Find minimum delay for chain (assume r=2):
`4/3
`
`Cin = 20fF
`
`f1 = 2.53
`f2 = 2.53 • 3/4 = 1.9
`f3 = 2.53 • 3/4 = 1.9
`f4 = 2.53 • 3/7 = 1.1
`f5 = 2.53
`s1 = 1
`s2 = f1 • g1/g2 = 1.9
`s3 = f1f2 • g1/g3 = 3.6
`s4 = f1f2f3 • g1/g4 = 3.9
`s5 = f1f2f3f4 • g1/g5 = 10.0
`
`49
`
`