Leakage Current Mechanisms and Leakage
`Reduction Techniques in Deep-Submicrometer
`CMOS Circuits
`
`KAUSHIK ROY, FELLOW, IEEE, SAIBAL MUKHOPADHYAY, STUDENT MEMBER, IEEE, AND
`HAMID MAHMOODI-MEIMAND, STUDENT MEMBER, IEEE
`
`Contributed Paper
`
`High leakage current in deep-submicrometer regimes is be-
`coming a significant contributor to power dissipation of CMOS
`circuits as threshold voltage, channel length, and gate oxide thick-
`ness are reduced. Consequently, the identification and modeling
`of different leakage components is very important for estimation
`and reduction of leakage power, especially for low-power appli-
`cations. This paper reviews various transistor intrinsic leakage
`mechanisms,
`including weak inversion, drain-induced barrier
`lowering, gate-induced drain leakage, and gate oxide tunneling.
`Channel engineering techniques including retrograde well and
`halo doping are explained as means to manage short-channel
`effects for continuous scaling of CMOS devices. Finally, the paper
`explores different circuit techniques to reduce the leakage power
`consumption.
`
`Keywords—Channel engineering, CMOS, dynamic Vdd, dy-
`namic Vth, gate leakage, leakage current, low-leakage memory,
`multiple Vdd, multiple Vth, scaling, stacking effect, subthreshold
`current, tunneling.
`
`I. INTRODUCTION
`
`To achieve higher density and performance and lower
`power consumption, CMOS devices have been scaled for
`more than 30 years. Transistor delay times decrease by more
`than 30% per technology generation, resulting in doubling
`of microprocessor performance every two years. Supply
`voltage
`has been scaled down in order to keep the
`power consumption under control. Hence, the transistor
`threshold voltage
`has to be commensurately scaled
`to maintain a high drive current and achieve performance
`improvement. However, the threshold voltage scaling results
`
`Manuscript received July 10, 2002; revised November 5, 2002. This work
`was supported in part by Semiconductor Research Corporation, in part by
`Defense Advanced Research Projects Agency, Intel, and IBM.
`The authors are with the School of Electrical and Computer
`Engineering, Purdue University, West Lafayette,
`IN 47907-1285
`USA (e-mail: kaushik@ecn.purdue.edu;
`sm@ecn.purdue.edu; mah-
`moodi@ecn.purdue.edu).
`Digital Object Identifier 10.1109/JPROC.2002.808156
`
`Fig. 1 Log (I ) versus V at two different drain voltages for 20
` 0.4-m n-channel transistor in a 0.35-m CMOS process [2].
`
`increase of the subthreshold leakage
`
`in the substantial
`current [1].
`Fig. 1 shows a typical curve of drain current
`versus gate voltage (VG) in logarithmic scale [2]. It allows
`measurement of many device parameters such as
`,
`, and subthreshold slope
`, that is, the slope of
`versus
`in the weak inversion state. Transistor off-state
`current
`is the drain current when the gate voltage
`is zero. The n-channel transistor in Fig. 1 has an
`of
`20 and 4 pA m at the drain voltage of 2.5 and 0.1 V,
`respectively.
`is influenced by the threshold voltage,
`channel physical dimensions,
`channel/surface doping
`profile, drain/source junction depth, gate oxide thickness,
`and
`.
`in long-channel devices is dominated by
`leakage from the drain-well and well-substrate reverse-bias
`pn junctions [2]. Short-channel transistors require lower
`power supply levels to reduce their internal electric fields
`and power consumption. This forces a reduction in the
`threshold voltage that causes a substantially large increase
`in
`[1]. This increase is due to the weak inversion state
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`PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003
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`0018-9219/03$17.00 © 2003 IEEE
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`APPLE 1012
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`(a)
`
`(b)
`
`Fig. 2
`ITRS projections for transistor scaling trends and power consumption: (a) physical
`dimensions and supply voltage and (b) device power consumption [6].
`
`. In this paper, we explore
`leakage and is a function of
`all leakage mechanisms contributing to the off-state current
`(not just the current from the drain terminal). Other leakage
`mechanisms are peculiar to the small geometries them-
`selves. As the drain voltage increases, the drain to channel
`depletion region widens, resulting in a significant increase
`in the drain current. This increase in
`is typically due
`to channel surface current caused by drain-induced barrier
`lowering (DIBL) or due to deep channel punchthrough
`currents [3]–[5]. Moreover, as the channel width decreases,
`the threshold voltage and the off current both get modulated
`by the width of the transistor, giving rise to significant
`narrow-width effect. All these adverse effects which cause
`threshold voltage reduction (leakage current increase) in
`scaled devices are called short-channel effects (SCE). To
`maintain a reasonable SCE immunity while scaling down
`the channel length, oxide thickness has to be reduced nearly
`in proportion to the channel
`length. Decrease in oxide
`thickness results in increase in the electric field across the
`gate oxide. The high electric field and low oxide thickness
`result
`in considerable current flowing through the gate
`of a transistor. This current destroys the classical infinite
`input impedance assumption of MOS transistors and thus
`affects the circuit performance severely. Major contributors
`to the gate leakage current are gate oxide tunneling and
`injection of hot carrier from substrate to the gate oxide.
`Gate-induced drain leakage (GIDL) is another significant
`
`leakage mechanism, resulting due to the depletion at the
`drain surface below the gate-drain overlap region. Fig. 2
`shows projections for transistor physical dimensions, supply
`voltage, and device power consumption according to the
`International Technology Roadmap for Semiconductors
`(ITRS) [6]. All
`the parameters are normalized to their
`values in the year 2001. As shown in Fig. 2(b), due to the
`substantial increase in the leakage current, the static power
`consumption is expected to exceed the switching component
`of the power consumption unless effective measures are
`taken to reduce the leakage power.
`Due to adverse SCEs, the channel length cannot be arbi-
`trarily reduced even if allowed by lithography. For digital
`applications, the most undesirable SCE is the reduced gate
`threshold voltage at which the device turns on, especially at
`high drain voltages. Therefore, to take the best advantage of
`the new high-resolution lithographic techniques, new device
`designs, structures, and technologies should be developed to
`keep SCEs under control at very small dimensions. In ad-
`dition to gate oxide thickness and junction scaling, another
`technique to improve short-channel characteristics is well en-
`gineering. By changing the doping profile in the channel re-
`gion, the distribution of the electric field and potential con-
`tours can be changed. The goal is to optimize the channel
`profile to minimize the off-state leakage while maximizing
`the linear and saturated drive currents. Supersteep retrograde
`wells and halo implants have been used as a means to scale
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`Fig. 3 Summary of leakage current mechanisms of
`deep-submicrometer transistors.
`
`Fig. 4 BTBT in reverse-biased pn junction [14].
`
`the channel length and increase the transistor drive current
`without causing an increase in the off-state leakage current
`[7]–[10].
`This paper is organized as follows. In Section II, different
`leakage current components and mechanisms in deep-sub-
`micrometer transistors are explained, which is essential to
`guide solutions for reducing power and leakage per transistor.
`Device options for leakage reduction, which are based on
`channel engineering, are explained in the first part of Sec-
`tion III. The second part of Section III explores different cir-
`cuit techniques for leakage control in logic and memory. Fi-
`nally, the conclusion of the paper appears in Section IV.
`
`II. TRANSISTOR LEAKAGE MECHANISMS
`
`We describe six short-channel leakage mechanisms as il-
`lustrated in Fig. 3.
`is the reverse-bias pn junction leakage;
`is the subthreshold leakage;
`is the oxide tunneling cur-
`rent;
`is the gate current due to hot-carrier injection;
`is
`the GIDL; and
`is the channel punchthrough current. Cur-
`rents
`,
`, and
`are off-state leakage mechanisms, while
`and
`occur in both ON and OFF states.
`can occur in the
`off state, but more typically occurs during the transistor bias
`states in transition.
`
`A. pn Junction Reverse-Bias Current
`Drain and source to well junctions are typically reverse
`biased, causing pn junction leakage current. A reverse-bias
`pn junction leakage
`has two main components: one is
`minority carrier diffusion/drift near the edge of the deple-
`tion region; the other is due to electron-hole pair generation
`in the depletion region of the reverse-biased junction [12].
`For an MOS transistor, additional leakage can occur between
`the drain and well junction from gated diode device action
`(overlap of the gate to the drain-well pn junctions) or carrier
`generation in drain to well depletion regions with influence
`of the gate on these current components [13]. pn junction re-
`verse-bias leakage
`is a function of junction area and
`doping concentration [12]. If both n and p regions are heavily
`doped (this is the case for advanced MOSFETs using heavily
`doped shallow junctions and halo doping for better SCE),
`band-to-band tunneling (BTBT) dominates the pn junction
`leakage [14]. This leakage mechanism is explained in Sec-
`tion II-A1.
`
`1) Band-to-Band Tunneling Current: High electric field
`10 V/cm across the reverse-biased pn junction causes
`significant current to flow through the junction due to tun-
`neling of electrons from the valence band of the p region to
`the conduction band of the n region, as shown in Fig. 4 [14].
`From Fig. 4, it is evident that for the tunneling to occur, the
`total voltage drop across the junction has to be more than the
`band gap. The BTBT current in silicon involves the emission
`or absorption of phonons, since silicon is an indirect band
`gap semiconductor. The tunneling current density is given
`by [14]
`
`and
`
`(1)
`
`is the energy-band
`is effective mass of electron;
`where
`gap;
`is the electric field at
`is the applied reverse bias;
`the junction;
`is the electronic charge; and
`is
`times
`Planck’s constant.Assuming a step junction, the electric field
`at the junction is given by [14]
`
`(2)
`
`are the doping in the p and n side, re-
`and
`where
`spectively;
`is permittivity of silicon; and
`is the built
`in voltage across the junction. In scaled devices, high doping
`concentrations and abrupt doping profiles cause significant
`BTBT current through the drain-well junction.
`
`B. Subthreshold Leakage
`Subthreshold or weak inversion conduction current be-
`tween source and drain in an MOS transistor occurs when
`gate voltage is below
`[15]. The weak inversion region is
`seen in Fig. 1 as the linear region of the curve (semilog plot).
`In the weak inversion, the minority carrier concentration is
`small, but not zero. Fig. 5 shows the variation of minority
`carrier concentration along the length of the channel for an
`n-channel MOSFET biased in the weak inversion region. Let
`us consider that the source of the n-channel MOSFET is
`grounded,
`, and the drain to source voltage
`V. For such weak inversion condition,
`drops almost
`entirely across the reverse-biased substrate-drain pn junction.
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`Fig. 5 Variation of minority carrier concentration in the channel
`of a MOSFET biased in the weak inversion.
`
`at
`As a result, the variation of the electrostatic potential
`the semiconductor surface along the channel (the
`axis) is
`small. The
`component of the electric field vector
`,
`being equal to
`, is also small. With both the number of
`mobile carriers and the longitudinal electric field small, the
`drift component of the subthreshold drain-to-source current
`is negligible. Therefore, unlike the strong inversion region
`in which the drift current dominates, the subthreshold con-
`duction is dominated by the diffusion current. The carriers
`move by diffusion along the surface similar to charge trans-
`port across the base of bipolar transistors. The exponential
`relation between driving voltage on the gate and the drain
`current is a straight line in a semilog plot of
`versus
`(see Fig. 6). Weak inversion typically dominates modern de-
`vice off-state leakage due to the low
`. The weak inversion
`current can be expressed based on the following [15]:
`
`where
`
`(3)
`
`(4)
`
`is the
`is the threshold voltage, and
`where
`thermal voltage.
`is the
`is the gate oxide capacitance;
`zero bias mobility; and
`is the subthreshold swing coeffi-
`cient (also called body effect coefficient).
`is the max-
`imum depletion layer width, and
`is the gate oxide thick-
`ness.
`is the capacitance of the depletion layer.
`In long-channel devices, the subthreshold current is inde-
`pendent of the drain voltage for
`larger than a few . On
`the other hand, the dependence on the gate voltage is expo-
`nential, as illustrated in Fig. 6 [16]. The inverse of the slope
`of the
`versus
`characteristic is called the sub-
`threshold slope
`[15] and is given by
`
`(5)
`
`Subthreshold slope indicates how effectively the transistor
`can be turned off (rate of decrease of
`) when
`is
`decreased below
`. As device dimensions and the supply
`
`Fig. 6 Subthreshold leakage in a negative-channel
`metal–oxide–semiconductor (NMOS) transistor.
`
`voltage are scaled down to enhance performance, power
`efficiency, and reliability, subthreshold characteristics may
`limit the scalability of the supply voltage. The parameter
`is measured in millivolts per decade of the drain current.
`and at room temperature,
`For the limiting case of
`60 mV/decade. Typical
`values for a bulk CMOS
`process can range from 70 to 120 mV/decade. A low value
`for subthreshold slope is desirable. It can be noted from
`the preceding expression that
`can be made smaller by
`using a thinner oxide (insulator) layer to reduce
`or a
`lower substrate doping concentration (resulting in larger
`). Changes in operating conditions—namely, lower
`temperature or a substrate bias—also modifies
`.
`1) Drain-Induced Barrier Lowering: In long-channel
`devices, the source and drain are separated far enough that
`their depletion regions have no effect on the potential or
`field pattern in most part of the device. Hence, for such
`devices, the threshold voltage is virtually independent of
`the channel length and drain bias. In a short-channel device,
`however, the source and drain depletion width in the vertical
`direction and the source drain potential have a strong effect
`on the band bending over a significant portion of the device.
`Therefore,
`the threshold voltage, and consequently the
`subthreshold current of short-channel devices, vary with the
`drain bias. This effect is referred to as DIBL. One way to
`describe it is to consider the energy barrier at the surface
`between the source and drain, as shown in Fig. 7 [17]. Under
`off conditions, this potential barrier prevents electrons from
`flowing to the drain. For a long-channel device, the barrier
`height is mainly controlled by the gate voltage and is not
`sensitive to
`. However, the barrier of a short-channel
`device reduces with an increase in the drain voltage, which
`in turn increases the subthreshold current due to lower
`threshold voltage.
`DIBL occurs when the depletion regions of the drain and
`the source interact with each other near the channel surface to
`lower the source potential barrier. When a high drain voltage
`is applied to a short-channel device, it lowers the barrier
`height, resulting in further decrease of the threshold voltage.
`The source then injects carriers into the channel surface (in-
`dependent of gate voltage). DIBL is enhanced at high drain
`voltages and shorter channel lengths. The surface DIBL typ-
`ically occurs before the deep bulk punchthrough. Ideally,
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`Fig. 7 Lateral energy-band diagram at the surface versus distance
`(normalized to the channel length L) from the source to the drain
`for: (a) long-channel MOSFET; (b) a short-channel MOSFET;
`(c) a short-channel MOSFET at high drain bias. The gate voltage
`is same for all three cases [17].
`
`Fig. 8 n channel I
`vs. V showing DIBL, GIDL, weak
`inversion, and pn junction reverse-bias leakage components [11].
`
`, but does
`DIBL does not change the subthreshold slope
`lower
`. Higher surface and channel doping and shallow
`source/drain junction depths reduce the DIBL effect on the
`subthrshold leakage current [17], [18]. Fig. 8 illustrates the
`DIBL effect as it moves the
`curve up and to the
`left as the drain voltage increases. DIBL can be measured at
`constant
`as the change in
`for a change in
`[11].
`2) Body Effect: Reverse biasing well-to-source junction
`of a MOSFET transistor widens the bulk depletion region and
`increases the threshold voltage [19]. The effect of body bias
`can be considered in the threshold voltage equation [20]
`
`where
`is the flat-band voltage;
`the substrate; and
`
`is the doping density in
`is the difference
`
`(6)
`
`Fig. 9 n channel log(I ) versus V for six substrate biases on a
`0.35-m logic process technology (V = 2.7 V) [11].
`
`between the Fermi potential and the intrinsic potential in the
`substrate. The slope of
`versus
`curve is therefore
`
`(7)
`
`which is referred to as the substrate sensitivity. It can be seen
`from (7) that the substrate sensitivity is higher for higher bulk
`doping concentration, and the substrate sensitivity decreases
`as the substrate reverse bias increases. At
`, the sub-
`strate sensitivity is
`or
`(4). Therefore,
`is
`also called body effect coefficient.
`Fig. 9 shows suppression in n-channel drain current when
`the well-to-source voltage is back biased from 0 to 5 V (the
`back bias is the well voltage) [11]. Virtually no change is seen
`in the subthreshold slope
`at different substrate biases. An
`important observation from Fig. 9 is that as
`increases,
`because of applied reverse substrate bias and a shift in the
`–
`curve,
`decreases.
`The subthreshold leakage of an MOS device including
`weak inversion, DIBL, and body effect, can be modeled as
`[21]
`
`where
`
`(8)
`
`(9)
`
`is the
`is the zero bias threshold voltage, and
`thermal voltage. The body effect for small values of source
`to bulk voltages is linear and is represented by the term
`in (7), where
`is the linearized body effect coefficient.
`the DIBL coefficient,
`is the gate oxide capacitance,
`is the zero bias mobility, and
`is the subthreshold swing
`coefficient of the transistor.
`is a term introduced to
`account for transistor-to-transistor leakage variations.
`3) Narrow-Width Effect: The decrease in gate width
`modulates the threshold voltage of a transistor, and thereby
`modulates the subthreshold leakage. There are mainly three
`ways that narrow width modulates the threshold voltage.
`
`is
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`(a)
`
`(b)
`
`Fig. 10 Three types of device structures and associated inversion–depletion layer. (a)
`Large-geometry MOSFET. (b) LOCOS gate MOSFET. (c) Trench isolated MOSFET [22].
`
`(c)
`
`First, let us consider the local oxide isolation (LOCOS) gate
`MOSFET. In the LOCOS gate MOSFET, the existence of
`the fringing field causes the gate-induced depletion region
`to spread outside the defined channel width and under the
`isolations as shown in Fig. 10(b). This results in an increase
`of the total depletion charge in the bulk region above its
`expected value. The threshold voltage of MOS can be
`defined using depletion approximation as [22]
`
`(10)
`
`where
`is the surface potential;
`is the flat-band voltage;
`is the capacitance across the oxide; and
`is the deple-
`tion charge in the bulk. Due to narrow-width effect,
`in-
`creases by
`as shown in Fig. 10(b). This effect becomes
`more substantial as the channel width decreases, and the de-
`pletion region underneath the fringing field is comparable to
`the classical depletion formed by the vertical field. This re-
`sults in increase of threshold voltage due to narrow-channel
`effect [23], [24]. This narrow-width effect can be modeled as
`an increase in
`by the amount
`given by [25]
`
`(11)
`
`where
`is the maximum
`is the substrate doping;
`vertical depletion width;
`is the capacitance across the
`oxide;
`is the effective width;
`is the oxide thickness;
`and
`is the surface potential. A more accurate model can
`be found in [24].
`the
`The second way that narrow-width modulates
`threshold voltage is due to the fact that the channel doping
`is higher along the width dimension in LOCOS gates. Due
`to the channel stop, dopants encroach under the gate. Hence,
`
`a higher voltage is needed to completely invert the channel
`[26].
`A more complex effect is seen in trench isolation devices,
`known as inverse-narrow-width effect. In the case of trench
`isolation devices, depletion layer cannot spread under the
`oxide isolation [see Fig. 10(c)]. Hence, the total depletion
`charge in the bulk does not increase
`, thereby
`eliminating the increase in the threshold voltage. On the other
`hand, due to the two-dimensional (2-D) field-induced edge-
`fringing effect at the gate edge, formation of an inversion
`layer at the edges occurs at a lower voltage than the voltage
`required at the center. Moreover, the overall gate capacitance
`now includes the sidewall capacitance
`due to
`overlap of the gate with the isolation oxide. This increases
`the overall gate capacitance [22]. Overall gate capacitance is
`therefore given by
`, which is greater than
`given in (10). Hence, the overall
`reduces as shown
`in Fig. 11 [22]. A much more complex behavior can be ob-
`served in the case of trench-isolated buried channel P-MOS-
`FETs, where reduction of the width first decreases the
`until the width is 0.4 m. The width reduction below 0.4 m
`causes a sharp increase in Fig. 12 [27].
`Rolloff: Threshold
`4) Effect of Channel Length and
`voltage of MOSFET decreases as the channel length is re-
`duced. This reduction of threshold voltage with reduction
`of channel length is known as
`rolloff. Fig. 13 shows
`the reduction of threshold voltage with reduction in channel
`length. The principal reason behind this effect is the pres-
`ence of 2-D field patterns in short-channel devices instead
`of one-dimensional (1-D) field patterns in long-channel de-
`vices. This 2-D field pattern originates from the proximity
`of source and drain regions [28]. There are depletion re-
`gions surrounding the source and drain junctions. In long-
`channel devices, since the source and drain are far apart, their
`depletion regions do not have much effect on the potential
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`Fig. 11 Variation of threshold voltage with gate width for uniform
`doping [22].
`
`Fig. 14 Schematic diagram for charge-sharing model explaining
`the reduction of V due to the source/drain depletion regions. The
`bulk charge that needs to be inverted is proportional to the area
`under the trapezoidal region given by Q / W (L + L )=2,
`which is less than the total depletion charge in the long-channel
`case, which is Q / W (L) [28].
`
`Fig. 12 Variation of threshold voltage with gate width in the
`case of trench isolated buried channel P-MOSFET showing the
`anomalous behavior [27].
`
`Fig. 13 Threshold voltage rolloff with change in channel length;
`V reduction is more severe at higher drain bias.
`
`profile or field pattern in most parts of the channel. How-
`ever, in the case of short-channel devices, source-to-drain
`distance is comparable to the depletion width in the vertical
`direction. As a result, source drain depletion width has a
`more pronounced effect on potential profiles and field pat-
`terns. The source and drain depletion regions now penetrate
`more into the channel length, resulting in part of the channel
`being already depleted. Thus, gate voltage has to invert less
`bulk charge to turn a transistor on (see Fig. 14). In other
`words, for the same gate voltage, there is more band bending
`in the Si–SiO interface in a short-channel device as com-
`
`Fig. 15
`[18].
`
`I
`
`versus V showing temperature sensitivity of I
`
`pared with a long-channel one. Consequently, the threshold
`voltage is lower for a short-channel device. The effect of
`the source drain depletion region is more severe at a high
`drain bias. High drain bias results in more depletion charge
`in the channel from the drain and source, resulting in fur-
`ther decrease of the threshold voltage, and hence, larger sub-
`threshold current.
`5) Effect of Temperature: Temperature dependence of
`the subthreshold leakage current is important, since digital
`very large scale integration (VLSI) circuits usually operate
`at elevated temperatures due to the power dissipation (heat
`generation) of the circuit.
`versus
`shows a linear
`change in subthreshold slope
`with temperature (see
`Fig. 15) as predicted by the subthreshold current model
`[15]. In Fig. 15,
`varies from 58.2 to 81.9 mV/decade
`as the temperature increases from 50 C to 25 C in a
`0.35- m technology. In this technology, the major com-
`ponent of
`is the subthershold leakage; therefore, the
`temperature dependence of
`represents the temperature
`dependence of the subthreshold leakage. The increase in
`the
`is 0.45–160 pA for the 20- m-wide device (23
`fA m to 8 pA m).
`increases by a factor of 356 for
`this technology. Two parameters increase the subthreshold
`leakage as temperature is raised: 1)
`linearly increases
`with temperature; and 2) the threshold voltage decreases.
`The temperature sensitivity of
`was measured to be about
`0.8 mV C. The temperature sensitivity of
`can be used
`to estimate
`at other temperatures.
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`

`(a)
`
`(b)
`
`Fig. 16 Tunneling of electrons through an MOS capacitor. (a) Energy-band diagram at flat-band
`condition. (b) Energy-band diagram with positive gate bias showing tunneling of electron from
`substrate to gate. (c) Energy-band diagram at negative gate bias showing tunneling of electron from
`gate to substrate [29].
`
`(c)
`
`C. Tunneling into and Through Gate Oxide
`
`Reduction of gate oxide thickness results in an increase in
`the field across the oxide. The high electric field coupled with
`low oxide thickness results in tunneling of electrons from
`substrate to gate and also from gate to substrate through the
`gate oxide, resulting in the gate oxide tunneling current.
`To understand the phenomenon of tunneling,
`let us
`consider an MOS capacitor with a heavily doped n+-type
`polysilicon gate and a p-type substrate. Also, for sim-
`plicity, let us now focus only on the electron tunneling. An
`energy-band diagram in flat-band condition is shown in
`Fig. 16(a), where
`is the Si-SiO interface barrier height
`for electrons. When a positive bias is applied to the gate, the
`energy-band diagram changes as shown in Fig. 16(b). Due
`to the small oxide thickness, which results in a small width
`of the potential barrier, the electrons at the strongly inverted
`surface can tunnel into or through the SiO layer and hence
`give rise to the gate current. On the other hand, if a negative
`gate bias is applied, electrons from the n+ polysilicon can
`tunnel into or through the oxide layer and give rise to the
`gate current [see Fig. 16(c)] [29].
`The mechanism of tunneling between substrate and gate
`polysilicon can be primarily divided into two parts, namely:
`(1) Fowler–Nordheim (FN) tunneling; and (2) direct tun-
`neling. In the case of FN tunneling, electrons tunnel through a
`triangular potential barrier, whereas in the case of direct tun-
`neling, electrons tunnel through a trapezoidal potential bar-
`rier. The tunneling probability of an electron depends on the
`thickness of the barrier, the barrier height, and the structure of
`the barrier. Therefore, the tunneling probabilities of a single
`electron in FN tunneling and direct tunneling are different,
`resulting in different tunneling currents.
`1) Fowler–Nordheim Tunneling: In FN tunneling, elec-
`trons tunnel into the conduction band of the oxide layer.
`
`Fig. 17 FN tunneling of electrons.
`
`Fig. 17 shows the FN tunneling of electrons from the inverted
`surface to the gate. Ignoring the effect of finite temperature
`and image-force-induced barrier lowering, the current den-
`sity in the FN tunneling is given by [29]
`
`(12)
`
`is the barrier
`is the field across the oxide;
`where
`height for electrons in the conduction band; and
`is the ef-
`fective mass of an electron in the conduction band of silicon.
`The FN current equation represents the tunneling through the
`triangular potential barrier and is valid for
`, where
`is the voltage drop across the oxide [30]. The measured
`value of FN tunneling current is very small; for example, at
`an oxide field of 8 MV/cm, the FN tunneling current den-
`sity is about 5
`10
`A/cm [29]. Since
`eV,
`short-channel devices mostly operate at
`. Thus, for
`normal device operation, the FN tunneling current is negli-
`gible.
`2) Direct Tunneling: In very thin oxide layers (less than
`3–4 nm), electrons from the inverted silicon surface, instead
`of tunneling into the conduction band of SiO , directly tunnel
`
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`current
`and the
`, part of which goes to the source
`rest goes to the drain
`; and the gate to the substrate
`leakage current
`(see Fig. 21) [31], [32]. The modeling
`of each of the components can be found in [31], [32].
`c) Effect of quantization of substrate electron en-
`ergy: Due to high substrate doping level and large electric
`field at the Si–SiO surface, the quantization of carrier
`energy occurs within the Si substrate (see Fig. 22). This
`results in less occupied energy states from which electrons
`can tunnel. Also due to the quantization effect, the carrier
`density in the substrate is different from the classical pre-
`diction. With the quantization, the carrier density peaks at a
`little distance away from the surface and not at the surface as
`predicted by classical physics. This can be considered as an
`effective increase in the oxide thickness. Thus, quantization
`effect modulates the gate direct tunneling current [34].
`low-
`d) Effect
`of
`image-force-induced
`barrier
`ering: The emission of electron from Si to SiO causes
`build up of image charge at the oxide side of the Si–SiO
`interface, which results in a reduction in the barrier height
`at the Si–SiO interface from
`eV by an amount
`given by
`
`(15)
`
`where
`is the permittivity of SiO . This is called the
`image-force-induced barrier-lowering effect
`[29]. Since
`it modulates the barrier height, it also modulates the gate
`tunneling current, as the tunneling exponentially depends
`on
`.
`
`Fig. 18 Direct tunneling of electrons.
`
`to the gate through the forbidden energy gap of the SiO
`layer [29]. The direct tunneling phenomenon is explained
`in Fig. 18. In the case of direct tunneling, electrons tunnel
`through a trapezoidal potential barrier instead of a triangular
`potential barrier. Hence, the direct tunneling occurs at
`[30]. The equation governing the current density of the
`direct tunneling is given by [30]
`
`(13)
`
`. Di-
`and
`where
`rect tunneling current is significant for low oxide thicknesses.
`Fig. 19 shows the variation of the direct tunneling current
`density with
`based on (13).
`Potential drop across the oxide is obtained from the fact
`that applied gate voltage over the flat-band voltage drops
`across the polysilicon depletion layer, gate oxide, and the rest
`appear as surface potential.
`
`(14)
`
`D. Injection of Hot Carriers from Substrate to Gate Oxide
`
`where
`is the surface potential;
`is the applied gate bias;
`and
`is the potential drop across the polysilicon deple-
`tion region given by
`, where
`is the
`doping concentration of polysilicon,
`is the permittivity of
`silicon, and
`is the permittivity of SiO .
`a) Mechanisms of direct tunneling: There are three
`major mechanisms for direct tunneling in MOS devices,
`namely, electron tunneling from conduction band (ECB),
`electron tunneling from valence band (EVB), and hole tun-
`neling from valance band (HVB) [31], [32] (see Fig. 20). In
`NMOS, ECB controls the gate to channel tunneling current
`in inversion, whereas gate-to-body tunneling is controlled
`by EVB in depletion-inversion and ECB in accumulation. In
`positive-channel MOSs (PMOSs), HVB controls the gate to
`channel leakage in inversion, whereas gate-to-body leakage
`is controlled by EVB in depletion-inversion and ECB in
`accumulation [31], [32]. Since the barrier height for HVB
`(4.5 eV) is considerably higher than barrier height for ECB
`(3.1 eV), the tunneling current associated with HVB is much
`less than the current associated with ECB. This results in
`lower gate leakage current in PMOS than in NMOS [33].
`b) Components of tunneling current: The gate direct
`tunneling current can be divided into five major components,
`namely, parasitic leakage current through gate-to-S/D exten-
`sion overlap region (
`and
`);