IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Chang Kwon, et al.
`In re Patent of:
`8,063,674 Attorney Docket No.: 39521-0053IP1
`U.S. Patent No.:
`November 22, 2011
`
`Issue Date:
`Appl. Serial No.: 12/365,559
`
`Filing Date:
`February 4, 2009
`
`Title:
`MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN
`DETECTORS
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandr`ia, VA 22313-1450
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`Declaration of Jacob Robert Munford
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`APPLE 1016
`
`1
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`

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`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
`
`1. My name is Jacob Robert Munford. I am over the age of 18, have
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`personal knowledge of the facts set forth herein, and am competent to testify to the
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`same.
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`2.
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`I earned a Master of Library and Information Science (MLIS) from
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`the University of Wisconsin-Milwaukee in 2009. I have over ten years of
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`experience in the library/information science field. Beginning in 2004, I have
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`served in various positions in the public library sector including Assistant
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`Librarian, Youth Services Librarian and Library Director. I have attached my
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`Curriculum Vitae as Appendix A.
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`3.
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`During my career in the library profession, I have been responsible for
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`materials acquisition for multiple libraries. In that position, I have cataloged,
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`purchased and processed incoming library works. That includes purchasing
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`materials directly from vendors, recording publishing data from the material in
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`question, creating detailed material records for library catalogs and physically
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`preparing that material for circulation. In addition to my experience in acquisitions,
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`I was also responsible for analyzing large collections of library materials, tailoring
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`library records for optimal catalog search performance and creating lending
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`agreements between libraries during my time as a Library Director.
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`4.
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`I am fully familiar with the catalog record creation process in the
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`library sector. In preparing a material for public availability, a library catalog
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`2
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`

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`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
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`record describing that material would be created. These records are typically
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`written in Machine Readable Catalog (herein referred to as MARC) code and
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`contain information such as a physical description of the material, metadata from
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`the material’s publisher and date of library acquisition. In particular, the 008 field
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`of the MARC record is reserved for denoting the creation of the library record
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`itself. As this typically occurs during the process of preparing materials for public
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`access, it is my experience that an item’s MARC record accurately indicates the
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`date of an item’s public availability.
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`5.
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`I have reviewed Exhibit 1007, an article by Jun Cheol Park and
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`Vincent J. Mooney III entitled “Sleepy Stack Leakage Reduction” from the
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`Institute of Electrical and Electronics Engineers (IEEE) publication IEEE
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`Transactions on Very Large Scale Integration (VLSI) Systems.
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`6.
`
`Attached hereto as Appendix NA01 is a true and correct copy of
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`“Sleepy Stack Leakage Reduction” from the Central Michigan University library. I
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`secured this article from IEEE Transactions on Very Large Scale Integration
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`(VLSI) Systems Vol. 14 Issue 11 (Nov. 2006) in the Central Michigan University’s
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`digital library of journal and periodicals. In comparing Appendix PA01 to Exhibit
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`1007, it is my determination that Exhibit 1007 is a true and correct copy of the
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`article by Jun Cheol Park and Vincent J. Mooney III entitled “Sleepy Stack
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`3
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`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
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`Leakage Reduction” in the IEEE Transactions on Very Large Scale Integration
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`(VLSI) Systems.
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`7.
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`Attached hereto as Appendix NA02 is a true and correct copy of the
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`MARC record for IEEE Transactions on Very Large Scale Integration (VLSI)
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`Systems from the Central Michigan University library. I secured this record from
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`the library’s online catalog.
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`8.
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`Attached hereto as Appendix NA03 is a true and correct copy of
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`Central Michigan University’s holdings for IEEE Transactions on Very Large
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`Scale Integration (VLSI) Systems. I secured this holdings list from Central
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`Michigan University’s IEEE Xplore Digital Library. As this collection’s scope
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`includes volumes of the IEEE Transactions on Very Large Scale Integration
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`(VLSI) Systems from 1966 to the present via access to IEEE’s digital archives, it is
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`my determination that IEEE Transactions on Very Large Scale Integration (VLSI)
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`Systems Vol. 14 Issue 11 containing “Sleepy Stack Leakage Reduction” is included
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`within the scope of the Central Michigan University’s collection.
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`9.
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`Attached hereto as Appendix NA04 is a true and correct copy of email
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`correspondence between myself and the IEEE Support Center. As this journal’s
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`MARC record from CMU does not track the acquisition date of particular issues, I
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`contacted the IEEE to determine when the initial journal issue was published and
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`whether or not that release date differed from the journal issue’s inclusion into the
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`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
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`IEEE Xplore Digital Library. According to the IEEE, IEEE Transactions on Very
`
`Large Scale Integration (VLSI) Systems Vol. 14 Issue 11 was first published as of
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`December 4, 2006 and the digital edition of this journal was integrated into the
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`IEEE Xplore Digital Library before the formal release as of November 27, 2006.
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`10.
`
`In my discussions with Central Michigan University digital librarians
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`I was informed that any updates made to IEEE Xplore Digital Library by the IEEE
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`are automatically reflected overnight in the university’s holdings/digital records.
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`As such, the release dates given in Appendix NA04 provide an accurate indication
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`as to when IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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`Vol. 14 Issue 11 was first made available to the public via the Central Michigan
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`University library.
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`11. The 008 field of IEEE Transactions on Very Large Scale Integration
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`(VLSI) Systems’ MARC record included in Appendix NA02 indicates that this
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`journal has been held in perpetuity by the Central Michigan University library
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`since July 19, 2000 via access to the IEEE Xplore Digital Library.
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`12. The release dates provided via the IEEE itself included within
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`Appendix NA04 provide a more specific date of November 27, 2006 as to when
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`the IEEE Xplore Digital Library would have updated with the issue of IEEE
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`Transactions on Very Large Scale Integration (VLSI) Systems containing “Sleepy
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`Stack Leakage Reduction”. Based on this information, it is my determination that
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`5
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`

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`Attorney Docket No. 39521-0053IP1
`IPR of U.S. Patent No. 8,063,674
`
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`this material would have first been made accessible and publicly available as of
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`November 27, 2006 and no later than December 4, 2006 according to the journal’s
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`formal release date.
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`13.
`
` I have been retained on behalf of the Petitioner to provide assistance
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`in the above-illustrated matter in establishing the authenticity and public
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`availability of the documents discussed in this declaration. I am being compensated
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`for my services in this matter at the rate of $100.00 per hour plus reasonable
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`expenses. My statements are objective, and my compensation does not depend on
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`the outcome of this matter.
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`14.
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`I declare under penalty of perjury that the foregoing is true and
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`correct. I hereby declare that all statements made herein of my own knowledge are
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`true and that all statements made on information and belief are believed to be true;
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`and further that these statements were made the knowledge that willful false
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`statements and the like so made are punishable by fine or imprisonment, or both,
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`under Section 1001 of Title 18 of the United States Code.
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`
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`Dated: 6/25/18
`
`Jacob Robert Munford
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`6
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`APPENDIX A
`“Curriculum Vitae of Jacob Munford”
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`7
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`Appendix A - Curriculum Vitae
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`Education
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`University of Wisconsin-Milwaukee - MS, Library & Information Science, 2009
`Milwaukee, WI
`● Coursework included cataloging, metadata, data analysis, library systems,
`management strategies and collection development.
`● Specialized in library advocacy and management.
`
`Grand Valley State University - BA, English Language & Literature, 2008
`Allendale, MI
`● Coursework included linguistics, documentation and literary analysis.
`● Minor in political science with a focus in local-level economics and
`government.
`
`Professional Experience
`
`Library Director, February 2013 - March 2015
`Dowagiac District Library
`Dowagiac, Michigan
`● Executive administrator of the Dowagiac District Library. Located in
`Southwest Michigan, this library has a service area of 13,000, an annual
`operating budget of over $400,000 and total assets of approximately
`$1,300,000.
`● Developed careful budgeting guidelines to produce a 15% surplus during the
`2013-2014 & 2014-2015 fiscal years.
`● Using this budget surplus, oversaw significant library investments including
`the purchase of property for a future building site, demolition of existing
`buildings and building renovation projects on the current facility.
`● Led the organization and digitization of the library's archival records.
`● Served as the public representative for the library, developing business
`relationships with local school, museum and tribal government entities.
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`8
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`

`● Developed an objective-based analysis system for measuring library services
`- including a full collection analysis of the library's 50,000+ circulating
`items and their records.
`
`
`November 2010 - January 2013
`Librarian & Branch Manager, Anchorage Public Library
`Anchorage, Alaska
`● Headed the 2013 Anchorage Reads community reading campaign including
`event planning, staging public performances and creating marketing
`materials for mass distribution.
`● Co-led the social media department of the library's marketing team, drafting
`social media guidelines, creating original content and instituting long-term
`planning via content calendars.
`● Developed business relationships with The Boys & Girls Club, Anchorage
`School District and the US Army to establish summer reading programs for
`children.
`
`June 2004 - September 2005, September 2006 - October 2013
`Library Assistant, Hart Area Public Library
`Hart, MI
`● Responsible for verifying imported MARC records and original MARC
`cataloging for the local-level collection as well as the Michigan Electronic
`Library.
`● Handled OCLC Worldcat interlibrary loan requests & fulfillment via
`ongoing communication with lending libraries.
`
`Professional Involvement
`
`Alaska Library Association - Anchorage Chapter
`● Treasurer, 2012
`
`Library Of Michigan
`● Level VII Certification, 2008
`● Level II Certification, 2013
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`9
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`Michigan Library Association Annual Conference 2014
`● New Directors Conference Panel Member
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`Southwest Michigan Library Cooperative
`● Represented the Dowagiac District Library, 2013-2015
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`Professional Development
`
`Library Of Michigan Beginning Workshop, May 2008
`Petoskey, MI
`● Received training in cataloging, local history, collection management,
`children’s literacy and reference service.
`
`Public Library Association Intensive Library Management Training, October 2011
`Nashville, TN
`● Attended a five-day workshop focused on strategic planning, staff
`management, statistical analysis, collections and cataloging theory.
`
`Alaska Library Association Annual Conference 2012 - Fairbanks, February 2012
`Fairbanks, AK
`● Attended seminars on EBSCO advanced search methods, budgeting,
`cataloging, database usage and marketing.
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`10
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`ATTACHMENT NA01
`“Park Full Article (CMU)”
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`11
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`1250
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`IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006
`
`Sleepy Stack Leakage Reduction
`
`Jun Cheol Park and Vincent J. Mooney III, Senior Member, IEEE
`
`Abstract—Leakage power consumption of current CMOS
`technology is already a great challenge. International Technology
`Roadmap for Semiconductors projects that leakage power con-
`sumption may come to dominate total chip power consumption as
`the technology feature size shrinks. Leakage is a serious problem
`particularly for CMOS circuits in nanoscale technology. We pro-
`pose a novel ultra-low leakage CMOS circuit structure which we
`call “sleepy stack.” Unlike many other previous approaches, sleepy
`stack can retain logic state during sleep mode while achieving
`ultra-low leakage power consumption. We apply the sleepy stack
`to generic logic circuits. Although the sleepy stack incurs some
`delay and area overhead, the sleepy stack technique achieves the
`lowest leakage power consumption among known state-saving
`leakage reduction techniques, thus, providing circuit designers
`with new choices to handle the leakage power problem.
`Index Terms—Dual- th, low-leakage power dissipation, tran-
`sistor stacking.
`
`I. INTRODUCTION
`
`P OWER consumption is one of the top concerns of VLSI
`
`circuit design, for which CMOS is the primary technology.
`Today’s focus on low power is not only because of the recent
`growing demands of mobile applications. Even before the mo-
`bile era, power consumption has been a fundamental problem.
`To solve the power dissipation problem, many researchers have
`proposed different ideas from the device level to the architec-
`tural level and above. However, there is no universal way to
`avoid tradeoffs between power, delay, and area, and thus, de-
`signers are required to choose appropriate techniques that sat-
`isfy application and product needs.
`Power consumption of CMOS consists of dynamic and static
`components. Dynamic power is consumed when transistors are
`switching and static power is consumed regardless of transistor
`switching. Dynamic power consumption was previously (at
`0.18- m technology and above) the single largest concern
`for low-power chip designers since dynamic power accounted
`for 90% or more of the total chip power. Therefore, many
`previously proposed techniques, such as voltage and frequency
`scaling, focused on dynamic power reduction. However, as the
`feature size shrinks, e.g., to 0.09 and 0.065 m, static power
`has become a great challenge for current and future technolo-
`gies. Based on the International Technology Roadmap for
`Semiconductors (ITRS) [1], Kim et al. report that subthreshold
`leakage power dissipation of a chip may exceed dynamic power
`dissipation at the 65-nm feature size [2].
`
`One of the main reasons causing the leakage power increase
`is the increase of subthreshold leakage power. When technology
`feature size scales down, supply voltage and threshold voltage
`also scale down. Subthreshold leakage power increases expo-
`nentially as threshold voltage decreases. Furthermore, the struc-
`ture of the short channel device decreases the threshold voltage
`even lower. In addition to subthreshold leakage, another con-
`tributor to leakage power is gate-oxide leakage power due to the
`tunneling current through the gate-oxide insulator. Since gate-
`oxide thickness may reduce as the channel length decreases, in
`sub 0.1- m technology, gate-oxide leakage power may be com-
`parable to subthreshold leakage power if not handled properly.
`However, we assume other techniques will address gate-oxide
`leakage; for example, high- dielectric gate insulators may pro-
`vide a solution to reduce gate-leakage [2]. Therefore, this paper
`focuses on reducing subthreshold leakage power consumption.
`In this paper, we provide a new circuit structure named
`“sleepy stack” as a remedy for static power consumption. The
`sleepy stack has a novel structure that uniquely combines the
`advantages of two major prior approaches, the sleep transistor
`technique and the forced stack technique. However, unlike the
`sleep transistor technique, the sleepy stack technique retains the
`original state; furthermore, unlike the forced stack technique,
`to achieve up
`the sleepy stack technique can utilize high-
`to two orders of magnitude leakage power reduction compared
`to the forced stack. Unfortunately, the sleepy stack technique
`comes with delay and area overheads. Therefore, the sleepy
`stack technique provides new Pareto points [3] to designers
`who require ultra-low leakage power consumption and are
`willing to pay some area and delay cost.
`The main contributions of this paper are as follows: 1) intro-
`duction of a sleepy stack structure that can save leakage power
`up to two orders of magnitude for circuits that require extremely
`low leakage power consumption and 2) analysis of example
`sleepy stack logic circuits in terms of various ways (transistor
`scaling, threshold voltage, and transistor width) circuit design
`engineers can employ to adopt the sleepy stack technique as nec-
`essary.
`This paper is organized as follows. In Section II, prior work
`about low-leakage logic design is discussed. In Section III, the
`sleepy stack structure is explained and an analytical delay model
`is discussed. In Section IV, an empirical methodology applying
`the sleepy stack to generic logic is explained. In Section V, the
`experimental results of the sleepy stack for generic logic is pre-
`sented. In Section VI, conclusions are given.
`
`Manuscript received August 5, 2005; revised July 7, 2006.
`J. C. Park is with the Mobility Group, Intel Corporation, Folsom, CA 95630
`USA (e-mail: juncheol.park@intel.com).
`V. J. Mooney III is with the School of Electrical and Computer Engi-
`neering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail:
`mooney@ece.gatech.edu).
`Digital Object Identifier 10.1109/TVLSI.2006.886398
`
`II. PREVIOUS WORK
`
`In this section, we discuss previous low-power techniques
`that primarily target reducing leakage power consumption of
`CMOS circuits. Techniques for leakage power reduction can
`
`1063-8210/$20.00 © 2006 IEEE
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`12
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`PARK AND MOONEY III: SLEEPY STACK LEAKAGE REDUCTION
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`1251
`
`be grouped into the following two categories: 1) state-saving
`techniques where circuit state (present value) is retained and
`2) state-destructive techniques where the current Boolean output
`value of the circuit might be lost [2]. A state-saving technique
`has an advantage over a state-destructive technique in that with a
`state-saving technique the circuitry can immediately resume op-
`eration at a point much later in time without having to somehow
`regenerate state. We characterize each low-leakage technique
`according to this criterion.
`State-destructive techniques cut off transistor (pull-up or pull-
`down or both) networks from supply voltage or ground using
`sleep transistors [4]. These types of techniques are also called
`and gated-
`(note that a gated clock is gener-
`gated-
`ally used for dynamic power reduction). Motoh et al. propose a
`technique they call multithreshold-voltage CMOS (MTCMOS)
`[4], which adds high-
`sleep transistors between pull-up net-
`works and
`and between pull-down networks and ground
`while logic circuits use low-
`transistors in order to maintain
`fast logic switching speeds. The sleep transistors are turned off
`when the logic circuits are not in use. By isolating the logic net-
`works using sleep transistors, the sleep transistor technique dra-
`matically reduces leakage power during sleep mode. However,
`the additional sleep transistors increase area and delay. Further-
`more, during sleep mode, the pull-up and pull-down networks
`will have floating values and, thus, will lose state. These floating
`values significantly impact the wake-up time and energy of the
`sleep technique due to the requirement to recharge transistors
`which lost state during sleep (this issue is nontrivial, especially
`for registers and flip-flops).
`To reduce the wake-up cost of the sleep transistor technique,
`the zigzag technique is introduced [5]. The zigzag technique
`reduces the wake-up overhead by choosing a particular circuit
`state (e.g., corresponding to a “reset”) and then, for the exact
`circuit state chosen, turning off the pull-down network for each
`gate whose output is high while conversely turning off the
`pull-up network for each gate whose output is low.
`By applying, prior to going to sleep, the particular input pat-
`tern chosen prior to chip fabrication, the zigzag technique can
`prevent floating. Although the zigzag technique retains the par-
`ticular state chosen prior to chip fabrication, any other arbitrary
`state during regular operation is lost in power-down mode.
`Another technique to reduce leakage power is transistor
`stacking. Transistor stacking exploits the stack effect;
`the
`stack effect results in substantial subthreshold leakage current
`reduction when two or more stacked transistors are turned off
`together. Narendra et al. study the effectiveness of the stack
`effect including effects from increasing the channel length [6].
`Since forced stacking of what previously was a single tran-
`sistor increases delay, Johnson et al. propose an algorithm that
`finds circuit input vectors that maximize stacked transistors of
`existing complex logic [7]. As a variation of the stacking tran-
`sistors, Hanchate and Ranganathan introduce self-controlled
`stacked transistors which are inserted between pull-up and
`pull-down networks and reduce leakage power by increasing
`internal resistance [8].
`Our sleepy stack structure can achieve more power savings
`than the forced stack technique and the self-controlled stacked
`transistors (e.g., 100
`compared with 10
`for the forced
`
`(a) Forced stack technique applied to an inverter. (b) Sleep transistor
`Fig. 1.
`technique applied to an inverter.
`
`stack transistor or the self-controlled stacked transistors).
`Furthermore, the sleepy stack can save exact logic state unlike
`gated-
`and gated-
`techniques (conventional sleep tran-
`sistor technique) and the zigzag technique.
`In Section III, we will discuss the sleepy stack structure and
`sleepy stack operation.
`
`III. SLEEPY STACK STRUCTURE
`We introduce our new leakage power reduction technique we
`name “sleepy stack.” The sleepy stack technique has a combined
`structure of the forced stack technique and the sleep transistor
`technique. However, unlike the sleep transistor technique, the
`sleepy stack technique retains exact logic state when in sleep
`mode; furthermore, unlike the forced stack technique, the sleepy
`stack technique can utilize high-
`transistors without 5
`(or
`greater) delay penalties. Therefore, far better than any prior ap-
`proach known to the authors of this paper, the sleepy stack tech-
`nique can achieve ultra-low leakage power consumption while
`saving state.
`We, first, explain the structure of the sleepy stack technique
`using an inverter. Then, we describe the details of sleepy stack
`operation in active mode and sleep mode. The advantages of
`the sleepy stack technique over the forced stack technique and
`the sleep transistor technique are explored. Finally, we derive a
`first-order delay model that compares the sleepy stack technique
`to the forced stack technique analytically.
`
`A. Sleepy Stack Approach
`In this section, we explain our sleepy stack structure com-
`paring to the forced stack technique and the sleep transistor tech-
`nique. The details of the sleepy stack inverter are described as
`an example. Two operation modes, active mode and sleep mode,
`of the sleepy stack technique are explored.
`1) Sleepy Stack Structure: The sleepy stack structure has
`a combined structure of the forced stack and the sleep tran-
`sistor techniques. Although we mentioned these two techniques
`in Section II, we focus on explaining forced stack and sleep
`transistor inverters here for the purposes of comparison with a
`sleepy stack inverter. Fig. 1(a) depicts a forced stack inverter and
`Fig. 1(b) depicts a sleep transistor inverter. The forced stack in-
`verter breaks existing transistors into two transistors and forces a
`stack structure to take advantage of the stack effect; this is shown
`in Fig. 1(a). Meanwhile, the sleep transistor inverter shown in
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`IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006
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`(a) Sleepy stack inverter with W=L of each transistor and active mode
`Fig. 2.
`S, S assertion. (b) Sleep mode S, S assertion.
`
`Fig. 1(b) isolates existing logic networks using sleep transis-
`tors. The stack structure in Fig. 1(b) saves leakage power con-
`sumption during sleep mode. This sleep transistor technique
`frequently uses high-
`sleep transistors (the transistors con-
`trolled by
`and
`) to achieve larger leakage power reduction.
`The sleepy stack technique has a structure merging the forced
`stack technique and the sleep transistor technique. Fig. 2 shows
`a sleepy stack inverter. The sleepy stack technique divides ex-
`isting transistors into two transistors each typically with the
`same width
`half the size of the original single transistor’s
`width
`(i.e.,
`), thus, maintaining equivalent
`input capacitance. The sleepy stack inverter in Fig. 2(a) uses
`for the pull-up transistors and
`for the
`pull-down transistors, while a conventional inverter with the
`same input capacitance would use
`for the pull-up
`transistor and
`for the pull-down transistor (assuming
`). Then sleep transistors are added in parallel to
`one of the transistors in each set of two stacked transistors.
`We use a transistor sized as half the width of the original tran-
`sistor (i.e., we use
`) for the sleep transistor width of the
`sleepy stack. Although we exclusively use
`for the width
`of the sleep transistor, changing the sleep transistor width in
`various ways may provide additional tradeoffs between delay,
`power, and area. However, in this paper, we mainly focus on
`applying the sleepy stack structure with
`sleep transistor
`widths to generic logic circuits while varying technology fea-
`ture size, threshold voltage, and temperature. Please note that
`halving transistor width is not possible for a circuit that uses
`minimum size transistors. However, many circuits use nonmin-
`imum size to gain driving strength. In any case, if we cannot
`halve transistor width, then we simply use minimum width.
`2) Sleepy Stack Operation: Now we explain how the sleepy
`stack works during active mode and during sleep mode. Also,
`we explain leakage power savings using the sleepy stack struc-
`ture.
`The sleep transistors of the sleepy stack operate similar to the
`sleep transistors used in the sleep transistor technique in which
`sleep transistors are turned on during active mode and turned
`off during sleep mode. Fig. 2 depicts the sleepy stack operation
`using a sleepy stack inverter. During active mode [Fig. 2(a)],
`and
`are asserted, and, thus, all sleep transistors
`
`Fig. 3.
`
`(a) Inverter circuit schematic. (b) RC equivalent circuit.
`
`are turned on. This sleepy stack structure can potentially reduce
`circuit delay in two ways. First, since the sleep transistors are al-
`ways on during active mode, the sleepy stack structure achieves
`faster switching time than the forced stack structure; specifi-
`cally, in Fig. 2(a), at each sleep transistor drain, the voltage
`value connected to the sleep transistor source is always ready
`and available at the sleep transistor drain, and thus, current flow
`transistors connected to
`is immediately available to the low-
`the gate output regardless of the status of each transistor in par-
`allel to the sleep transistors. Furthermore, we can use high-
`transistors (which are slow but 1000
`or so less leaky) for the
`sleep transistors and the transistors parallel to the sleep transis-
`tors (see Fig. 2) without incurring large (e.g., 2 or more) delay
`increase.
`During sleep mode [Fig. 2(b)],
`are
`and
`asserted, and so both of the sleep transistors are turned off.
`Although the sleep transistors are turned off, the sleepy stack
`structure maintains exact logic state. The leakage reduction of
`the sleepy stack structure occurs in two ways. First, leakage
`power is suppressed by high-
`transistors, which are applied
`to the sleep transistors and the transistors parallel to the sleep
`transistors. Second, stacked and turned off transistors induce
`the stack effect [11], which also suppresses leakage power
`consumption. By combining these two effects, the sleepy stack
`structure achieves ultra-low leakage power consumption during
`sleep mode while retaining exact logic state. The price for this,
`however, is increased area.
`We will derive an analytical delay model of the sleepy stack
`inverter and compare the sleepy stack technique to the forced
`stack inverter in the next section. This analytical comparison
`of the next section, Section III-B, can be skipped if desired.
`The detailed experimental methodology and the results will be
`presented in Section IV.
`
`B. Analytical Comparison of Sleepy Stack Inverter Versus
`Forced Stack Inverter
`In this section, an analytical delay model of a sleepy stack
`inverter is explained and compared to a forced stack inverter,
`the best prior state-saving leakage reduction technique we could
`find.
`Generally, the transistor delay of a conventional inverter
`shown in Fig. 3 driving a load of
`can be expressed using
`the following equation:
`
`where
`tance.
`
`is the transistor resis-
`is the load capacitance and
`in Fig. 3(b) indicates input capacitance. Although the
`
`(1)
`
`14
`
`

`

`PARK AND MOONEY III: SLEEPY STACK LEAKAGE REDUCTION
`
`1253
`
`is 50%
`We assume that the internal node capacitance
`larger than
`because
`is the capacitance from three tran-
`sistors connected, while
`is the capacitance from two tran-
`sistors connected. Then
`
`(6)
`
`(7)
`
`Therefore,
`and
`if we use the same
`is 25% faster than
`for the forced stack inverter and the sleepy stack inverter.
`Alternatively, we may increase
`of the sleepy stack inverter
`and make the delay of the sleepy stack inverter and the delay of
`the forced stack inverter the same.
`Let us take an example. The gate delay of a CMOS circuit can
`be expressed as shown in the following approximated equation:
`
`(8)
`
`denote the gate delay in a CMOS cir-
`, and
`,
`where
`cuit, the threshold voltage, and velocity saturation index of a
`transistor, respectively. Using (8), the delay of the forced stack
`and the delay of the sleepy stack
`can be expressed as
`follows:
`
`(9)
`
`(10)
`
`and
`
`where
`are delay coefficients of the forced stack
`and
`inverter and the sleepy stack inverter, respectively. When the
`threshold voltage of the forced stack
`is the same as the
`threshold voltage of the sleepy stack
`, we calculate
`V,
`from (7). If we assume that
`,
`by applying
`equal to
`V, we can make
`of the forced
`, which is 69% higher than the
`stack inverter. This higher
`can potentially result in large
`leakage power reduction (e.g., 10 ).
`In this section, we introduced the sleepy stack technique for
`leakage power reduction. By combining the forced stack tech-
`nique and the sleep transistor technique, the sleepy stack can
`achieve smaller transistor delay than the forced stack technique
`while retaining state unlike the sleep transistor technique. The
`main advantage of the sleepy stack approach is the ability to use
`high-
`for both the sleep transistors and the transistors in par-
`allel with the sleep transistors. The increased threshold voltage
`transistors of the sleepy stack technique potentially brings much
`larger ( 10 ) leakage power reduction than the forced stack
`technique while achieving the same transistor delay. From the
`analytical model of the sleepy stack inverter, we observe that
`the sleepy stack inverter can reduce delay by 25%, which al-
`ternatively can be used to increase
`by 69%. Using this in-
`creased threshold voltage, the sleepy stack inverter can poten-
`tially achieve a large (e.g., 10 ) leakage power reduction com-
`pared to the forced stack inverter.
`In this section, we explained the sleepy stack structure and
`sleepy stack operation. We also described a first-order delay
`model of the sleepy stack (please note that all power and
`delay results reported in Section V are based, however, on
`
`(a) Forced stack technique inverter circuit schematic. (b) RC equivalent
`
`Fig. 4.
`circuit.
`
`Fig. 5.
`
`(a) Sleepy stack technique inverter schematic. (b) RC equivalent circuit.
`
`nonsaturation mode equation is complicated, we can predict the
`adequate first-order gate delay from (1) [14].
`Now we derive the delay of the inverter with the forced
`stack technique shown in Fig. 4. Since we assume that we
`break each existing transistor into two half sized transistors
`(see Section III-A1), the resistance of each transistor of the
`forced stack technique is doubled, i.e.,
`, compared to the
`standard inverter; furthermore, in this way, we can maintain
`input capacitance equal to Fig. 3(b). In Fig. 4,
`is internal
`node capacitance between the two pull-down transistors. Using
`the Elmore equation [10], we can express the dela