A REVIEW OF SEMICONDUCTOR ?ACKAGING AND ITS ROLE IN ELECTRONICS MANUFACTURING
`
`G W GRIFFITHS
`CAMMAX Machines Limited, Ely, Cambridge, England
`
`the most
`is
`functionality brought by semiconductor technology
`low cost
`The
`important
`factor
`in
`the widespread use of electronics.
`Interconnection and
`assembly
`technologies enable semiconductor science to bring
`its
`processing
`power
`to
`fulfilment in overall systems integration. The small semiconductor
`structures must be brought into contact with the outside world. Together with
`suitable substrate technologies,
`semiconductors can be used in any of the forms
`available, from bare dice to encapsulated, tested and burnt-in complex functions
`in LSI.
`This
`review examines the development of semiconductors, with
`the
`emphasis on
`the
`forms of packaging available. Until
`the dream of
`total
`self-sufficiency of silicon becomes a reality more and more
`innovative and
`complex means will be proposed to deal with the problems of ever increasing lead
`counts,
`some of which will mature into manufacturing methods. Designing on
`silicon
`has
`a
`strong
`influence,
`bringing
`into
`focus
`the
`fact
`that
`interconnection adds cost not functionality, this latter lies in the silicon.
`
`INTRODUCTION
`
`Electronics started by using semiconductors but the early detector crystals and
`oxide rectifiers had little impact outside their immediate area of use. Where
`amplification or nonlinear signal processing was needed
`thermionic devices
`prevailed until semiconductor microwave diodes ousted thermionic types
`in
`the
`1940s. The
`invention of
`the transistor
`started
`the modern
`technological
`revolution that has changed the whole industrial scene.
`
`Early semiconductors, mostly in germanium, had open pn Junctions with a high
`susceptibility to moisture and needed hermetic encapsulation. This meant
`that
`little choice was available in packaging. Silicon was handicapped by
`the
`material properties and its use was restricted to areas where
`its technical
`properties were needed.
`
`to
`invention of the diffused planar method of fabrication brought silicon
`The
`the fore as the material for low cost high performance transistors. The planar
`process involves the thermal growth of silicon dioxide on a silicon wafer which
`acts as a mask to the gaseous dopants used during diffusion and remains after as
`a hermetic seal over the pn junction. Planar processing gives significant
`advantages in manufacturing methods for silicon semiconductors.
`
`imaging and chemical etching can define multiple, very small
`Photographic
`diffusion windows over a large area enabling many devices
`to be processed
`simultaneously on single wafer.
`
`Control over diffusion processes enables a high degree of uniformity and
`reliability to be obtained at low cost.
`
`Oxide protection of the junctions, inherent in the process, removes the need for
`hermetic encapsulation, allowing low cost device packaging in plastic.
`
`Planar methods encompass bipolar and field effect structures.
`
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`The oxide can support metal connections defined by phot09raphic means on a
`microscopic scale between diffused areas, diffused tracks can also be used under
`the oxidise so enabling multi-level wafer interconnection.
`
`Continuous refinements in technology have lead to Small scale Integration (SSI),
`Medium scale Integration (MSI}, Large scale Integration (LSI} and very Large
`Scale
`Integration
`(VLSI) with
`the promise of Wafer scale
`Integration.
`In
`achieving this the high involvement in circuitry of semiconductor manufacturers
`has lead to them a having a significant amount of the initiative in electronics.
`
`into
`the wafer
`transistors and ICs are cut from
`Basic semiconductor parts -
`"die" or "chips" which are small and inaccessible for connection using normal
`assembly processes. For
`technical and economic reasons,
`the silicon
`in a
`transistor or an integrated circuit should be no larger than the diffused areas
`dictate. Bonding pads do not contribute to the function and must be minimised in
`area, well below the size which would allow for direct connection
`to a PCB.
`Presenting the devices to the user in a practical fora is part of semiconductor
`manufacturing, a large sector of which is given over
`to packaging.
`
`It allows handling the devices on a scale compatible with other components
`testing, grading and assembly - automated or otherwise.
`
`for
`
`It protects against physical damage during assembly and use.
`
`Type, date code and other information can be printed on the package.
`
`Much of the added value is in the packaging which is something the semiconductor
`manufacturers are unwilling to forgo.
`
`Packaging
`both.
`
`involves several operations,
`
`some physical,
`
`some electrical,
`
`some
`
`lead frame
`The dice must be physically held on a supporting structure - header,
`or substrate. This may include making some or all of the electrical connections.
`Mass production of "conventional" semiconductors uses die bonding to locate, fix
`and
`in some cases electrically connect the dice,
`the latter for example
`in
`bipolar
`transistors where a low ohmic connection between the die and substrate
`is needed. Bonding may be by metallurgical means, by forming a gold/silicon
`eutectic or soldering. Alternatively gluing can be used with the glue having
`metallic additives for electrical conductivity. Eutectic bonding is strong and
`convenient
`to mechanise. No materials other than the silicon die and a gold
`plated headers or lead frames are needed. Thick Film gold will work
`for
`this
`purpose also. The process used a fairly high temperature and does not
`find
`favour in multi-chip applications for this reason. Gluing is an alternative for
`both single and multi-chip applications, with mechanisation being possible.
`As
`it reduces the amount of gold needed,
`gluing offers savings in materials. It
`offers flexibility of choice on mounting materials and finishes due
`to
`low
`processing temperatures.
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`semiconductors is a further
`Connectioning to the bonding pads on "conventional"
`operation. Fine wires of gold or aluminium are diffusion bonded to
`the metal
`pads and
`taken to the +eo:minals of the package. The process uses pressure.
`temperature,
`and
`frequently ultrasonic energy.
`Aluminium predomi:1ate:s
`for
`metallisation but where additional passivation
`is
`required more
`complex
`metallisations are adopted using noble and refractory metals.
`
`3.nC.
`The silicon dice and fine wires needs protectio:-. 3.gai2.st physl-::3..:..
`~~3.ma.::ic
`chemical ccmtamination. Prctection can be by a metal enclosure around the dicF::(cid:173)
`or by embedding it in plastic. The use of plastic •s widespread and, whilst root
`truly hermetic offers protection to a level suitable for th>? mos-1-
`.J..pt:l::J:::at1ons.
`Plastic allows a high degree of mechanisation and standardisation, both at
`the
`manufacturer's and user's end.
`
`into
`By modifying the processing the mounting and connections may be integrated
`one process. Some processes use totally different wafer processing - Beam Lead
`for example -
`some use the standard processing up to a late stage in the wafer
`processing - flip chip, TAB for example.
`
`The forms of semiconductor dice and the packaging options are discussed below.
`
`D_EVICE~ __ F]l_Q_M
`
`:'>TANDA_BQ_ DIFFUSION PROCES_§ING
`
`technologies developed alongside silicon planar. As no Surface Mounting
`Film
`Types were available to start,
`the inconvenience of mounting wire ended devices
`on
`to surfaces without holes could be avoided by using elemental silicon dice
`and
`treating
`the substrate as a header. Dice directly mounted on substrates
`gives very high density packaging and is, in principle,
`low cost -
`but
`there
`are technical and commercial problems to be overcome.
`
`Problems and solutions:
`
`Semiconductor manufacturers are being asked to supply a product with most of the
`value yet to be added. They draw attention to the problems and support a
`lobby
`favouring encapsulated devices. The difficulties can be overcome and
`the
`advantages make the technology attractive.
`
`Wafer scribing with a diamond could damage dice. This could cause whole circuits
`to be rejected with only one bad die on them. The use of wafer sawing has all
`but eliminated this problem.
`
`reJects,
`Device checking at the wafer stage is by probing to sort out absolute
`with no attempt at measurement and grading
`into parameter groups. However
`parameters vary gradually with position on the wafer so that large areas contain
`very similar devices. Sampling can characterise devices and be used
`to map
`wafers. Sample die can be used for stress
`testing
`to assess
`long
`term
`reliability. The semiconductor manufacturers could do this it is pointless whee
`devices are going to be finally tested anyway.
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`Hybrid circuit manufacturers had to acquire specialised knowledge, skills and
`machines. For some time the only equipment available was designed
`for mounting
`on headers or lead frames and ill suited to hybrid
`lllllilufacture. Attempts
`to
`adapt machines never had much success. Hybrid manufacturers initially had
`to
`make a lot of their own equipment and developed associations with machine makers
`or
`spawned breakaway groups to create sources
`for suitable equipment. The
`general availability of equipment today is helping to speed the adoption of chip
`and wire assembly on hybrid and PCBs.
`
`Device degradation due to exposure to high the temperatures of eutectic bonding
`lead to gluing,
`now in general use by the semiconductor manufacturers. The use
`of conductive adhesives for die mounting can, by using good back metallisation
`on the wafer. give electrical characteristics better than eutectic bonding. For
`most
`ICs, with all connectionis on
`the
`top surface,
`using
`cheaper,
`nonconducting. adhesives is possible. Thermosonic gold wire bonding at about 150
`deg. C, gives no measurable
`device deterioration but restricts substrate
`materials. Ultrasonic aluminium wire bonding, done at room temperature, can be
`applied
`to most metallisations on organic
`or
`nonorganic
`substrates.
`Mechanisation of aluminium
`bonding
`is complex but well supported with
`equipment.
`
`Commercial Aspects
`
`IC,
`from differing diffusion sources, Bipolar, FET, Digital,
`Semiconductors
`Discrete, Non-Silicon - GaAs, GaAsP LEDs etc. can be combined in a high density
`fashion on hybrid ~nd PCB in a way that SM on PCB cannot rival in density and
`pE:rformance nor monoli.thic on its own in the combir..a.ti.on cf technolog~es~
`
`reluctantly.
`rather
`Semicond•~cc'.Or ;r,anufacturers support chip and wire dice
`Frequently dice are treated as specials and c:Hered only via die houses. at a
`very high added cost. This has restricted use to high cost, high density
`military/avionics
`type applications where
`the cost, due
`to multiple
`die
`handling by intermediaries can be accepted. That the use of naked dice is sound
`and economica~ly viable
`is clear from their use by equipment manufacturers
`having their own semiconductor operations,
`a example is car electronics, where
`ruggedness and performance are extremely challenging. An
`cost.
`reliability,
`exception
`to the reluctance to supply dice is in the area of custom and custom
`ICs with most of the added value in the design and wafer processing. Many
`suppliers of custom and seaicustom ICs prefer users to take wafers and sort out
`their own encapsulation.
`
`Substrate requirements for direct bonding of dice:
`
`Direct bonding to substrates is applicable over the whole range of semiconductor
`devices
`-
`from micro wave with devices on micro-strip having dimensions below
`200 microns square, to LSI and large power devices up to
`lea square.
`
`conductive epoxy die bonding can be done on all substrate materials, plated
`Pd/Ag & Au on thick film as well as Au or Ni on thin
`copper on PCB,
`film. On
`bipolar devices saturation voltages are low and consistent. To satisfy
`some
`specification gold
`loaded epoxy may be substituted for silver
`loaded epoxy
`although usually
`the only difference to be seen is the cost. Bipolar devices
`need back metallising such as Ni, Au or various alloys, usually put on by the
`semiconductor supplier. Power devices with larger areas, having the need
`for
`high electrical and
`thermal conduction may be soft soldered. This
`is an
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`is done
`technique on hybrid substrates and as a production method
`established
`without
`flux,
`in an inert atmosphere, using a oven. The fairly close match
`between
`the thermal expansion of alumina and silicon alleviates the problem of
`solder crystalisation due to thermal stress (this is a characteristic of devices
`mounted on copper headers, forcing other methods or intermediate metal layers to
`be used).
`Jigging and weighting the dice, metering the solder by printing and
`good oven control will ensure a void-free joint. The method is not applicable to
`PCB as the materials have generally poor thermal conduction.
`
`Wire bonding needs gold substrate metallisation. The effect of high material
`costs when using gold on thick film can be minimised by applying it only on
`the
`small area needed for bonding. On PCBs a soft gold coating of a few tenths of a
`micron is sufficient. This can be selectively plated but it must have a nickel
`barrier layer under to suppress copper diffusion into the gold. Aluminium wire
`may be applied by wedge bonding on cold substrates with wires up to 250 microns
`diameter. Aluminium wire is frequently used for power devices because
`it
`is
`economically obtainable in much heavier gauges than gold.
`
`Plasma de-smearing can improve bond strengths on PCB and alumina substrates.
`Plasma cleaning appears
`to have no measurable effect on other substrate
`properties, such as resistor characteristics.
`
`Hybrid production in companies with no semiconductor experience makes solderable
`encapsulated active devices preferable. Users struggled with formed wire ended
`types until SOT devices, first made for use on PCBs in the 1960s.
`together with
`the SO
`IC versions became available. Diodes can also be supplied as Metal
`ELectrode Face bonded (MELF) format, wire ended devices with the wires left off.
`The use of surface mounting on PCBs means the availability of devices in
`these
`packages is extensive and expanding, with good availability. They are favoured
`by the semiconductor manufacturers who see more added value
`than on naked dice.
`Their use,
`and the associated problems are well reported. Some general comments
`can be made however.
`90% of companies in electronics assembly do not make
`anything other than joints. The secret of success is obtaining good material and
`making good joints. Solder has been the traditional means to make connections to
`Dual-in-Line (DIL) devices and extended to SOT/SO, where it is frequently used
`to hold as well as connect. With four times the surface density of DIL. greater
`care needs
`to be taken to ensure that good joints are made,
`leads must have
`solder only on the joint areas. Too much will reduce the compliance of the leads
`and ~ause eventual failure during thermal cycling. Whereas passive components
`can have metallisation suited to epoxy adhesive attachment or solder, SOT/SO
`devices, having
`tinned leads, are only suited to solder attachment. Design
`rules, manufacturing control and production line discipline have
`to be more
`stringent with surface mounting.
`
`As lead counts rise. packages with leads down two sides cease to be effective.
`The extension of the leads to the extremities can only be acn~eved by increas·lrig
`the package width, due to the minimum limits on tracks and spaces. Reduction cf
`spaces from the DIL 0.1"
`to the so 0.05" and 0.03" or even 0.02" means a very
`lead with very thin material and this brings a problem of
`small width
`lead
`stability. Lead counts over 40 are rare for so. For higher lead counts all rour
`sides of
`the package are used. Packages of this type are available
`in both
`hermetic and plastic versions.
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`No hermetic SOT/SO are available. Where hermeticity is a requirement other means
`must be found to satisfy it. Mounting an assembly
`in an hermetic enclosure does
`not necessarily provide a solution with anything other than naked dice, because
`the plastic itself in the so is considered as a device-degrading aaterial and
`only cavity packages are acceptable.
`
`The Leadless Ceramic Chip carrier (LCCC) has evolved as a high density, high
`lead count, hermetic package. With no compliant leads to relieve the stress,
`failure of the soldered joints is a problem. Good heat aanagement is needed
`to
`reduce thermal gradients along the soldered joints. This problem is much worse
`for LCCCs on PCBs as the thermal conduction of FR4 is far lower than ceramic and
`the differential expansion higher. One thing that cannot be miniaturised
`is
`power dissipation. This has resulted in some complex means of heat extraction
`from
`the package, with the use of metal heat paths integral to the package on
`the substrate.
`In extreme cases the ceramic substrate has been abandoned
`in
`favour of metal/organic laminated substrate with thermal expansion matched
`to
`ceramic with forced cooling. In less extreme cases, the solution is to avoid the
`solid joint and provide some compliance by having leads, albeit short ones. The
`LCCC can have leads added but this worsens the thermal path and is not usual.
`Plastic packages are more suited to having leads and two main types of plastic
`chip carriers have evolved - "Gull Wing" and "J Lead". Gull Wing is the old Flat
`Pack. Leads come from the side of the package and are given a slight crank so
`they sit in a plane,
`leaving the body of the package
`just clear of
`the
`substrate. J Lead has the lead bent at a right angle as it exits the package and
`then bent through a curve under the package to make the J shape. Gull Wing takes
`more area but
`the Joints are visible and can be made by a variety of means. The
`Lead package is compact but has limited means by which it can be soldered.
`Lead counts of chip carriers can go into the hundreds.
`Increasing complexity Of
`electronics
`is stated as leading to !Cs having ever higher lead counts. Some
`predictions discuss lead counts up to 1000s. This implies higher interconnection
`density between dice. At this level wire bonding will pose problems and other
`methods
`to access
`the silicon need to be considered. How
`these will be
`implemented on
`the die is somewhat speculative but the use of output pads
`in
`places not restricted to the edges of the die is one possibility.
`
`FH_p Chips
`
`the
`The semiconductor industry has sought ways to include the terminations into
`wafer processing stages. The Bump Chip or Flip Chip transfers a
`substantial
`amount of the packaging onto the die. By plating on to the pads of a die whilst
`still on the w~fer a series of bumps can be produced. These can be hard or soft
`material,
`in
`the latter case lead or lead/tin. After separation
`the die
`is
`inverted to place the bumps on to the substrate metallisation. By using suitable
`alloys and control of the temperature,
`the bumps may be subject to controlled
`:-.,llapse ensuring
`that each and every bump will contact
`the
`substrate
`metallisation. This technique, problematical as it may seem, has been applied to
`die having bumps placed all over the surface. A problem with this method is that
`substrate metallisation patterns need to be made to the same precision as
`the
`metallising ct' the wafer. This could exclude thick film and limit the use of
`bump;od
`:L·.·e •,-
`•i-,e :;1~b':ractive, photo-processed substrates such as fine
`line
`PCBs and thin f~lm. Flip Chips use th~ same wafer as wire bonded dice for most
`of
`the processinq but there is a difference in the final metallisation
`layer,
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`the bump die needing a barrier layer in addition to the standard aluminium. A
`commercial problem with bumped dice is that only dice are available
`that
`the
`semiconductor manufacturer has elected to process this way, with
`no general
`availability. However, the in-house use of this technology has become widespread
`in a number of computer manufacturing companies.
`
`Beam Leads
`
`For microwave, where short, well defined terminations are needed, another form
`of wafer processing can be used,
`this is Beam Lead. Small extensions
`to
`the
`electrodes are grown by plating gold over an enhanced passivation layer. Instead
`of separation by cutting,
`the dice are etched out from the reverse side of
`the
`wafer and by so doing leave the gold extensions as small cantilevers which are
`then thermo-compression bonded to the substrate. Dedicated wafer processing
`is
`needed at all stages. Originally proposed as a general method any
`theoretical
`advantages
`in reliability due to the added passivation and cost savings
`in
`assembly are negated by the considerable extra wafer processing and poor silicon
`utilisation. This has
`left
`the beam lead as a
`special product where
`low
`inductance connections are the paramount consideration. With the applications
`mainly in the microwave area,
`the process has been adapted to other materials,
`such as GaAs.
`
`is Tape
`A major branch of device packaging technology stemming from bump dice
`Automated Bonding
`(TAB}. Continuous tape of 35mm film format is used, with
`a
`photographically defined metallised pattern on to which the dice are bonded, the
`metallisation
`is extended from the die area to make connections to
`the
`larger
`substrate dimensions and by
`this means the need
`for very
`fine substrate
`geometries
`is
`reduced. The die bonding -
`inner lead bonding
`is automated,
`hence the name. The metal connections can be very fine and high lead counts can
`be accommodated. The devices are kept on reels for automatic mounting on to the
`substrate, which is done by punching the device from the tape and at
`the
`same
`time pressure bonding the extended metallisation to the substrate pattern. TAB
`has been used
`to mount devices in standard DIL packages,
`the aim being
`to
`eliminate the wire bonding process and costs.
`
`the
`facilitate the use of TAB on nonbumped die, an alternative of bumping
`To
`tape can be used. With the constraints on die metallisation, the bonding is more
`difficult and whilst development continues,
`the commercial use is still very
`limited.
`
`is now
`is being adapted to more conventional assembly technologies and
`TAB
`available in a form for direct mounting on to PCB by automated SM placement and
`re-flow soldering processes.
`
`Interconnection of high lead count semiconductor devices can be done using are
`two main substrate technologies. These are:-
`
`Medium track density with many layers. PCB - Multilayer, Thick Film.
`
`High track density with few layers. PCB - Double Sided, Thin Film.
`
`To achieve high density, PCB through hole technology uses multilayer, as organic
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`materials can easily be drilled and layers laminated. Through hole plating both
`interconnects
`the
`layers and provides the interface for mounting
`the
`leaded
`components.
`
`to
`PCBs can be processed to give very fine geometries. This is better suited
`but
`double sided PCBs
`than multilayers as PCB materials exhibit small
`significant dimensional changes during processing. Where inserted devices and
`components are us~~ " limitation on track density is imposed by the hole sizes
`and solder
`lands. Directly bonded dice or
`the use of SH
`removes
`this
`resti-ictL:m. Thick film processing can lay down dielectric layers and build up a
`mul t ilaye: s•.nicture by successive layers of conductive and nonconductive films.
`~·3.::~::.. ... ::::~i.c rt·__.ltilayer processes for ~hi.r.. fi:'..m have been developed but, being
`!'b
`~~o~,"'.'graph~:::al::.y ;:·2cessed it can \.:u.ve very fine lines.
`
`Wt-;.et.her mu::.+_i~ayer or fine line will dominate is a matter of speculation. Device
`paclrnges ha·ve been developed fo:· bc~h. Multilayer PCB is widely used and with
`through hole plating making contact with one or more of the
`layers
`is well
`suited to inserted devices. To accommodate this the Pin Grid Array package (PGA)
`r-.as been developed.
`In the PGA pins are arranged on a 0.1 matrix around the die
`which sits
`in a cavity. The wire bonding pads are extended by metallisation
`to the pins. Both ceramic and plastic types are available.
`It is also possible
`to have
`the die up or down in the package. This enables heat sinking
`to be
`applied. This type of package has several advantages:
`it can be tested using a
`Z.erc
`Insertion Force socket and it interfaces with the through-hole PCB, which
`sti 11
`represents
`the major method of
`interconnection
`today.
`It
`is very
`difficult.
`:f not impossible,
`to rework,
`it can be used with a socket but the
`insertion and withdrawal forces are very high - measured in several kilogrammes.
`It
`is almost impossible to use with film circuits or high definition PCB
`(in
`contrast to the PLCC whict1 can be socketed for TH use).
`
`CONCLUSIONS
`
`future of interconnection for VLSI is in the balance between organic PCBs
`The
`and ceramic substrates.
`In the end the technical superiority of ceramic may win
`out, but the semiconductor manufacturers are supporting PCB. The secret is not
`in solving today's problems tomorrow but in anticipating tomorrow's problems and
`solving
`them
`today. High lead counts cause us to question the philosophy of
`having a
`single die with so many I/Os. Attention must be given
`to systems
`integration by more effective means than high interconnection density interfaces
`between devices.
`In contrast, we can see
`that higher
`levels of silicon
`integration will lead to higher levels of on-silicon interconnection and
`less
`between
`(fewerj devices with lower lead counts. The economics and practical
`limitations of using so much silicon area only as a means to connect
`to other
`silicon must drive towards the goal of full silicon solutions.
`In the meantime,
`until
`the tools and techniques are refined we must use off-silicon methods
`for
`hiqh
`ir.terconnection density as well. Rather than invent more and more exotic
`device pac~aging and interconnection, effort needs to be put into examining the
`lar9er problem of designing them, out of the system. An important consideration
`is
`the increasing use of custom res, where the initiative has now passed back
`from
`the semiconductor house to the systems designer. With hybrids the system
`designer has always played an important role in the decisions on manufacturing
`options. The use of customised silicon in association with appropriate assembly
`methods and production techniques to realise a "best" overall solution is much
`mo1c, Gf a prac:tical possibility now that the design function is in one place.
`The packaging and interconnection sector of the electronics
`industry
`together
`with the use of good production and management methods are the essential support
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`activities of systems and silicon design. Much can still be done by
`the
`to
`integrating
`the
`thoughts and technologies of all the activities to provide
`a
`unified concept applicable to the future of electronics. Custom Silicon is
`the
`catalyst.
`The complexities and costs of
`semiconductor pacKaging gives
`emphasis
`to the need for designers in all branches of electronics to accept
`to
`concepts and acquire the sKills of designing on the silicon
`itself. By
`this
`means
`they will not only achieve better products in terms of performance and
`cost but will once again become masters of their own destiny.
`
`413
`
`IEEE/ISHM ~O IEMT Symposium - Italy
`
`9
`
`