US008063674B2
`
`United States Patent
`
`(12)
`(10) Patent No.:
`US 8,063,674 B2
`
`Kwon et al.
`(45) Date of Patent:
`Nov. 22, 2011
`
`(54) MULTIPLE SUPPLY-VOLTAGE
`POWER-UP/DOWN DETECTORS
`
`(75)
`
`.
`.
`.
`Inventors: Chang K1 Kwon, San Diego, CA (US),
`Vlvek Mohan, San D1680, CA (US)
`
`73 A '
`:
`UALCOMM I
`t d S
`)
`SSlgnee Siege CA (Us) “corpora e ’
`,
`
`(
`
`an
`
`( * ) Notice:
`
`Subject. to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154 b b 165 da 5.
`(
`) y
`y
`
`PP
`21 A 1. No.: 12/365,559
`
`2002/0163364 A1
`11/2002 Majcherczak
`2006/0044027 A1 *
`3/2006 Chen ............................. 327/ 143
`2006/0103437 A1
`5/2006 Kang
`2007/0030039 A1
`2/2007 Chen
`2008/0100341 A1*
`5/2008 Kim ................................ 326/63
`
`2008/0218223 A1*
`9/2008
`.. 327/142
`
`2009/0027087 A1 *
`1/2009 Sukup et a1.
`.................... 327/72
`FOREIGN PATENT DOCUMENTS
`2007091211
`8/2007
`
`WO
`
`OTHER PUBLICATIONS
`
`International Search Report and Written Opinion7PCT/US2010/
`023081, International Search Authority7European Patent Office7
`Aug. 5, 2010.
`
`(22)
`
`Filed:
`
`Feb. 4, 2009
`
`* cited by examiner
`
`(65)
`
`Prior Publication Data
`
`(51)
`
`Aug. 5’ 2010
`
`US 2010/0194200 A1
`Int Cl
`(2006.01)
`H03L 7/00
`(2006.01)
`H03L 5/00
`(2006.01)
`H03K 5/153
`(2006.01)
`H03K 19/094
`(52) US. Cl.
`............. 327/143. 3271/72. 327/333. 326/68
`(58) Field of Classification Search .................... 326/82
`326/83 86 87 93 112 119. 327333 108
`See application file for complete search history ’
`.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,781,051 A * 11/1988 Schultese a1.
`5,130,569 A
`7/1992 Glica
`5,495,453 A *
`2/1996 Wojciechowski
`et a1.
`........................ 365/185.18
`
`3/1998 Roohparvar
`....... 327/81
`
`. 327/143
`7/1998 Sandhu .....
`6/2003 Lim ................................ 327/77
`11/2003 Matthews
`5/2005 Kursun et a1.
`8/2007 Kwon et a1.
`
`5,723,990 A *
`5,781,051 A *
`6,577,166 B2*
`6,646,844 B1
`6,900,666 B2*
`7,253,655 B2
`
`................. 72/247
`
`................... 326/95
`
`Primary Examiner 7 Shawki Ismail
`Assistant Examiner 7 Dylan White
`(74) Attorney, Agent, or Firm 7 Sam Talpalatsky; Nicholas
`J. Pauley; Jonathan T. Velasco
`57
`ABSTRACT
`
`)
`(
`A multiple supply voltage device includes an input/output
`(l/O) network operative at a first supply voltage, a core net-
`work coupled to the I/O network and operative at a second
`supply Whages and a Power'on'contml
`(POC) network
`coupled to the I/O network and the core network. The POC
`network is configured to transmit a POC signal to the l/O
`network and includes an adjustable current power up/down
`detector configured to detect a power state of the core net-
`work. The POC network also includes processing circuitry
`coupled to the adjustable current power up/down detector and
`configured to process the power state into the POC signal, and
`one or more feedback circuits. For reducing the leakage cur-
`rent while also improving the power-up/down detection
`speed, the feedback circuit(s) are coupled to the adjustable
`current power up/down detector and configured to provide
`feedback signals to adjust a current capacity ofthe adjustable
`current power up/down detector.
`
`22 Claims, 8 Drawing Sheets
`
`40
`
`/
`
`
`
`Vss
`
`Power U/D
`Detector
`306
`
`|
`|
`|
`'
`
`Signal
`Processor
`308
`
`I
`|
`|
`.
`
`POC
`
`Output
`Buffer
`309
`
`APPLE 1001
`
`APPLE 1001
`
`1
`
`

`

`U.S. Patent
`
`m.N
`
`m,
`
`00Mm
`
`US 8,063,674 B2
`
`m$385Oh8Al00m
`
`S
`
`58:0_Farm
`mmfim_QE<
`
`N32:
`
`A52”SEA:
`
`H.05
`
`SBBDD
`
`of
`
`Q5333 O=>
`
`bagsmo:
`
`E:
`
`Ugoo>
`
`080
`
`Egon
`
`bmmsm
`
`m2
`
`2
`
`

`

`U.S. Patent
`
`NOV. 22, 2011
`
`Sheet 2 of 8
`
`US 8,063,674 B2
`
`om
`
`\
`
`m2:
`
`mzfiw
`
`3:333mEgonOh
`
`m3bgmsw$33800
`
`
`
`DOA
`
`>64
`
`A52moan:
`
`N.05
`
`3
`
`

`

`U.S. Patent
`
`Nov. 22, 2011
`
`Sheet 3 of8
`
`US 8,063,674 B2
`
`302
`
`1/0
`
`Network
`
`POC
`
`Network
`
`Level
`
`Shifters
`
`
`
`Core
`
`Network
`
`FIG. 3A
`
`4
`
`

`

`U.S. Patent
`
`NOV. 22, 2011
`
`Sheet 4 of 8
`
`US 8,063,674 B2
`
`#538ZO:
`
`SpooaoQ
`
`Q55&8
`
`€956Z#23me
`
`5
`
`

`

`U.S. Patent
`
`Nov. 22, 2011
`
`Sheet 5 of8
`
`US 8,063,674 B2
`
`POC
`
`Vss
`
`Power U/D
`Detector
`306
`
`I
`|
`|
`.
`
`|
`|
`|
`'
`
`Signal
`Processor
`308
`
`FIG. 4
`
`Output
`Buffer
`309
`
`6
`
`

`

`U.S. Patent
`
`Nov. 22, 2011
`
`Sheet 6 of8
`
`US 8,063,674 B2
`
`POC
`
`VSS
`
`Power U/D
`Detector
`306
`
`I
`
`:
`|
`
`Output
`Buffer
`309
`
`|
`
`:
`|
`
`Signal
`Processor
`308
`
`FIG. 5
`
`7
`
`

`

`U.S. Patent
`
`Nov. 22, 2011
`
`Sheet 7 of8
`
`US 8,063,674 B2
`
`POC
`
`Vss
`
`Power U/D
`Detector
`306
`
`|
`I
`I
`'
`
`Output
`Buffer
`309
`
`|
`I
`I
`'
`
`Signal
`Processor
`308
`
`FIG. 6
`
`8
`
`

`

`U.S. Patent
`
`Nov. 22, 2011
`
`Sheet 8 of8
`
`US 8,063,674 B2
`
`Detect a power-on of a second supply voltage while a
`first supply voltage is already on.
`
`700
`
`Decrease a current capacity of a power on/off detector of
`the FCC network responsive to the power-on detection.
`
`701
`
`Detect a power—down of the second supply voltage
`while the first supply voltage is on.
`
`702
`
`703
`
`Increase the current capacity of the power on/off detector
`responsive to the power-down detection.
`
`FIG. 7
`
`9
`
`

`

`US 8,063,674 B2
`
`2
`
`1
`MULTIPLE SUPPLY-VOLTAGE
`POWER-UP/DOWN DETECTORS
`
`TECHNICAL FIELD
`
`The present disclosure is related, in general, to integrated
`circuit devices and, more particularly, to power up/down
`detectors for multiple supply voltages devices.
`
`BACKGROUND
`
`As technology has advanced there has been an increased
`ability to include more and more devices and components
`within integrated circuits. Semiconductor fabrication tech-
`niques have allowed these embedded devices to become
`smaller and have lower voltage requirements, while still oper-
`ating at high-speeds. However, because these new integrated
`devices often interface with older technology devices or
`legacy products, input/output (I/O) circuits within the inte-
`grated circuit have remained at higher operating voltages to
`interface with the higher voltage requirements of these older
`systems. Therefore, many newer integrated circuit devices
`include dual power supplies: one lower-voltage power supply
`for the internally operating or core applications, and a second
`higher-voltage power supply for the I/O circuits and devices.
`Core devices and applications communicate with opera-
`tions outside of the integrated component through the I/O
`devices. In order to facilitate communication between the
`
`core and I/O devices, level shifters are employed. Because the
`I/O devices are connected to the core devices through level
`shifters, problems may occur when the core devices are pow-
`ered-down. Powering down or power collapsing is a common
`technique used to save power when no device operations are
`pending or in progress. For example, if the core network is
`power collapsed, it is possible that the level shifters, whether
`through stray currents or the like, could send a signal to the
`I/O devices for transmission. The I/O devices assume that the
`core devices have initiated this communication, and will,
`therefore, transmit the erroneous signal into the external envi-
`ronment.
`It has been found useful to have the I/O devices in a known
`
`state when the core networks are powered down. In order to
`guarantee these known states, solutions have included the
`addition of hardware or software for managing additional
`external signals to control the I/O circuitry. By using these
`external signals, the I/O circuitry can be controlled (e.g.,
`placed in a known state) whenever the core power is col-
`lapsed. However, whether implementing this extemal signal
`management system using hardware or software, a consider-
`able amount of delay is added to the operation of the inte-
`grated device. Although hardware is slightly faster than soft-
`ware controls, hardware solutions may have problems caused
`by significant additional power leakage on the I/O device
`side.
`
`One hardware solution currently in use provides power-up/
`down detectors to generate a power-on/off-control (POC)
`signal internally. The POC signal instructs the I/O devices
`when the core devices are shut down. FIG. 1 is a circuit
`diagram illustrating standard POC system 10 for multiple
`supply voltage devices. POC system 10 is made up of three
`functional blocks: power-up/down detector 100,
`signal
`amplifier 101, and output stage 102. Power-up/down detector
`100 has PMOS transistor M1 and NMOS transistors M2-M3.
`
`The gate terminals for each of M1-M3 are connected to core
`power supply 103, Vcore. When core power supply 103 is
`power collapsed, M2 and M3 are switched off while M1 is
`switched on, pulling up the input node to amplifier 105 to
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`10
`
`VI/O, i.e., I/O power supply 104. A “high” signal is input into
`amplifier 105 which inverts the output to a “low” signal. In
`output stage 102, the low signal from amplifier 105 is pro-
`cessed in output buffer 106 and again inverted to a high signal
`for POC 107. The high signal for POC 107 is transmitted to
`the I/O circuitry indicating that core power supply 103 has
`been shut down.
`
`When core power supply 103, Vcore, is on, M1 becomes
`very weak and M2 and M3 both switch strongly on, pulling
`the input node to amplifier 105 to V55, i.e., core power supply
`103. V55 is considered the logical low signal. Therefore,
`amplifier 105 inverts it to a high signal which is then pro-
`cessed in output buffer 106 and inverted again to a low signal.
`This signal detection process operates acceptably when either
`I/O power supply 104 is on and core power supply 103 is
`power collapsed or when core power supply 103 is powered-
`up before I/O power supply 104 is powered-up. However,
`when I/O power supply 104 is powered-up before core power
`supply 103 powers-up, substantial current leakage may occur
`in the power up/down detector 100 or in the POC 10.
`In the situation where I/O power supply 104 is on and core
`power supply 103 is off, M1 is switched on with M2 and M3
`switched off. When core power supply 103 is then powered
`up, M2 and M3 switch 011, and M1 becomes very weak.
`However, before M1 can switch completely off, there is a
`period in which all three transistors within power up/down
`detector 100 are on. Thus, a virtual short is created to ground
`causing a significant amount of current to flow from I/O
`power supply 104 to ground. This “glitch” current consumes
`unnecessary power.
`In order to reduce this stray power consumption, one solu-
`tion may be adopted to decrease the sizes of transistors
`M1-M3. By reducing the size ofM1-M3, the actual amount of
`current that can pass through the transistors is physically
`limited. However, because the transistors are now smaller,
`their switching speeds are also reduced. The reduced switch-
`ing speed translates into less sensitivity in detecting power-
`up/down ofcore supply voltage 103 or longer processing time
`for power-up/down events.
`FIG. 2 is an illustration of diagram 20 presenting the signal
`interactions in POC circuit 10 of FIG. 1. Diagram 20 includes
`power supply diagram 21 and POC diagram 22. As I/O power
`supply 104 is powered up, there is a steady increase until it
`reaches VI/O. POC 107 follows I/O power supply 104 as it
`powers up to reach the high level. Similarly, when I/O power
`supply 104 maintains steady at VI/O at time 200, POC 107
`remains steady at the high signal. When core power supply
`103 begins to power on at time 201 power up/down detector
`100 (FIG. 1) takes a little time to actually detect this new
`power level. Once detected, at time 202, POC 107 is switched
`to the low value. POC 107 should, thereafter, remain at the
`low level until core power supply 103 is power collapsed,
`between times 203 and 205. Again, because power up/down
`detector 100 (FIG. 1) takes a little time to actually detect the
`new power level, POC 107 remains in the low state until time
`204, when the powering down is actually detected by power
`up/down detector 100. This low state time, between time 202
`and 204 is referred to as the normal operation region. Once
`core power supply 103 is completely offorpower collapsed at
`time 205, the input to amplifier 105 (FIG. 1) is again pulled up
`to the high signal. POC 107 will then follow I/O power supply
`104 as it also powers down between times 206 and 207.
`The leakage current between I/O power supply 104 and
`ground can be lessened because of the smaller transistor size.
`Thus, during the time between times 201 and 205 any leakage
`that occurs is reduced. However, this reduced leakage comes
`at the price of faster detection. If POC circuit 10 may include
`
`10
`
`

`

`US 8,063,674 B2
`
`3
`the lower-threshold or bigger transistors, switching/detecting
`times would be faster. For example, as core power supply 103
`begins to power up at time 201, the lower-threshold or bigger
`transistors of power up/down detector 100 would detect the
`power-up at time 208, instead of time 202. Moreover when
`core power supply 103 begins powering down at time 203, the
`power up/down detector 100 would detect the power-down at
`time 209, instead of time 204. This increase may be repre-
`sented by the difference between the time periods oftime 202
`to 204 vs. time 208 to 209. Therefore, the conventional solu-
`tions still have problems with leakage and switching times.
`
`SUMMARY
`
`Various representative embodiments of the disclosure
`relate to integrated devices having multiple supply voltages.
`Further representative embodiments ofthe present disclosure
`relate to methods for reducing power consumption in a power
`on/off control (POC) network of a multiple supply voltage
`device. Additional representative embodiments ofthe present
`disclosure relate to systems for reducing power consumption
`in a POC network of a multiple supply voltage device.
`A multiple supply voltage device includes a core network
`operative at a first supply voltage and a control network
`coupled to the core network. The control network is config-
`ured to transmit a control signal. The control network
`includes an up/down (up/down) detector configured to detect
`a power state ofthe core network. The control network further
`includes processing circuitry coupled to the up/down detector
`and is configured to generate the control signal based on the
`power state. The control network further includes one or more
`feedback circuits coupled to the up/down detector. The one or
`more feedback circuits are configured to provide feedback
`signals to adjust a current capacity of said up/down detector.
`A method for reducing power consumption in a power
`on/off control (POC) network of a multiple supply voltage
`device includes detecting a power-on of a second supply
`voltage while a first supply voltage is already on, decreasing
`a current capacity of a power on/off detector of the FCC
`network in response to the power-on detection, detecting a
`power-down of the second supply voltage while the first
`supply voltage is on, and increasing the current capacity ofthe
`power on/off detector in response to the power-down detec-
`tion.
`
`A system for reducing power consumption in a power
`on/off control (POC) network of a multiple supply voltage
`device includes a means for detecting a power-on of a second
`supply voltage while a first supply voltage is already on. The
`system further includes means for decreasing a current capac-
`ity of a power on/off detector of the FCC network responsive
`to the power-on detection. The system further includes means
`for detecting a power-down of the second supply voltage
`while the first supply voltage is on, and means for increasing
`the current capacity ofthe power on/offdetector responsive to
`the power-down detection.
`The foregoing has outlined rather broadly the features and
`technical advantages ofthe present embodiments in order that
`the detailed description of the disclosure that follows may be
`better understood. Additional features and advantages of the
`embodiments will be described hereinafter which form the
`
`subject of the claims of the disclosure. It should be appreci-
`ated by those skilled in the art that the conception and specific
`embodiments disclosed may be readily utilized as a basis for
`modifying or designing other structures for carrying out the
`same purposes of the present disclosure. It should also be
`realized by those skilled in the art that such equivalent con-
`structions do not depart from the spirit and scope of the
`
`5
`
`10
`
`15
`
`4
`
`disclosure as set forth in the appended claims. The novel
`features which are believed to be characteristic of the disclo-
`
`sure, both as to its organization and method of operation,
`together with further objects and advantages will be better
`understood from the following description when considered
`in connection with the accompanying figures. It is to be
`expressly understood, however, that each of the figures is
`provided for the purpose of illustration and description only
`and is not intended as a definition of the limits of the present
`disclosure.
`
`BRIEF DESCRIPTION OF TIIE DRAWINGS
`
`For a more complete understanding of the present disclo-
`sure, reference is now made to the following descriptions
`taken in conjunction with the accompanying drawings.
`FIG. 1 is a circuit diagram illustrating a conventional POC
`system for multiple supply voltage devices.
`FIG. 2 is an illustration of a diagram presenting the signal
`interactions in the FCC circuit of FIG. 1.
`
`FIG. 3A is a block diagram illustrating an integrated circuit
`(IC) device having a power on control (POC) network con-
`figured according to the teachings of the present disclosure.
`FIG. 3B is a block diagram illustrating a POC network
`configured according to the teachings of the present disclo-
`sure.
`
`25
`
`FIG. 4 is a circuit diagram illustrating another POC net-
`work configured according to the teachings of the present
`disclosure.
`
`30
`
`FIG. 5 is a circuit diagram illustrating a further POC net-
`work configured according to the teachings of the present
`disclosure.
`
`35
`
`FIG. 6 is a circuit diagram illustrating still another POC
`network configured according to the teachings of the present
`disclosure.
`
`FIG. 7 is a flowchart illustrating process blocks for imple-
`menting one embodiment according to the teachings of the
`present disclosure.
`
`DETAILED DESCRIPTION
`
`Turning now to FIG. 3A, a block diagram is presented
`illustrating an integrated circuit (IC) device 30 having a
`power on control (POC) network 305 configured according to
`one embodiment of the present disclosure. The IC device 30
`is an integrated circuit that includes embedded components
`powered by multiple power supplies, such as the VI/O 300 and
`the Vcore 301. The VH0 300 and the Vcore 301 supply several
`different voltage level power supplies to different compo-
`nents and networks within the IC device 30. Two such embed-
`ded networks are the I/O network 302 and the core network
`
`303. The I/O network 302 operates at a voltage level provided
`by the VI/O 300. The Core network 303 operates at a voltage
`level provided by the V60", 301, which is usually a lower
`voltage than that provided by the VI/O 300. Because the I/O
`network 302 and the core network 303 operate at different
`voltages, they are coupled together through level shifters 304
`for communication. The level shifters 304 essentially shift the
`voltage levels of any communications that occur between the
`I/O network 302 and the core network 303.
`POC network 305 senses the status ofthe core network 303
`
`and transmits a POC signal to the I/O network 302 and level
`shifters 304. The FCC signal either turns them on or off. This
`prevents stray signals received by the I/O network 302 from
`being mistakenly transmitted to devices or components exter-
`nal to the IC device 30.
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`11
`
`11
`
`

`

`US 8,063,674 B2
`
`5
`FIG. 3B is a block diagram illustrating a POC network 305
`configured according to one embodiment of the present dis-
`closure. The POC network 305 includes a power up/down
`detector 306, processing circuitry 307, and feedback network
`310. The processing circuitry 307 is made up of a signal
`processor 308 and an output buffer 309. When the VI/O 300 is
`on and the Vcore 301 is off, the power up/down detector 306
`provides a detection signal to the signal processor 308, which
`processes the detection signal and transmits the processed
`signal to the output buffer 309. The output buffer 309 then
`conditions the processed signal into a POC signal 311, which
`is then transmitted to an I/O network 302. Along the way, a
`feedback network 310 receives feedback from the signal pro-
`cessor 308 and feeds that signal back to the power up/down
`detector 306. The power up/down detector 306 uses the feed-
`back signal to adjust its current capacity. While the Vcore 301
`is in an off or low state, the feedback signal allows the power
`up/down detector 306 to select a maximum current capacity.
`This maximum current capacity state makes the power
`up/down detector 306 more sensitive to detecting when the
`core
`V
`3 01 either powers -up or powers -down, or both, depend-
`ing on the circuit configuration ofthe power up/down detector
`306.
`
`When the V60”, 301 powers-up while the VI/O 300 is on, the
`power up/down detector 306 detects the power-up and
`changes the value of the detection signal transmitted to the
`signal processor 308. The process detection signal is then
`conditioned by the output buffer 309 into the changed POC
`signal 311 and transmitted to the I/O network 302. With the
`changing signals being processed through the signal process-
`ing circuitry 307, the feedback network 310 receives the new
`feedback signal that, when input into power the up/down
`detector 306, causes the current capacity within the power
`up/down detector 306 to decrease. This decrease in current
`capacity will limit and reduce the amount of leakage current
`that may be dissipated through the power up/down detector
`core
`306 because of its connections to the VI/O 300 and the V
`301.
`
`FIG. 4 is a circuit diagram illustrating a POC network 40
`configured according to one embodiment of the present dis-
`closure. The POC network 40 has similar processing regions
`as the FCC network 305 (FIGS. 3A and 3B), i.e., a power
`up/down detector 306, a signal processor 308, an output
`buffer 3 09, and a feedback network 3 10. The FCC network 40
`also generates a POC signal 311 and is coupled to aVI/O 300
`and a V60”, 301. As shown in the embodiment illustrated in
`FIG. 4, the power up/down detector 306 comprises multiple
`transistors M4-M7 coupled in series together. Each gate ofthe
`transistors M4-M7 is coupled to the Vcore 301, while the
`source terminal of the transistor M4 is coupled to the VI/O
`300. The transistors M4 and M5 are p-type transistors and the
`transistors M6 and M7 are n-type transistors. Therefore,
`when the V60”, 301 is off, i.e., in a low state, the transistors M4
`and M5 are switched on, while the transistors M6 and M7 are
`switched off.
`
`In contrast, when the Vcore 301 is on, i.e., in a high state,
`transistors M4 and M5 become very weak while transistors
`M6 and M7 are strongly switched on. M6 and M7 turning on
`pulls the voltage of the input to inverting amplifier to V55,
`which is a logical low signal compared with VI/O. VSS is
`designed as the logical low signal and may comprise ground,
`0 V, or some other selected voltage level that represents the
`logical low symbol. Thus, when the Vcore 301 is off, the
`transistors M4 and M5 pull up the voltage level at the input to
`an inverting amplifier 400 to the V[/0 3 00. Therefore, the input
`to the inverting amplifier 400 is high when theV
`301 is off
`and low when the V60”, 301 is on. The inverting amplifier 400
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`then amplifies and inverts the detection signal before trans-
`mitting it to the inverting buffer 401 for conditioning and
`inverting for the FCC signal 311.
`The feedback network 310 comprises a transistor M8 con-
`nected in parallel to the transistor M4. The transistor M8 is
`also configured as a p-type transistor, such that when the
`feedback signal from the inverting amplifier 400 is high, the
`transistor M8 is switched off, and when the feed back signal
`is low, the transistor M8 is switched on. Thus, when the Vcore
`301 is off, producing a high detection signal, the inverting
`amplifier 400 inverts that signal to a logic low which causes
`the transistor M8 to switch on. As the V60”, 301 is powered-
`on, the detection signal changes to a logic low, which changes
`the feedback signal from the inverting amplifier 400 to a logic
`high, which, in turn, turns the transistor M8 off. While the
`transistor M8 is off, the power up/down detector 306 has a
`decreased current capacity,
`i.e., smaller current will flow
`through the transistor M8 because ofthe amplified low signal.
`The voltage level caused by the V60”, 301 on the gate termi-
`nals of M4 and M5 could in some glitch or stray signal
`situations, cause leakage through M4 and M5. Because the
`feedback signal for the transistor M8 is received from the
`inverting amplifier 400, when the Vcore 301 powers-down, the
`feedback signal will switch quickly from a logic high to a
`logic low, which will then switch the transistor M8 on. Thus,
`in the circuit configuration depicted in FIG. 4, the power
`up/down detector 40 will detect the V60”, 301 powering down
`more quickly than the existing POC networks.
`FIG. 5 is a circuit diagram illustrating a POC network 50
`configured according to one embodiment of the present dis-
`closure. The POC network 50 comprises multiple transistors
`M4 -M7 in the power up/down detector 306 coupled together
`in a fashion similar to the FCC network 40 (FIG. 4) with each
`gate coupled to a V60”, 301, and the source terminal of the
`transistor M4 coupled to a VI/O 300. A signal processor 308
`comprises an inverting amplifier 400, and an output buffer
`309 includes an inverting buffer 401. The FCC network 50
`generates a POC signal 311, which will be transmitted to the
`I/O network to which the FCC network 50 is coupled. In the
`FCC network 50, a feedback network 310 is configured with
`the transistors M9 and M10 coupled in parallel with the
`transistor M7. The transistors M6, M7, M0, are the same type,
`n-type or can be low-threshold n-type transistors to speed up
`the power-on detection. The transistor M9 receives its feed-
`back signal from the output of the inverting buffer 401, while
`the gate of the transistor M10 is connected to the V60”, 301.
`In operation, when the VI/O 300 is on and the Vcore 301 is
`off, the inverting amplifier 400 receives a logic high signal by
`Virtue ofthe VI/O 300, which, when amplified and inverted by
`the inverting amplifier 400 and then conditioned and inverted
`by the inverting buffer 401, provides a logic high feedback
`signal. This high signal would normally switch M9 in the
`feedback network 310 on. However, because M6, M7, and
`M10 are all off, there is no channel formation within the
`transistor M9 to switch it 011. When the V60”, 301 powers on,
`M4 and M5 become very weak, while M6, M7, and M10
`switch on, which immediately causes M9 to switch on
`because its gate is already connected to a logic high input. M6
`and M7 switching on pulls the input to the inverting amplifier
`400 down to a logical low signal, i.e., VSS. The low detection
`signal input to the inverting amplifier 400 is amplified and
`inverted and then conditioned and inverted again at the invert-
`ing buffer 401. Once the inverting buffer 401 outputs a low
`signal, the feedback of that low to the transistor M9 will
`switch M9 off, which, because switching M9 off stops the
`channel formation in the transistor M10, causes the transistor
`M10 to also switch off. Thus, the configuration of the FCC
`
`12
`
`12
`
`

`

`US 8,063,674 B2
`
`7
`network 50, as illustrated in FIG. 5, operates to detect the
`Vcore 301 powering on faster than the existing POC networks,
`while still reducing the amount of leakage current while the
`V60”, 301 is on. The feedback signal used by the transistor M9
`allows the power up/down detector 306 to adjust its current
`capacity, which reduces the leakage current at the same time
`as the detection speed is improved.
`FIG. 6 is a circuit diagram illustrating a POC network 60
`configured according to one embodiment of the present dis-
`closure. The POC network 60 includes a feedback network
`
`310 configured according to the circuit arrangements of both
`the FCC network 40 @IG. 4) and the FCC network 50 (FIG.
`5). As such, multiple transistors M4-M7 make up the power
`up/down detector 306. The feedback network 310 includes
`transistor M8, coupled in parallel to the transistor M4, and the
`transistors M9 and M10, coupled in parallel with the transis-
`tor M7. The detection signal from the power up/down detec-
`tor 306 provides input to an inverting amplifier 400 of a signal
`processor 308, which amplifies and inverts the detection sig-
`nal for input to an inverting buffer 401 ofan output buffer 309.
`The conditioned and inverted POC signal 311 is then trans-
`mitted to the appropriate I/O and level shifter network of the
`system. The feedback transistor M8 obtains its feedback sig-
`nal from the output of the inverting amplifier 400, while the
`feedback transistor M9 obtains its feedback signal from the
`output of the inverting buffer 401. Using these feedback sig-
`nals, as described with respect to the FCC network 40 (FIG.
`4) and the FCC network 50 (FIG. 5), the FCC network 60 is
`able to increase the speed that the Vcore 301 is quickly
`detected both in the power-on and power-off stages. At the
`same time, because the feedback network 310 provides the
`capability of the FCC network 60 to adjust the current capac-
`ity of the power up/down detector 306, the unwanted leakage
`current can also be reduced during the V60”, 301 normal
`operation periods.
`It should be noted that each of the embodiments described
`
`with respect to the FCC network 40 (FIG. 4), the FCC net-
`work 50 (FIG. 5), and the FCC network 60 (FIG. 6) has its
`own advantages. For example, the FCC network 50 (FIG. 5)
`is able to have a considerably improved performance charac-
`teristic with the addition of very small thin-oxide circuitry to
`the overall silicon. Thus, each ofthe illustrated embodiments,
`as well as the various additional and/or alternative embodi-
`
`ments of the present disclosure represent improvements over
`the existing systems and methods.
`FIG. 7 is a flowchart illustrating process blocks for imple-
`menting one embodiment of the present disclosure. In block
`700, a power-on of a second supply voltage is detected while
`a first supply voltage is already on. At block 701 a current
`capacity of a power on/off detector of the FCC network is
`decreased responsive to the power-on detection. At block 702
`a power-down of the second supply voltage is detected while
`the first supply voltage is on. At block 703 the current capacity
`of the power on/off detector is increased responsive to the
`power-down detection.
`Some embodiments of an exemplary wireless communica-
`tion system include multiple remote units and multiple base
`stations. It can be recognized that typical wireless communi-
`cation systems may have many more remote units and base
`stations. The remote units include multiple semiconductor
`devices having power detection, as discussed above. Embodi-
`ments include forward link signals from the base stations and
`the remote units and reverse link signals from the remote units
`to the base stations.
`
`In other embodiments, a remote unit is a mobile telephone,
`another remote unit is a portable computer, and another
`remote unit is a fixed location remote unit in a wireless local
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`loop system. For example, the remote units may be mobile
`phones, hand-held personal communication systems (PCS)
`units, portable data units such as personal data assistants,
`navigation devices (e.g., GPS enabled devices,) set-top
`boxes, music players, video players, entertainment units,
`fixed location data units such as meter reading equipment, or
`any other device that stores or retrieves data or computer
`instructions, or any combination thereof. Although these
`embodiments illustrates remote units according to the teach-
`ings of the disclosure, the disclosure is not limited to these
`exemplary illustrated units. The disclosed device may be
`suitably employed in any device which includes a semicon-
`ductor device.
`
`Although specific circuitry has been set forth, it will be
`appreciated by those skilled in the art that not all of the
`disclosed circuitry is required to practice the disclosure.
`Moreover, certain well known circuits have not been
`described so as to maintain focus on the disclosure. Similarly,
`although the description refers to logical “0” or “low” and
`logical “ l” or “high” in certain locations, one skilled in the art
`appreciates that the logical values can be switched, with the
`remainder of the circuit adjusted accordingly, without affect-
`ing operation of the present disclosure.
`Although the present disclosure and its advantages have
`been described in detail, it should be understood that various
`changes, substitutions and alterations can be made herein
`without departing from the spirit and scope of the disclosure
`as defined by the appended claims. Moreover, the scope ofthe
`present app