(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY(PCT)
`Wiese AUNTUNA0100
`
`(19) World Intellectual Property Organization
`International Bureau
`
`12 August 2010 (12.08.2010)
`
`(43) International Publication Date
`
`(10) International Publication Number
`WO 2010/091105 A2
`
`(51)
`
`(21)
`
`International Patent Classification:
`HO3K 17/22 (2006.01)
`;
`ale
`International Application Number:
`
`;
`;
`PCT/US2010/023081
`
`(22)
`
`International Filing Date:
`
`(25) Filing Language:
`
`3 February 2010 (03.02.2010)
`
`(26) Publication Language:
`(30) Priority Data:
`12/365,559
`
`4 February 2009 (04.02.2009)
`
`(71) Applicant (for all designated States except US): QUAL-
`COMMINCORPORATED[US/US]; Attn: Internation-
`al Ip Administration, 5775 Morehouse Drive, San Diego,
`CA 92121 (US).
`
`English
`:
`English
`
`US
`
`(72)
`(75)
`
`CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO,
`DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT,
`HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KM, KN, KP,
`KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD,
`ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI,
`NO, NZ, OM,PE, PG, PH, PL, PT, RO, RS, RU, SC, SD,
`SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR,
`TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
`
`(84) Designated States (unless otherwise indicated, for every
`kind ofregional protection available); ARIPO (BW, GH,
`GM, KE, LS, MW, MZ, NA,SD,SL, SZ, TZ, UG, ZM,
`ZW), Eurasian (AM, AZ, BY, KG, KZ, MD, RU, TJ,
`TM), European (AT, BE, BG, CH, CY, CZ, DE, DK, EE,
`ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV,
`MC, MK, MT, NL, NO, PL, PT, RO, SE, SI, SK, SM,
`TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW,
`ML, MR, NE, SN, TD, TG),
`
`Declarations under Rule 4.17:
`
`— as to applicant's entitlement to apply for and be granted
`a patent (Rule 4.17(ii))
`
`Inventors; and
`Inventors/Applicants (for US only): KWON, Cheng, Ki
`[KR/US]; 5775 Morehouse Drive, San Diego, CA 92121
`(US). MOHAN,Vivek [US/US]; 5775 Morehouse Drive,
`San Diego, CA 92121 (US).
`— as to the applicant's entitlement to claim the priority of
`the earlier application
`(Rule 4.17 (iii))
`(74) Agent: TALPALATSKY,Sam; 5775 MorehouseDrive, ee ee ee
`San Diego, CA 92121 (US).
`Published:
`(81) Designated States (unless otherwise indicated, for every — without international search report and fo be republished
`kind ofnational protection available): AE, AG, AL, AM,
`uponreceipt of that report (Rule 48.2(g))
`AO, AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ,
`
`(54) Title: MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN DETECTORS
`
`
`
`
`Power U/D
`
`Detector
`
`
`
`pant
`Lo
`Network
`
`(57) Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core
`network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to
`the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes
`an adjustable current power up/downdetector configured to detect a power state of the core network. The POC network also in-
`cludes processing circuitry coupled to the adjustable current power up/down detector and configured to process the powerstate
`into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-
`up/downdetection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to
`provide feedback signals to adjust a current capacity ofthe adjustable current power up/downdetector.
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.1
`Exhibit 2001, p.1
`
`
`
`
`
`
`
`Wo2010/091.105A2[IINITIMNINIINIMTITMINITITANACAT0TUA
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN DETECTORS
`
`TECHNICAL FIELD
`
`[0001] The present disclosure is related, in general, to integrated circuit
`
`devices and, moreparticularly, to power up/down detectors for multiple supply voltages
`
`devices.
`
`BACKGROUND
`
`[0002] As technology has advancedthere has been an increasedability to
`
`include more and more devices and components within integrated circuits.
`
`Semiconductorfabrication techniques have allowed these embedded devices to become
`
`smaller and have lower voltage requirements, while still operating at high-speeds.
`
`However, because these new integrated devices often interface with older technology
`
`devices or legacy products, input/output (I/O)circuits within the integrated circuit have
`
`remained at higher operating voltages to interface with the higher voltage requirements
`
`of these older systems. Therefore, many newerintegrated circuit devices include dual
`
`powersupplies: one lower-voltage powersupply for the internally operating or core
`
`applications, and a second higher-voltage powersupply for the I/O circuits and devices.
`
`[0003] Core devices and applications communicate with operations
`
`outside of the integrated componentthrough the I/O devices.
`
`In orderto facilitate
`
`communication between the core and I/O devices, level shifters are employed. Because
`
`the I/O devices are connected to the core devices throughlevel shifters, problems may
`
`occur whenthe core devices are powered-down. Powering downor powercollapsing is
`
`a commontechnique used to save power when no device operations are pendingorin
`
`progress. For example,if the core network is powercollapsed, it is possible that the
`
`level shifters, whether through stray currents orthe like, could send a signal to the I/O
`
`devices for transmission. The I/O devices assume that the core devices have initiated
`
`this communication, and will, therefore, transmit the erroneous signal into the external
`
`environment.
`
`[0004]
`
`It has been found useful to have the I/O devices in a knownstate
`
`whenthe core networks are powered down.
`
`In order to guarantee these knownstates,
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.2
`Exhibit 2001, p.2
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`2
`
`solutions have included the addition of hardware or software for managing additional
`
`external signals to control the I/O circuitry. By using these external signals, the I/O
`
`circuitry can be controlled (e.g., placed in a knownstate) wheneverthe core poweris
`
`collapsed. However, whether implementing this external signal management system
`
`using hardware or software, a considerable amountof delay is added to the operation of
`
`the integrated device. Although hardwareisslightly faster than software controls, ,
`
`hardware solutions may have problemscaused by significant additional power leakage
`
`on the I/O device side.
`
`[0005] One hardwaresolution currently in use provides power-up/down
`
`detectors to generate a power-on/off-control (POC) signal internally. The POC signal
`
`instructs the I/O devices when the core devices are shut down, FIGURE|isacircuit
`
`diagram illustrating standard POC system 10 for multiple supply voltage devices. POC
`
`system 10 is made up of three functional blocks: power-up/downdetector 100, signal
`
`amplifier 101, and output stage 102. Power-up/downdetector 100 has PMOStransistor
`
`M1 and NMOStransistors M2 — M3. The gate terminals for each of MI-M3 are
`
`connected to core powersupply 103, Veore. When core powersupply 103 is power
`
`collapsed, M2 and M3 are switched off while M1 is switched on, pulling up the input
`
`node to amplifier 105 to Vyo,i.e., /O power supply 104. A “high”signal is input into
`
`amplifier 105 which inverts the output to a “low”signal.
`
`In output stage 102, the low
`
`signal from amplifier 105 is processed in output buffer 106 and again inverted to a high
`
`signal for POC 107. The high signal for POC 107is transmitted to the I/O circuitry
`
`indicating that core power supply 103 has been shut down.
`
`[0006] When core powersupply 103, Veore, is on, M1 becomes very weak
`
`and M2 and M3 both switchstrongly on, pulling the input node to amplifier 105 to Vss,
`
`i.c., core power supply 103. Vss is considered the logical low signal. Therefore,
`
`amplifier 105 invertsit to a high signal whichis then processed in output buffer 106 and
`
`inverted again to a low signal. This signal detection process operates acceptably when
`
`either I/O power supply 104 is on and core powersupply 103 is power collapsed or
`
`when core powersupply 103 is powered-up before I/O powersupply 104 is powered-
`
`up. However, when I/O powersupply 104 is powered-up before core power supply 103
`
`powers-up, substantial current leakage may occurin the power up/down detector 100 or
`
`in the POC 10.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.3
`Exhibit 2001, p.3
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`3
`
`[0007]
`
`In the situation where I/O powersupply 104 is on and core power
`
`supply 103 is off, M1 is switched on with M2 and M3 switched off. When core power
`
`supply 103 is then powered up, M2 and M3 switch on, and M1 becomes very weak.
`
`However, before M1 can switch completely off, there is a period in whichall three
`
`transistors within power up/downdetector 100 are on. Thus, a virtual short is created to
`
`ground causing a significant amount of current to flow from I/O power supply 104 to
`
`ground. This “glitch” current consumes unnecessary power.
`
`[0008]
`
`In order to reduce this stray power consumption, one solution may
`
`be adopted to decreasethe sizes of transistors M1-M3. By reducing the size of M1-M3,
`
`the actual amountof current that can pass throughthe transistors is physically limited.
`
`However, becausethe transistors are now smaller, their switching speedsare also
`
`reduced. The reduced switching speed translates into less sensitivity in detecting
`
`power-up/downofcore supply voltage 103 or longer processing time for power-
`
`up/downevents.
`
`[0009]
`
`FIGURE2 is anillustration of diagram 20 presenting the signal
`
`interactions in POCcircuit 10 of FIGURE 1. Diagram 20 includes power supply
`
`diagram 21 and POC diagram 22. As I/O powersupply 104 is powered up, there is a
`
`steady increase until it reaches Vj. POC 107 follows I/O powersupply 104 asit
`
`powers up to reach the high level. Similarly, when I/O powersupply 104 maintains
`
`steady at Vyoat time 200, POC 107 remainssteady at the high signal. When core
`
`powersupply 103 begins to poweron at time 201 power up/down detector 100
`
`(FIGURE1) takesa little time to actually detect this new powerlevel. Once detected, at
`
`time 202, POC 107 is switched to the low value. POC 107 should, thereafter, remain at
`
`the low level until core power supply 103 is power collapsed, between times 203 and
`
`205. Again, because power up/downdetector 100 (FIGURE 1) takesalittle time to
`
`actually detect the new powerlevel, POC 107 remainsin the low state until time 204,
`
`whenthe powering downis actually detected by power up/down detector 100. This
`
`low state time, between time 202 and 204 is referred to as the normal operation region.
`
`Once core powersupply 103 is completely off or powercollapsed at time 205, the input
`
`to amplifier 105 (FIGURE 1) is again pulled up to the high signal. POC 107 will then
`
`follow I/O powersupply 104 as it also powers down between times 206 and 207.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.4
`Exhibit 2001, p.4
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`4
`
`[0010] The leakage current between I/O powersupply 104 and ground can
`
`be lessened becauseofthe smallertransistor size. Thus, during the time between times
`
`201 and 205 any leakage that occurs is reduced. However, this reduced leakage comes
`
`at the price of faster detection. If POC circuit 10 may include the lower-threshold or
`
`biggertransistors, switching/detecting times would be faster. For example, as core
`
`powersupply 103 begins to powerupat time 201, the lower-threshold or bigger
`
`transistors of power up/down detector 100 would detect the power-up at time 208,
`
`instead of time 202. Moreover when core powersupply 103 begins powering downat
`
`time 203, the power up/downdetector 100 would detect the power-downat time 209,
`
`instead of time 204. This increase maybe represented by the difference between the
`
`time periods of time 202 to 204 vs. time 208 to 209. Therefore, the conventional
`
`solutionsstill have problems with leakage and switching times.
`
`SUMMARY
`
`[0011]
`
`Various representative embodiments ofthe disclosure relate to
`
`integrated devices having multiple supply voltages. Further representative
`
`embodimentsof the present disclosure relate to methods for reducing power
`
`consumption in a poweron/off control (POC) network of a multiple supply voltage
`
`device. Additional representative embodiments ofthe present disclosure relate to
`
`systems for reducing power consumption in a POC networkof a multiple supply voltage
`
`device.
`
`[0012] A multiple supply voltage device includes a core network operative
`
`at a first supply voltage and a control network coupled to the core network. The control
`
`networkis configured to transmit a control signal. The control network includes an
`
`up/down ( up/down) detector configured to detect a powerstate of the core network.
`
`The control network further includes processing circuitry coupled to the up/down
`
`detector and is configured to generate the control signal based on the powerstate. The
`
`control network further includes one or more feedback circuits coupled to the up/down
`
`detector. The one or more feedbackcircuits are configured to provide feedback signals
`
`to adjust a current capacity of said up/down detector.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.5
`Exhibit 2001, p.5
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`5
`
`[0013] A method for reducing power consumption in a poweron/off
`
`control (POC) network of a multiple supply voltage device includes detecting a power-
`
`on of a second supply voltage while a first supply voltage is already on, decreasing a
`
`current capacity of a poweron/off detector of the POC network in responseto the
`
`power-on detection, detecting a power-down ofthe second supply voltage while thefirst
`
`supply voltage is on, and increasing the current capacity of the poweron/off detector in
`
`response to the power-downdetection.
`
`[0014] A system for reducing power consumption in a poweron/off control
`
`(POC) network of a multiple supply voltage device includes a meansfor detecting a
`
`power-on of a second supply voltage while a first supply voltage is already on. The
`
`system further includes meansfor decreasing a current capacity of a poweron/off
`
`detector of the POC network responsive to the power-on detection. The system further
`
`includes meansfor detecting a power-downofthe second supply voltage while the first
`
`supply voltage is on, and meansfor increasing the current capacity of the power on/off
`
`detector responsive to the power-downdetection.
`
`[0015] The foregoing has outlined rather broadly the features and
`
`technical advantages of the present embodimentsin order that the detailed description of
`
`the disclosure that follows may be better understood. Additional features and
`
`advantages of the embodiments will be described hereinafter which form the subject of
`
`the claims of the disclosure.
`
`It should be appreciated by those skilled in the art that the
`
`conception and specific embodiments disclosed maybereadily utilized as a basis for
`
`modifying or designing other structures for carrying out the same purposesofthe
`
`present disclosure.
`
`It should also be realized by those skilled in the art that such
`
`equivalent constructions do not depart from the spirit and scope ofthe disclosure as set
`
`forth in the appended claims. The novel features which are believed to be characteristic
`
`ofthe disclosure, both as to its organization and method of operation, together with
`
`further objects and advantageswill be better understood from the following description
`
`when considered in connection with the accompanyingfigures.It is to be expressly
`
`understood, however, that each of the figures is provided for the purposeofillustration
`
`and description only andis not intended as a definition of the limits of the present
`
`disclosure.
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.6
`Exhibit 2001, p.6
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`6
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0016]
`
`For amore complete understanding of the present disclosure,
`
`reference is now madeto the following descriptions taken in conjunction with the
`
`accompanying drawings.
`
`
`
`[0017] FIGURE1|isa circuit diagram illustrating a conventional POC
`
`system for multiple supply voltage devices.
`
`[0018]
`
`FIGURE2 is anillustration of a diagram presenting the signal
`
`interactions in the POC circuit of FIGURE1.
`
`[0019]
`
`FIGURE3A is a block diagram illustrating an integrated circuit
`
`(IC) device having a power on control (POC) network configured according to the
`
`teachingsof the present disclosure.
`
`[0020]
`
`FIGURE 3B is a block diagram illustrating a POC network
`
`configured according to the teachings of the presentdisclosure.
`
`
`
`[0021] FIGURE4isacircuit diagram illustrating another POC network
`
`configured according to the teachings of the present disclosure.
`
`
`
`[0022] FIGURE5 isacircuit diagram illustrating a further POC network
`
`configured accordingto the teachingsofthe present disclosure.
`
`[0023]
`
`FIGURE6 is a circuit diagram illustrating still another POC
`
`network configured according to the teachings of the presentdisclosure.
`
`
`
`[0024] FIGURE7isaflowchart illustrating process blocks for
`
`implementing one embodiment according to the teachings of the present disclosure.
`
`FIGURE8is a diagram illustrating an exemplary wireless communication
`
`system.
`
`DETAILED DESCRIPTION
`
`[0025] Turning now to FIGURE3A,a block diagram is presented
`
`illustrating an integrated circuit (IC) device 30 having a poweron control (POC)
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.7
`Exhibit 2001, p.7
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`7
`
`network 305 configured according to one embodimentofthe present disclosure. The IC
`
`device 30 is an integrated circuit that includes embedded components powered by
`
`multiple power supplies, such as the Vyo 300 and the Veore 301. TheVio 300 and the
`
`Veore 301 supply several different voltage level power supplies to different components
`
`and networks within the IC device 30. Two such embedded networksare the I/O
`
`network 302 and the core network 303. The I/O network 302 operatesat a voltage level
`
`provided by the Vy 300. The Core network 303 operates at a voltage level provided by
`
`the Voor 301, which is usually a lower voltage than that provided by the Vio 300.
`
`Becausethe I/O network 302 and the core network 303 operateat different voltages,
`
`they are coupled together through level shifters 304 for communication. Thelevel
`
`shifters 304 essentially shift the voltage levels of any communications that occur
`
`betweenthe I/O network 302 and the core network 303.
`
`[0026]
`
`POC network 305 sensesthe status of the core network 303 and
`
`transmits a POCsignalto the I/O network 302 and level shifters 304. The POC signal
`
`either turns them on oroff. This prevents stray signals received by the I/O network 302
`
`from being mistakenly transmitted to devices or components external to the IC device
`
`30.
`
`
`
`[0027] FIGURE3B isablock diagram illustrating a POC network 305
`
`configured according to one embodimentofthe present disclosure. The POC network
`
`305 includes a power up/down detector 306, processing circuitry 307, and feedback
`
`network 310. The processing circuitry 307 is made up ofa signal processor 308 and an
`
`output buffer 309. When the Vo 300 is on and the Veore 301 is off, the power up/down
`
`detector 306 provides a detection signal to the signal processor 308, which processes the
`
`detection signal and transmits the processed signal to the output buffer 309. The output
`
`buffer 309 then conditions the processed signal into a POC signal 311, which is then
`
`transmitted to an I/O network 302. Along the way, a feedback network 310 receives
`
`feedback from the signal processor 308 and feeds that signal back to the power
`
`up/down detector 306. The power up/downdetector 306 uses the feedback signal to
`
`adjust its current capacity. While the Veore 301 is in an off or low state, the feedback
`
`signal allows the power up/downdetector 306 to select a maximum current capacity.
`
`This maximum current capacity state makes the power up/downdetector 306 more
`
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.8
`Exhibit 2001, p.8
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`8
`
`sensitive to detecting when the Veore 301 either powers-up or powers-down,or both,
`
`depending onthe circuit configuration of the power up/downdetector 306.
`
`[0028] When the Voor 301 powers-up while the Vio 300 is on, the power
`
`up/down detector 306 detects the power-up and changesthe value of the detection signal
`
`transmitted to the signal processor 308. The process detection signal is then conditioned
`
`by the output buffer 309 into the changed POCsignal 311 and transmitted to the I/O
`
`network 302. With the changing signals being processed through the signal processing
`
`circuitry 307, the feedback network 310 receives the new feedback signal that, when
`
`input into power the up/downdetector 306, causes the current capacity within the power
`
`up/downdetector 306 to decrease. This decrease in current capacity will limit and
`
`reduce the amount of leakage current that may be dissipated through the power
`
`up/downdetector 306 becauseofits connections to the Vio 300 and the Veore 301.
`
`
`
`[0029] FIGURE4 isacircuit diagram illustrating a POC network 40
`
`configured according to one embodimentofthe present disclosure. The POC network
`
`40 has similar processing regions as the POC network 305 (FIGURE3A and 3B),i.e., a
`
`power up/downdetector 306, a signal processor 308, an output buffer 309, and a
`
`feedback network 310. The POC network 40 also generates a POC signal 311 and is
`
`coupled to a Vy300 and a Veore 301. As shown in the embodimentillustrated in
`
`FIGURE 4, the power up/down detector 306 comprises multiple transistors M4-M7
`
`coupledin series together. Each gate of the transistors M4-M7is coupled to the Veore
`
`301, while the source terminalof the transistor M4 is coupled to the Vyo 300. The
`
`transistors M4 and MSare p-typetransistors and the transistors M6 and M7are n-type
`
`transistors. Therefore, when the Vcore 301 is off, i.¢., in a low state, the transistors M4
`
`and M5 are switched on, while the transistors M6 and M7 are switchedoff.
`
`[0030]
`
`In contrast, when the Vor 301 is on,i.e., in a high state, transistors
`
`M4 and M5 become very weak while transistors M6 and M7are strongly switched on.
`
`M6and M7turning on pulls the voltage of the input to inverting amplifier to Vss, which
`
`is a logical low signal compared with Vyo. Vss is designed as the logical low signal and
`
`may comprise ground, 0 V, or some other selected voltage level that represents the
`
`logical low symbol. Thus, when the Veore 301 is off, the transistors M4 and M5 pull up
`
`the voltage level at the inputto an inverting amplifier 400 to the Vio 300. Therefore,
`
`the input to the inverting amplifier 400 is high when the Veore 301 is off and low when
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.9
`Exhibit 2001, p.9
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`9
`
`the Veore 301 is on. The inverting amplifier 400 then amplifies and inverts the detection
`
`signal before transmitting it to the inverting buffer 401 for conditioning and inverting
`
`for the POC signal 311.
`
`[0031] The feedback network 310 comprisesa transistor M8 connected in
`
`parallel to the transistor M4. Thetransistor M8is also configured as a p-type transistor,
`
`such that when the feedback signal from the inverting amplifier 400 is high, the
`
`transistor M8 is switched off, and when the feed back signal is low, the transistor M8 is
`
`switched on. Thus, when the Veore 301 is off, producing a high detection signal, the
`
`inverting amplifier 400 inverts that signal to a logic low which causesthe transistor M8
`
`to switch on. As the Veore 301 is powered-on, the detection signal changesto a logic
`
`low, which changesthe feedback signal from the inverting amplifier 400 to a logic high,
`
`which, in turn, turns the transistor M8 off. While the transistor M8is off, the power
`
`up/downdetector 306 has a decreased current capacity, i.e., smaller current will flow
`
`through the transistor M8 becauseof the amplified low signal. The voltage level caused
`
`by the Veore 301 on the gate terminals of M4 and MS could in someglitch orstray signal
`
`situations, cause leakage through M4 and M5. Because the feedback signal for the
`
`transistor M8is received from the inverting amplifier 400, when the Veore 301 powers-
`
`down,the feedback signal will switch quickly from a logic high to a logic low, which
`
`will then switch the transistor M8 on. Thus,in the circuit configuration depicted in
`
`FIGURE 4, the power up/down detector 40 will detect the Veore 301 powering down
`
`more quickly than the existing POC networks.
`
`[0032]
`
`FIGURE 5 isa circuit diagram illustrating a POC network 50
`
`configured according to one embodimentofthe present disclosure. The POC network
`
`50 comprises multiple transistors M4-M7 in the power up/downdetector 306 coupled
`
`together in a fashion similar to the POC network 40 (FIGURE4) with each gate coupled
`
`to a Veore 301, and the source terminal of the transistor M4 coupled to a Vio 300. A
`
`signal processor 308 comprises an inverting amplifier 400, and an output buffer 309
`
`includes an inverting buffer 401. The POC network 50 generates a POCsignal 311,
`
`whichwill be transmitted to the I/O network to which the POC network 50 is coupled.
`
`In the POC network 50, a feedback network 310 is configured with the transistors M9
`
`and M10 coupledin parallel with the transistor M7. The transistors M6, M7, M10,are
`
`the same type, n-type or can be low-threshold n-type transistors to speed up the power-
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.10
`Exhibit 2001, p.10
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`10
`
`on detection. The transistor M9 receivesits feedback signal from the output of the
`
`inverting buffer 401, while the gate of the transistor M10 is connected to the Veore 301.
`
`[0033]
`
`In operation, when the Vyo 300 is on and the Veore 301 is off, the
`
`inverting amplifier 400 receives a logic high signal by virtue of the Vio 300, which,
`
`when amplified and inverted by the inverting amplifier 400 and then conditioned and
`
`inverted by the inverting buffer 401, provides a logic high feedback signal. This high
`
`signal would normally switch M9 in the feedback network 310 on. However, because
`
`M6, M7, and M10 areall off, there is no channel formation within the transistor M9 to
`
`switch it on. When the Veore 301 powers on, M4 and M5 becomevery weak, while M6,
`
`M7, and M10 switch on, which immediately causes M9 to switch on becauseits gate is
`
`already connected to a logic high input. M6 and M7 switching on pulls the inputto the
`
`inverting amplifier 400 downto a logical low signal, i.e., Vss. The low detection signal
`
`input to the inverting amplifier 400 is amplified and inverted and then conditioned and
`
`inverted again at the inverting buffer 401. Once the inverting buffer 401 outputs a low
`
`signal, the feedback ofthat low to the transistor M9 will switch M9 off, which, because
`
`switching M9 off stops the channel formation in the transistor M10, causes the transistor
`
`M10 to also switch off. Thus, the configuration of the POC network 50,as illustrated in
`
`FIGURE 5, operates to detect the Vcore 301 powering on faster than the existing POC
`
`networks, while still reducing the amount of leakage current while the Veore 301 is on.
`
`The feedback signal used by the transistor M9 allows the power up/down detector 306
`
`to adjust its current capacity, which reducesthe leakage currentat the sametimeas the
`
`detection speed is improved.
`
`[0034]
`
`FIGURE 6 isa circuit diagram illustrating a POC network 60
`
`configured according to one embodimentofthe present disclosure. The POC network
`
`60 includes a feedback network 310 configured according to the circuit arrangements of
`
`both the POC network 40 (FIGURE 4) and the POC network 50 (FIGURE 5). As such,
`
`multiple transistors M4-M7 make up the power up/downdetector 306. The feedback
`
`network 310 includes transistor M8, coupled in parallel to the transistor M4, and the
`
`transistors M9 and M10, coupledin parallel with the transistor M7. The detection
`
`signal from the power up/downdetector 306 provides input to an inverting amplifier
`
`400 of a signal processor 308, which amplifies and inverts the detection signal for input
`
`to an inverting buffer 401 of an output buffer 309. The conditioned and inverted POC
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.11
`Exhibit 2001, p.11
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`1]
`
`signal 311 is then transmitted to the appropriate I/O and level shifter network of the
`
`system. The feedback transistor M8 obtains its feedback signal from the output of the
`
`inverting amplifier 400, while the feedback transistor M9 obtainsits feedback signal
`
`from the output of the inverting buffer 401. Using these feedback signals, as described
`
`with respect to the POC network 40 (FIGURE 4) and the POC network 50 (FIGURE5),
`
`the POC network 60is able to increase the speed that the Veore 301 is quickly detected
`
`both in the power-on and power-off stages. At the same time, because the feedback
`
`network 310 provides the capability of the POC network 60 to adjust the current
`
`capacity of the power up/downdetector 306, the unwanted leakage current can also be
`
`reduced during the Voor 301 normal operation periods.
`
`[0035]
`
`It should be noted that each of the embodiments described with
`
`respect to the POC network 40 (FIGURE 4), the POC network 50 (FIGURE5), and the
`
`POC network 60 (FIGURE 6) has its own advantages. For example, the POC network
`
`50 (FIGURE 5)is able to have a considerably improved performancecharacteristic with
`
`the addition of very small thin-oxidecircuitry to the overall silicon. Thus, each of the
`
`illustrated embodiments, as well as the various additional and/or alternative
`
`embodimentsof the present disclosure represent improvements overthe existing
`
`systems and methods.
`
`[0036]
`
`FIGURE7 is a flowchartillustrating process blocks for
`
`implementing one embodimentof the present disclosure.
`
`In block 700, a power-on ofa
`
`second supply voltage is detected while a first supply voltage is already on. At block
`
`701 a current capacity of a power on/off detector of the POC network is decreased
`
`responsive to the power-on detection. At block 702 a power-down ofthe second supply
`
`voltage is detected while the first supply voltage is on. At block 703 the current
`
`capacity of the poweron/off detector is increased responsive to the power-down
`
`detection.
`
`[0037]
`
`Figure 8 is a diagram illustrating an exemplary wireless communication
`
`system.
`
`In some embodiments, a system 800 includes multiple remote units 820-824
`
`and multiple base stations 850-852.
`
`It can be recognized that typical wireless
`
`communication systems may have many more remote units and basestations. The
`
`remote units 820-824 include multiple semiconductor devices 830-834 having power
`
`detection, as discussed above. Figure 8 showsa forward link signals 880 from the base
`Apple Inc. v. Qualcomm Incorporated
`Apple Inc. v. Qualcomm Incorporated
`IPR2018-01315
`IPR2018-01315
`Exhibit 2001, p.12
`Exhibit 2001, p.12
`
`

`

`WO 2010/091105
`
`PCT/US2010/023081
`
`12
`
`stations 850-852 and the remote units 820-824 and a reverselink signals 890 from the
`
`remote units 820-824 to the base stations 850-852.
`
`[0038]
`
`In other embodiments, Figure 8 the remote unit 820 is shown as a
`
`mobile telephone, the remote unit 822 is shown as a portable computer, and the remote
`
`unit 824 is shownasa fixed location remote unit in a wireless local loop system. For
`
`example, the remote units may be mobile phones, hand-held personal communication
`
`systems (PCS) units, portable data units such as personaldata assistants, navigation
`
`devices (e.g., GPS enabled devices,) set-top boxes, music players, video players,
`
`entertainmentunits, fixed location data units such as meter reading equipment, or any
`
`other device that stores or retrieves data or computerinstructions, or any combina