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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`Apple Inc.,
`Petitioner,
`v.
`
`Qualcomm Incorporated,
`Patent Owner
`____________________
`Case IPR2018-01315
`U.S. Patent No. 8,063,674
`_____________________
`
`PATENT OWNER SUR-REPLY
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`
` 
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` 
`
`B. 
`C. 
`
`Table of Contents
`Introduction ..................................................................................................... 1 
`Petitioner Does Not Disagree That AAPA Is Not Proper Prior Art In
`Inter Partes Review Proceedings ................................................................... 1 
`  Neither The Reply Nor Dr. Horst’s New Simulation Results Rebut
`Qualcomm’s Showing That The POSA Would Not Combine The
`Alleged AAPA And Majcherczak .................................................................. 2 
`A. 
`Petitioner’s Argument About The Alleged “Explicit”
`Motivation To Combine Is Erroneous .................................................. 2 
`The Reply’s Criticism Of Dr. Pedram’s Testimony Is Misplaced ....... 7 
`Dr. Horst’s Simulations Do Not Prove That The POSA Would
`Be Motivated To Combine The Alleged AAPA And
`Majcherczak ......................................................................................... 8 
`1. 
`The Simulation Results Are Unreliable And Should Be
`Disregarded ................................................................................ 9 
`Dr. Horst Selected Unrealistic Parameter Values That
`The POSA Would Never Use In The Proposed
`AAPA/Majcherczak Combination ........................................... 11 
`Dr. Horst Cherry Picked Parameter Values Favorable For
`Petitioner Without Providing Any Rationale For Their
`Selection ................................................................................... 16 
`The Simulations Fail To Show That The
`AAPA/Majcherczak Combination Does Not Result In
`Increased Leakage Current ...................................................... 17 
`The Single Simulation Result For AAPA/Majcherczak
`Reported By Dr. Horst Does Not Rebut Dr. Pedram’s
`Showing ................................................................................... 18 
`  Petitioner’s Extensive New Evidence And Argument Cannot Cure
`The Petition’s Failure To Show That The POSA Would Be Motivated
`To Combine Steinacker, Doyle, and Park .................................................... 19 
`
`2. 
`
`3. 
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`4. 
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`5. 
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`
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`-ii-
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`

`IPR2018-01315
`U.S. Patent 8,063,674
`Petitioner’s New Reasons For Why The POSA Would
`Allegedly Combine The References Are Deficient ........................... 21 
`Dr. Horst’s New Simulation Results Do Not Rebut
`Qualcomm’s Showing That The Hypothetical
`Steinacker/Doyle/Park Circuit Has Leakage And Glitch Current
`Problems ............................................................................................. 25 
`1. 
`Dr. Horst’s Simulation Results Contain Significant Errors ..... 25 
`2. 
`The Parameter Values Selected For The Proposed
`Steinacker/Doyle/Park Combination Are Unrealistic .............. 25 
`Dr. Horst’s Cherry Picked Parameter Values Show That
`His Selections Are Biased ........................................................ 26 
`The Simulations Fail To Show That The Proposed
`Steinacker/Doyle/Park Circuit Does Not Result In
`Increased Leakage Current ...................................................... 26 
`The Single Reported Simulation Result Does Not Rebut
`Dr. Pedram’s Showing ............................................................. 27 
`Conclusion .................................................................................................... 27 
`
`3. 
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`4. 
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`5. 
`
`A. 
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`B. 
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`-iii-
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`
`
`
`Introduction
`Petitioner’s reply introduces unpersuasive and belated arguments and
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`evidence that cannot salvage the petition. The Board should confirm the
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`patentability of claims 1, 2, and 5-7.
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`
`
`
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`Petitioner Does Not Disagree That AAPA Is Not Proper Prior Art In
`Inter Partes Review Proceedings
`Qualcomm’s response showed that Grounds 2(a) and 2(b) are improper
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`because the America Invents Act (AIA) does not permit IPR based on so-called
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`applicants admitted prior art (AAPA). Paper 12 at 17-20.
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`
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`The reply does not disagree that AAPA is not proper prior art for IPR
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`proceedings. Paper 16 at 1-2. In fact, the reply never makes the affirmative
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`statement that AAPA should be considered prior art in IPRs. See id. Instead,
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`Petitioner merely points out that the Institution Decision followed the logic
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`articulated in a previous IPR where a different panel found AAPA to be prior art.1
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`Id. But Petitioner carefully avoids endorsing the previous panel’s approach or ever
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`stating affirmatively that AAPA is proper prior art. The reason for this is clear:
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`
`
`1 The previous panel decision cited by Petitioner is distinguishable from the present
`case. In the cited case, AAPA was relied on as a secondary reference in an
`obviousness ground. One World Techs., Inc. v. Chamberlain Group, Inc., IPR2017-
`00126, Paper 56 at 6 (PTAB Oct. 24, 2018). By contrast, in the present case,
`Petitioner attempts to rely on AAPA as a primary reference.
`1
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`

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`IPR2018-01315
`U.S. Patent 8,063,674
`Counsel for Petitioner is currently taking the position before the Board and the
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`Federal Circuit that AAPA is “not ‘prior art consisting of patents or printed
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`publications’ and, thus is ineligible for inter partes review.” Ex. 2004 at 3.
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`
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`Qualcomm agrees with the position taken by Petitioner’s counsel in these
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`other proceedings.2 Petitioner’s reliance on AAPA is improper, and the challenged
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`claims should be held patentable over Grounds 2(a) and 2(b).
`
` Neither The Reply Nor Dr. Horst’s New Simulation Results Rebut
`Qualcomm’s Showing That The POSA Would Not Combine The
`Alleged AAPA And Majcherczak
`A.
`Petitioner’s Argument About The Alleged “Explicit” Motivation
`To Combine Is Erroneous
`The reply argues that a POSITA would have been motivated to integrate the
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`
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`feedback transistor M6 of Majcherczak’s voltage detector into the alleged AAPA to
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`enable stabilizing of the detection device through hysteresis, as described in
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`Majcherczak. Paper 16 at 2-6. But Petitioner is wrong because a POSA faced with
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`
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`2 Permitting petitioners to rely on AAPA in IPR proceedings is improper because,
`among other reasons, it dissuades patent applicants from including a background
`section in their patent applications. Further, Petitioner’s reliance on the alleged
`AAPA here is especially improper because it is being applied as a primary reference.
`Obviousness is judged by putting oneself in the mind of the POSA—and then asking
`whether that person, the POSA, would be motivated to combine the prior art to reach
`the claimed invention. Here, Petitioner puts itself not in the mind of the POSA, but
`rather in the mind of the inventor as a starting point. Applying the alleged AAPA as
`the primary reference inherently leads to hindsight bias because it starts the
`obviousness inquiry from the wrong context: the inventor’s mind, not the POSA’s.
`2
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`
`
`

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`IPR2018-01315
`U.S. Patent 8,063,674
`the problems articulated in the alleged AAPA—high leakage current and slow
`
`switching times—would never seek to add hysteresis.
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`
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`The primary reference of Petitioner’s Ground 2a is the alleged AAPA. See,
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`e.g., Paper 2 at 43-45. For this ground, Petitioner proposes “integrat[ing] … the
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`feedback transistor M6 from Majcherczak’s voltage detector into the POC system 10
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`of the AAPA” (id. at 43):
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`
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`Id. at 44.
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`
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`The Background section of the ’674 patent describes that the alleged AAPA
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`“ha[s] problems with leakage and switching times.” Ex. 1001 at 3:10-11.
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`Specifically, the patent states that the circuit of Figure 1 (i.e., the alleged AAPA)
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`suffers from undesirable leakage current that flows from VI/O to ground. Id. at 2:21-
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`39, 2:63-3:11. The patent further describes that “to reduce this stray power
`
`
`
`3
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`

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`IPR2018-01315
`U.S. Patent 8,063,674
`consumption, one solution may be … to decrease the sizes of transistors M1-M3.
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`By reducing the size of M1-M3, the actual amount of current that can pass through
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`the transistors is physically limited.” Id. at 2:31-35. But this solution comes at a
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`cost: “[B]ecause the transistors are now smaller, their switching speeds are also
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`reduced. The reduced switching speed translates into less sensitivity in detecting
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`power-up/down of core supply voltage 103 or longer processing time for power-
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`up/down events.” Id. at 2:35-39; see also id. at 2:63-67. The switching speed can
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`be increased by using lower-threshold transistors, but such transistors result in higher
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`leakage current. See id. at 2:67-3:10. The Background section concludes that
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`“[t]herefore, the conventional solutions still have problems with leakage and
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`switching times.” Id. at 3:10-11.
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`
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`A POSA starting with the alleged AAPA would never turn to Majcherczak for
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`its alleged “advantageous hysteresis.” Paper 16 at 5. Accordingly, the purported
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`“explicit motivation in Majcherczak” (id. at 3) is no motivation at all because the
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`POSA would never even get to this reference.
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`
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`First, the addition of Majcherczak’s hysteresis to the alleged AAPA would
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`make the high leakage current problem identified in the AAPA worse. Qualcomm’s
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`expert Dr. Pedram showed that Petitioner’s proposed addition of Majcherczak’s
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`transistor M6 to Figure 1 of the ’674 Patent (the alleged AAPA) results in increased
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`leakage current. Ex. 2002 at ¶¶69-74. The reply presents computer simulations
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`
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`4
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`IPR2018-01315
`U.S. Patent 8,063,674
`attempting to show that the AAPA/Majcherczak circuit does not have increased
`
`leakage current, but as explained in Section III.C.2 below, the simulations use
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`unrealistic parameter values that the POSA would never use, and therefore do not
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`rebut Dr. Pedram’s showing.
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`
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`Second, in view of the switching-speed problem articulated in the alleged
`
`AAPA, the POSA would never seek to add Majcherczak’s hysteresis absent
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`impermissible hindsight reconstruction. Hysteresis, by its very nature, slows down
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`detection in an up/down detector because it adds a noise margin and thus delays
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`(i) power-up detection to occur at higher voltages than normal, and (ii) power-down
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`detection to occur at lower voltages than normal. The POSA faced with the problem
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`of slow switching speeds described in the AAPA would thus never consider adding
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`Majcherczak’s hysteresis absent impermissible hindsight.
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`
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`In fact, the addition of the feedback circuit in the ’674 patent invention is
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`counterintuitive and further evidences the innovative nature of the invention. The
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`’674 patent invention adds this feedback circuit in a manner that minimizes the effect
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`on switching speed. See, e.g., Ex. 1001 at 7:4-7. In Majcherczak, by contrast, speed
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`is not a consideration, and the major concern of the reference is to increase the
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`stability of its detection device. See, e.g., Ex. 1008 at ¶37. Facing Majcherczak’s
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`problem of adding stability, i.e., avoiding false detection such as by adding a noise
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`margin, the intuitive solution would be to add hysteresis, and that is what
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`
`
`5
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`Majcherczak describes. But the POSA faced with the switching speed problem of
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`the alleged AAPA would never seek to add hysteresis because doing so would
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`decrease detection speeds and thus be counterintuitive.
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`
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`Third, although Petitioner highlights Majcherczak’s teaching of “enabl[ing]
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`the proper stabilizing of the detection device” (Paper 16 at 2-4), no portion of the
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`alleged AAPA suggests that stability is a problem in the AAPA circuit. As explained
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`above, the alleged AAPA identifies just two problems—leakage current and slow
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`switching times—and instability of the detection device is not one of them.
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`Accordingly, the POSA starting with the AAPA would have no reason to look to
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`Majcherczak for its alleged teaching of proper stabilization of the detection device
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`through hysteresis.
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`
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`Petitioner argues that the disadvantages resulting from the combination of the
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`alleged AAPA and Majcherczak amount to a “teaching away” defense. Paper 16
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`at 7. But that is wrong. As explained above, Petitioner’s one alleged motivation to
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`combine the references—“enabl[ing] the proper stabilizing of the detection
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`device”—is deficient, and there is no reason why a POSA would be motivated to
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`make Petitioner’s proposed combination absent a hindsight desire to create a circuit
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`reading on claims of the ’674 Patent. Petitioner has therefore failed to establish a
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`prima facie case of obviousness.
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`
`
`6
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`B.
`The Reply’s Criticism Of Dr. Pedram’s Testimony Is Misplaced
` Petitioner faults Dr. Pedram for not “cit[ing] to any references to support the
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`
`
`list of disadvantages … arising from the Petition’s combination of AAPA with
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`Majcherczak.” Paper 16 at 7. But the disadvantages described by Dr. Pedram—
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`increased leakage and glitch current and the DC fighting condition—are all well-
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`known phenomena that would be immediately apparent to the POSA upon
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`considering the proposed combination. See Ex. 2002 at ¶¶67-85. Petitioner sets
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`forth no argument that the disadvantages described by Dr. Pedram are obscure or not
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`generally understood, and such an assertion would be wrong.
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`
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`Further, the reply cites no statute, rule, or caselaw to support the proposition
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`that an expert’s opinion must be corroborated by independent references.
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`Dr. Pedram has over 30 years of experience in the fields of integrated circuit devices
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`and electronics, and his testimony on the disadvantages that would be apparent to
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`the POSA is informed by this extensive experience. See Ex. 2002 at ¶¶4-19.
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`Petitioner’s argument about the lack of corroborating references does not disprove
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`Dr. Pedram’s informed testimony.
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`
`
`The reply cites the Federal Circuit’s statement in Medichem, S.A. v. Rolabo,
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`S.L. that “a given course of action often has simultaneous advantages and
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`disadvantages, and this does not necessarily obviate motivation to combine.” 437
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`F.3d 1157, 1165 (Fed. Cir. 2006). Here, however, the purported advantage of
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`
`
`7
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`Majcherczak is no advantage at all. As explained in Section III.A above, the alleged
`
`AAPA identifies leakage current and slow switching speed as the problems of the
`
`conventional solutions, and the POSA faced with these problems would never turn
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`to Majcherczak. The additional disadvantages identified by Dr. Pedram—increased
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`glitch current, a DC fighting condition, etc.—further obviate any alleged motivation
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`to combine.
`
`C. Dr. Horst’s Simulations Do Not Prove That The POSA Would Be
`Motivated To Combine The Alleged AAPA And Majcherczak
` The reply argues that each of the problems of the AAPA/Majcherczak
`
`
`
`combination articulated by Dr. Pedram can be overcome through careful selection
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`of parameter values. Paper 16 at 7-12. To demonstrate this, Petitioner’s declarant
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`Dr. Horst performed simulations of the proposed combination of AAPA and
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`Majcherczak using unrealistic parameters and presents a single simulation case that
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`allegedly avoids the problems described by Dr. Pedram. Ex. 1018 at ¶¶21-31.
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`
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`As an initial matter, Petitioner’s argument misunderstands the proper inquiry
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`for obviousness. The relevant question is whether the POSA would be motivated to
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`combine the alleged AAPA and Majcherczak to reach the claimed invention. As
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`explained in Section III.A above, the POSA starting with the alleged AAPA would
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`never look to Majcherczak in the first place. The reply, however, incorrectly
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`assumes that the POSA would combine the references and works backwards to find
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`
`
`8
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`a set of parameters that could allegedly avoid the problems articulated by
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`Dr. Pedram. Paper 16 at 7-12. This approach is erroneous because the POSA never
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`would have made the combination in the first place.
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`
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`In any case, Dr. Horst’s simulations do not prove that the POSA would be
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`motivated to combine the alleged AAPA and Majcherczak to reach the claimed
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`invention. This is explained below.
`
`1.
`
`The Simulation Results Are Unreliable And Should Be
`Disregarded
`Dr. Horst’s supplemental declaration filed with the reply (Ex. 1018) contains
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`
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`numerous errors. For instance, the declaration shows simulation results for the
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`proposed Steinacker/Doyle/Park circuit that are identical to those for the
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`AAPA/Majcherczak circuit, even though the respective circuits have significant
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`differences, such as the 135-ohm resistor in Doyle. Compare results shown at
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`Ex. 1018, page 9, to results at page 15. Given these differences, the simulation
`
`results for the two circuits should not be the same, and the results are erroneous for
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`at least this reason.
`
`
`
`Recognizing this error, Dr. Horst prepared a corrective declaration including
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`a new set of graphs intended to replace those on page 15 of the supplemental
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`declaration. Ex. 2007. But even with the corrective declaration, Dr. Horst’s
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`simulation results are still littered with errors. For example, the results for Figure 4
`
`
`
`9
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`of the ’674 patent in the corrective declaration purport to show current flowing
`
`through a transistor “M2”:
`
`Ex. 2007 at 2. But the circuit simulated by Dr. Horst for Figure 4 of the ’674 patent
`
`contains no transistor labeled “M2”:
`
`
`
`
`
`
`
`10
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`Ex. 1018 at 14. Accordingly, it is not clear what current the “Is(M2)” waveform is
`
`intended to represent or whether it is even related to this simulation at all. Dr. Horst
`
`has not corrected this error.
`
`2.
`
`Dr. Horst Selected Unrealistic Parameter Values That The
`POSA Would Never Use In The Proposed
`AAPA/Majcherczak Combination
`A POSA starting with the alleged AAPA and the problems articulated therein
`
`
`
`would never use the parameter values selected by Dr. Horst for his simulations. His
`
`parameter values are unrealistic, and the simulation results therefore prove nothing.
`
`a.
`
`The FET Threshold Voltage Of 2.3V Causes The
`Problem Of Slow Detection Speed Described In The
`Alleged AAPA
`In Petitioner’s proposed AAPA/Majcherczak combination, the primary
`
`
`
`reference is the alleged AAPA, and Majcherczak is used only for the addition of the
`
`single feedback transistor M6. Paper 2 at 43-45. As described in Section III.A
`
`above, the “conventional solutions” of the alleged AAPA “have problems with
`
`leakage and switching times.” Ex. 1001 at 3:10-11. The Background section of the
`
`’674 patent specifically indicates that higher-threshold transistors address the
`
`problem of leakage current but result in an up/down detector with slow detection
`
`speeds. See id. at 2:63-3:11. Accordingly, the POSA starting with the alleged
`
`AAPA and seeking to add Majcherczak’s feedback resistor M6 would never
`
`implement the resulting up/down detector with higher-threshold transistors because
`
`
`
`11
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`that would result in an incomplete solution which fails to remedy one of the problems
`
`explicitly called out in the patent.
`
`
`
`Yet this is exactly what Dr. Horst did in his simulations: He selected FET
`
`threshold voltages that are unrealistically high and result in the problem of slow
`
`switching speed articulated in the ’674 patent. Dr. Horst’s simulations test the ability
`
`of the AAPA/Majcherczak circuit to detect power up and down of a 3.3V supply
`
`(Vcore). Ex. 1018 at ¶6. In the simulations, Dr. Horst “set a VTO value of 2.3 volts
`
`for the NMOS devices and negative 2.3 volts for the PMOS devices,” where “‘VTO’
`
`is the turn-on threshold of the transistor” (Ex. 2006 at 88:11-18):
`
`
`
`Ex. 1018 at 14.
`
`
`
`But a FET threshold voltage of 2.3V in an up/down detector with a 3.3V
`
`supply is much too high. Modern semiconductor processes generally allow for four
`
`types of FET threshold voltages: zero-, low-, standard-, and high-threshold. Zero-
`
`threshold voltage transistors have a threshold voltage of 0V. In a system with a 3.3V
`
`supply to be detected, low-threshold and standard-threshold voltages are in the range
`
`
`
`12
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`of approximately 0.7V or less. High-threshold voltages are generally around 1.0V
`
`or less. Dr. Horst’s selected threshold voltage of 2.3V is completely unrealistic, and
`
`a transistor with such an unreasonably high threshold voltage could only possibly be
`
`fabricated—if at all—by a foundry using special, non-standard processes. These
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`non-standard processes would be very expensive and incompatible with mainstream
`
`CMOS technologies. Also, the 2.3V threshold voltage would make the detector
`
`unsuitable for low-power applications since it would require a power supply voltage
`
`of at least 2.3V to even turn on any transistor, whereas state-of-the-art CMOS
`
`technology generally works with a supply voltage of 1V or less.
`
`
`
`Using this unrealistically high threshold voltage, Dr. Horst argues that the
`
`resulting up/down detector “does not show large ‘leakage current’ as predicted by
`
`Dr. Pedram.”3 Ex. 1018 at ¶26. Even if that is true, the detector would suffer from
`
`the precise problem articulated in the alleged AAPA for detectors employing high-
`
`threshold transistors: slow switching speeds. Dr. Horst’s declaration conveniently
`
`ignores any consideration of switching speed, and the slow switching speeds are not
`
`
`
`3 Dr. Horst’s simulation results do not support his argument. The results presented
`in the corrective declaration show that the power consumption of the proposed
`AAPA/Majcherczak circuit is approximately 12.5% higher than that of Figure 4 of
`the ’674 patent, i.e., ~450µW peak power versus ~400µW. Ex. 2007 at 2. It is thus
`clear that the proposed AAPA/Majcherczak combination addresses neither the
`leakage current problem nor the switching speed problem discussed in the alleged
`AAPA.
`
`
`
`13
`
`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`evident from Dr. Horst’s results, which use a relatively long time scale on the order
`
`of microseconds (µs), such that any switching delays are imperceptible. But the use
`
`of such a high threshold voltage—more than double what is generally considered to
`
`be “high-threshold” voltages—would undoubtedly have this problem. In any event,
`
`Dr. Horst’s use of the 2.3V threshold voltages results in a detector that does not
`
`detect a power-up event until the core voltage has ramped up to 3.0V, and that is
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`over 90% of the 3.3V operating voltage—unrealistically slow for an up/down
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`detector.
`
`
`
`In sum, the FET threshold voltage of 2.3V selected by Dr. Horst is unrealistic,
`
`and the POSA starting with the AAPA would never select this high-threshold value.
`
`b.
`
`Dr. Horst Selected Channel Length And Width
`Parameters From A Reference Unrelated To The
`Technology Of The Alleged AAPA
`In performing his simulations, Dr. Horst selected channel length and width
`
`
`
`values for transistors. Ex. 1018 at ¶7. Instead of selecting these values from a
`
`reference related to the technology of the alleged AAPA—i.e., “power-up/down
`
`detectors to generate a power-on/off-control (POC) signal,” see Ex. 1001 at 1:55-
`
`57—Dr. Horst chose values from a reference entirely unrelated to this technology.
`
`The POSA starting with the alleged AAPA and seeking to add Majcherczak’s
`
`feedback transistor M6 would never select the channel length and width values used
`
`in Dr. Horst’s simulations.
`
`
`
`14
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`

`

`IPR2018-01315
`U.S. Patent 8,063,674
`Dr. Horst’s declaration explains that “[w]here possible, [he] used channel
`
`
`
`length and width parameters based on the Voss reference (Ex. 1022) that was
`
`available prior to the critical date of the ’674 patent.” Ex. 1018 at ¶7. But aside
`
`from the fact that Voss was available prior to the filing date of the ’674 patent,
`
`Dr. Horst provides no reasoning or explanation as to why he selected parameter
`
`values from this reference. See generally id. Dr. Horst mentions that Voss discloses
`
`a power up/down detector (id. at ¶8), but Voss never refers to or describes any such
`
`power up/down detector. Rather, Voss is directed to a buffer for interfacing between
`
`a TTL circuit and a CMOS circuit. See, e.g., Ex. 1022 at 5:8-12.
`
`
`
`Dr. Horst provides no explanation for his decision to select parameter values
`
`from an entirely unrelated technology, and it appears that he did so merely because
`
`they provided results favorable to Petitioner.
`
`c.
`
`The Selected Parameter Values Are Divorced From
`Real-World Considerations
`Dr. Horst acknowledged at deposition that his computer simulations did not
`
`
`
`take into account various real-world considerations. For instance, it is well known
`
`that the threshold voltage of a transistor is determined by the manufacturer according
`
`to its minimum feature size (process) and supply voltage. Dr. Horst conceded,
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`however, that his simulations enabled him to choose any desired threshold voltage,
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`even if that voltage was inconsistent with the transistor’s minimum feature size and
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`U.S. Patent 8,063,674
`the supply voltage. Ex. 2006 at 93:3-13. And when asked whether his selected
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`threshold voltage of 2.3V would be typical for transistors having a 5V supply voltage
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`and a minimum feature size of 0.8 µm, Dr. Horst conceded that he chose the 2.3V
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`value simply because it “gave good results.” Id. at 94:5-13
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`
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`This testimony shows that Dr. Horst did not consider parameter values that
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`would be used in real-world settings, and rather, he selected values that “gave good
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`results” in his computer simulations. This is yet another reason why Dr. Horst’s
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`simulation parameters are unrealistic and prove nothing.
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`3.
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`Dr. Horst Cherry Picked Parameter Values Favorable For
`Petitioner Without Providing Any Rationale For Their
`Selection
`In a number of places, Dr. Horst selected parameter values for his simulations
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`
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`without providing any justification for his selections. For instance, Dr. Horst states
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`that he used length and width values from the Voss reference “for most NMOS and
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`[PMOS] transistors in [his] simulations.” Ex. 1018 at ¶8. Dr. Horst’s declaration
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`also states that “[a] different value was chosen for the width for the feedback P-
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`channel to make this transistor weaker than in the Voss circuit due to the difference
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`in the circuits.” Id. at ¶9.
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`
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`But the declaration provides no explanation as to why Dr. Horst only used the
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`Voss parameters for “most” transistors and not all of them. Likewise, the declaration
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`does not explain why he chose “[a] different value … for the width for the feedback
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`U.S. Patent 8,063,674
`P-channel to make this transistor weaker,” nor does the declaration explain which
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`alleged “difference in the circuits” necessitated this change. See id.
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`
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`At deposition, however, Dr. Horst explained the reason for changing the width
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`of the feedback transistor from what is described in Voss: If Voss’s parameters were
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`used consistently across the simulations—and not cherry picked and used for certain
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`transistors, but not others—then the simulation would fail. Ex. 2006 at 101:24-
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`102:17. This testimony crystallizes one of the key problems with Dr. Horst’s
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`simulations. He selects parameter values using a given methodology when they suit
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`his purposes—e.g., selecting parameters from Voss because it was “available prior
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`to the critical date of the ’674 patent,” see Ex. 1018 at ¶¶7-8—but then disregards
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`the methodology when its parameters do not yield his desired results. See also id.
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`(Dr. Horst stating, without any reasoning, that he used LTSpice default values for
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`some parameters and his own non-default values for other parameters).
`
`4.
`
`The Simulations Fail To Show That The
`AAPA/Majcherczak Combination Does Not Result In
`Increased Leakage Current
`Dr. Horst disputes Dr. Pedram’s showing (Ex. 2002 at ¶¶69-74) that the
`
`
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`AAPA/Majcherczak combination has a large amount of leakage current from VI/O to
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`VSS (ground). Ex. 1018 at ¶26. In an attempt to show that the AAPA/Majcherczak
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`combination has low leakage current, Dr. Horst’s simulations “show the core (input)
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`IPR2018-01315
`U.S. Patent 8,063,674
`voltage ramping from 0 to 3.3V and back to zero.” Id. at ¶8. This can be seen, for
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`instance, in the following panes from Dr. Horst’s simulation results:
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`
`
`
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`But ramping the Vcore up to a max value and then pulling it immediately back
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`down is not an accurate way of measuring leakage current. As Dr. Pedram explained
`
`in his declaration, in up/down detectors, leakage power is primarily a problem when
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`Vcore is high. Ex. 2002 at ¶¶72-73. Accordingly, one cannot accurately assess the
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`leakage current in an up/down detector by ramping down the Vcore voltage
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`immediately upon reaching its max value, as Dr. Horst did. To assess the leakage
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`current, Dr. Horst should have left the Vcore voltage at the 3.3V level for at least some
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`time. He did not.
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`5.
`
`The Single Simulation Result For AAPA/Majcherczak
`Reported By Dr. Horst Does Not Rebut Dr. Pedram’s
`Showing
`Dr. Pedram presented analysis based on fundamental circuit analysis
`
`
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`principles showing that the proposed AAPA/Majcherczak combination would have
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`multiple problems that would be recognized by the POSA. Ex. 2002 at ¶¶67-85.
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`Rather than rebut the substance of Dr. Pedram’s analysis, Dr. Horst presents results
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`IPR2018-01315
`U.S. Patent 8,063,674
`for a single computer simulation and argues that the problems “imagined” by Dr.
`
`Pedram are not present. Ex. 1018 at ¶¶21-31.
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`
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`But a single simulation result cannot provide an accurate indication of whether
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`a circuit would operate correctly under realistic, real-world conditions. Typically,
`
`engineers execute thousands of computer simulations to predict the operation of
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`circuits under various process, voltage, and temperature conditions and then do
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`testing on the fabricated circuits. In fact, Dr. Horst himself executed many more
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`simulations than he reported in his declaration. Ex. 2006 at 81:21-83:10, 93:23-
`
`94:4, 94:20-95:11, 102:11-19, 113:20-114:2, 116:21-117:2. Dr. Horst stated at
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`deposition, however, that he did not save the results for any of these unreported
`
`simulations. See id. Many of these simulations likely show inoperable circuit
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`results, and Dr. Horst conceded as much at deposition. See id. at 102:11-19 (“Q.
`
`When you ... conducted your simulations with a stronger Pchan2, the simulation
`
`failed; is that correct? A. Yes ….”).
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`
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`In the end, a single simulation result cannot rebut Dr. Pedram’s well-reasoned
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`analysis.
`
` Petitioner’s Extensive New Evidence And Argument Cannot Cure The
`Petition’s Failure To Show That The POSA Would Be Motivated To
`Combine Steinacker, Doyle, and Park
`In its petition, Petitioner provided just two short paragraphs explaining why
`
`
`
`the POSA would allegedly be motivated to combine Steinacker, Doyle, and Park.
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`Paper 2 at 21-22. In its Institution Decision, the Board stated that
`
`we have concerns regarding whether Petitioner’s arguments and
`evidence are based on impermissible hindsight…. Petitioner provides
`generic reasons for combining the various limitations.
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`Paper 7 at 38.
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`
`
`In reply, Petitioner submits new argument and over 30 paragraphs of expert
`
`testimony in an attempt to remedy the issues of its cursory motivation-to-combine
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`argument. Ex. 1018 at ¶¶3-20, 34-49. But a reply is too late to submit this kind of
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`extensive new evidence and argument. See Office Patent Trial Practice Guide,
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`August 2018 Update at 14 (“Petitioner may not submit new evidence or argument in
`