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`HORST - IPR2018-01315; -01316
`UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`---o0o---
`
`APPLE INC.,
`
`Petitioner,
`
`vs.
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`Cases IPR2018-01315; -01316
`U.S. Patent No. 8,063,674
`
`______________________________
`
`CONFIDENTIAL
`DEPOSITION OF ROBERT W. HORST, PH.D.
`VOLULME II
`BELLEVUE, WASHINGTON
`THURSDAY, AUGUST 8, 2019
`
`Reported by:
`DARCY J. BROKAW, RPR, CRR, CCR No. 3455
`JOB NO. 165495
`
`TSG Reporting - Worldwide 877-702-9580
`
`QUALCOMM EXHIBIT 2006
`Apple v. Qualcomm
`IPR2018-01315, -01316
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`HORST - IPR2018-01315; -01316
`UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`---o0o---
`
`APPLE INC.,
`
`Petitioner,
`
`vs.
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`Cases IPR2018-01315; -01316
`U.S. Patent No. 8,063,674
`
`______________________________
`
`CONFIDENTIAL
`DEPOSITION OF ROBERT W. HORST, PH.D.
`VOLULME II
`BELLEVUE, WASHINGTON
`THURSDAY, AUGUST 8, 2019
`
`Reported by:
`DARCY J. BROKAW, RPR, CRR, CCR No. 3455
`JOB NO. 165495
`
`TSG Reporting - Worldwide 877-702-9580
`
`QUALCOMM EXHIBIT 2006
`Apple v. Qualcomm
`IPR2018-01315, -01316
`
`
`
`Confidential
`
` HORST - IPR2018-01315; -01316
`
`Page 74
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` AUGUST 8, 2019
` 10:13 A.M.
`
` Deposition of ROBERT W. HORST, PH.D., Volume II,
`held at The Westin Bellevue, 600 Bellevue Way NE,
`Bellevue, Washington, before Darcy J. Brokaw, a
`Registered Professional Reporter, Certified Realtime
`Reporter, Washington Certified Court Reporter.
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` HORST - IPR2018-01315; -01316
`APPEARANCE OF COUNSEL:
`
` JONES DAY
` Attorneys for the Patent Owner:
` 901 Lakeside Avenue
` Cleveland, Ohio 44114
` BY: DAVID COCHRAN, ESQ.
`
` FISH & RICHARDSON
` Attorneys for the Petitioner:
` One Marina Park Drive
` Boston, Massachusetts 02210
` BY: WHITNEY REICHEL, ESQ.
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` HORST - IPR2018-01315; -01316
` ROBERT W. HORST, PH.D.,
` called as a witness, having been duly sworn,
` was examined and testified as follows:
` ---o0o---
`
` EXAMINATION
`BY MR. COCHRAN:
` Q. Dr. Horst, welcome back from the break.
` A. Thank you.
` Q. You understand you're still under oath?
` A. Yes.
` Q. I assume there's no reason you can't
`testify truthfully?
` A. That's right.
` Q. In between the last deposition and the
`five minutes starting this one.
` This deposition pertains to your
`Supplemental Declaration testimony in IPR2018-01315
`and IPR2018-01316, both relating to the '674 patent.
` Is that your understanding?
` A. Yes.
` MR. COCHRAN: I'm going to hand the
`witness what has been previously marked as
`Exhibit 1018 in IPR2018-01315.
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` HORST - IPR2018-01315; -01316
` (Deposition Exhibit No. 1018 marked for
` identification.)
`BY MR. COCHRAN:
` Q. Do you recognize this document?
` A. Yes. This is my Supplemental Declaration
`in the '674 patent.
` Q. Turn to page 40. Can you confirm that's
`your signature on page 40?
` A. Yes, this is my signature.
` I've also submitted a Corrective
`Declaration for one of the figures in this document.
` Q. Okay. I don't have that with me, so we're
`going to use this one.
` MR. COCHRAN: I'm also handing the witness
`what's been also marked as Exhibit 1018 in
`IPR2018-01316.
`BY MR. COCHRAN:
` Q. I'm going to ask you to identify if you
`recognize that document, Dr. Horst.
` A. Yes. I see this is the same declaration
`for the '674 patent but filed for the other IPR in
`this case.
` Q. The two exhibits are identical, correct?
` MS. REICHEL: Objection to form.
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` THE WITNESS: Yes, the two of these should
`be identical.
`BY MR. COCHRAN:
` Q. We're going to stick with the first one
`that I gave you so we don't have to use both, since
`it's the same document.
` If you'd turn to page 2 of Exhibit 1018,
`in section II.A. of your Supplemental Declaration.
` Starting at page 2 and continuing on
`through page 12, you discuss a SPICE, S-P-I-C-E,
`simulation of the proposed Steinacker/Doyle/Park
`combination, correct?
` A. Yes, this is referring to those SPICE
`simulations.
` Q. And more specifically, Dr. Horst, in
`section II.A., you compare a SPICE simulation of the
`Steinacker/Doyle/Park combination to a SPICE
`simulation of Figure 4 of the '674 patent, correct?
` A. Those simulation results are shown on
`page 9, yes.
` Q. Yeah. I was just asking: That's the
`content of section II.A. is the comparison of those
`two SPICE simulations, correct?
` A. That's part of what's disclosed in this,
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` HORST - IPR2018-01315; -01316
`yes.
` Q. Can you turn to page 4, paragraph 6.
` A. Okay.
` Q. In paragraph 6 of your Supplemental
`Declaration, you state:
` "The simulations use a power
` supply with VDD = 5 volts (VI/O) and
` test the ability of the circuit to
` detect power up and down of a 3.3 volt
` supply (Vcore). Power up is detected
` at 3 volts, and power down at
` 2.5 volts. MOSFET thresholds have
` been set based on these voltages, and
` all simulations of the '674 Figure 4
` circuit and prior art combinations use
` the same threshold settings."
` Correct?
` A. You read that correctly except that I had
`tildes in front of the voltages, so . . .
` Q. My --
` A. But I set the simulations to approximately
`detect those voltage levels.
` Q. Dr. Horst, in all of the simulations that
`you conducted, you set the MOSFET threshold values
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`so that the power up of a 3.3 volt supply is not
`detected until the supply voltage reaches
`approximately 3 volts, correct?
` A. Yes.
` Q. Why did you choose a 3.3 volt supply for
`Vcore?
` A. In Dr. Pedram's deposition, he was asked
`if the '674 patent should work in a system with
`5 volts and 3.3 volts input.
` So I used the voltages that he suggested,
`and then used a range of voltages around the
`3.3 volts that would be detected. So I set that at
`3 volts.
` Q. Did you perform any simulations for a
`5 volt supply for Vcore?
` A. I don't believe I did any simulations for
`5 volts. I -- instead, I used the suggestions from
`Dr. Pedram's report.
` My simulations are in response to his
`report and deposition that said that the circuit --
`the prior art circuits would have problems. And so
`I was doing the simulations to show whether or not
`there were any differences between the '674 circuit
`and the prior art circuits.
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` Q. Why did you choose a power-up detection
`threshold of approximately 3 volts for a 3.3 volt
`supply?
` A. From my experience, it's typical that you
`will specify a power supply with a tolerance of, in
`many cases, plus or minus 10 percent.
` So about a minus 10 percent from 3.3 volts
`is 3 volts. So a circuit should operate correctly
`anywhere from 3 to 3.3 volts, if that -- based on
`that assumption.
` Q. Did you perform any simulations using a
`power-up detection threshold other than 3 volts?
` A. As I was developing the simulations, I set
`the thresholds to different values; and sometimes
`they would trigger below 3 volts, and sometimes they
`would trigger above 3 volts, and so I picked the
`final parameters for the simulation based on
`parameters that would make it trigger at about
`3 volts.
` Q. How many simulations did you conduct using
`a power-up detection threshold of something other
`than 3 volts?
` A. I don't know how many I did. But in any
`kind of SPICE simulation, there's always an area of
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`process to get it to trigger or to perform the
`operation that you want it to perform.
` So I had a few different settings in the
`parameters, in particular the thresholds, until I
`got it to trigger 3 volts.
` Q. Did you save any of those results?
` A. Those results, I don't know if I saved
`any.
` Generally what I do is run SPICE like a
`spreadsheet, where it gives a simulation output; and
`then I change a variable and then run it again, and
`that changes the output again.
` But I don't save all those intermediate
`simulations.
` Q. So approximately how many simulations did
`you conduct?
` A. I don't know how many times I ran these,
`these circuits.
` Q. Ten?
` A. Each circuit -- it depended on which
`circuit it was. Sometimes I needed a couple of
`times to get it right; and other circuits, I needed
`a few more iterations. But I don't know what the
`total number would have been.
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` Q. Can you guess?
` MS. REICHEL: Objection to form. Calls
`for speculation.
`BY MR. COCHRAN:
` Q. I don't want you to speculate. Just give
`me an approximation.
` A. I don't think any of them had more than
`ten iterations before I zeroed in on the right
`values.
` Q. Okay. One of the design goals of a power
`up/down detector is fast detection time, correct?
` MS. REICHEL: Objection to form,
`foundation.
` THE WITNESS: The detection time is
`primarily determined by the speed of the input, the
`slew rate of the input, because the power supply
`changes very slowly.
` So the speed of the transistors that are
`recognized in that transition is almost
`insignificant compared to the -- the input voltage
`itself.
` So I would say that speed is not a primary
`goal in -- or not a primary driver to the circuit
`design.
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`BY MR. COCHRAN:
` Q. So if you were designing a power up/down
`detector, fast detection time would not be a concern
`to you?
` MS. REICHEL: Objection to form.
` THE WITNESS: Often power up/down
`detectors purposefully have a delay that may be,
`say, a millisecond or more delay, while the circuits
`operate at nanoseconds.
` So the circuit may be a million times
`faster than the result signal that you're trying to
`generate. So speed would not be a main
`consideration in designing a circuit.
`BY MR. COCHRAN:
` Q. Okay. Dr. Horst, do you agree that
`improving detection speed is one of the goals of the
`'674 patent?
` MS. REICHEL: Objection to form.
` THE WITNESS: There's some discussion of
`the detection speed in the '674, but there are no
`claims related to detection speed.
` So I would say that in terms of the patent
`claims, it's not an important factor.
`BY MR. COCHRAN:
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` Q. But it's described in the patent document,
`correct?
` A. There is some discussion in the patent.
`I'd like to see a copy of the '674 to fully answer
`that question.
` Q. Can you turn to page 7 of Exhibit 1018.
` A. Okay.
` Q. At the bottom of page 7, there are two
`circuit diagrams -- well, several circuit
`diagrams -- which you state are diagrams of the '674
`Figure 4 circuit and the Steinacker/Doyle/Park
`circuit, correct?
` A. Yes. These are from my SPICE simulations.
` Q. How were these diagrams created?
` A. When I run the SPICE simulations, I put it
`in two windows on the system; the left window has a
`schematic, and the right window has the output
`waveforms.
` So I did a -- I captured the image from
`the left side for the circuits and from the right
`side for the waveforms. And here, these are
`actually two different captures in this figure that
`were just put into the same figure.
` They almost look like they're the same
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`simulation, but they're not.
` Q. So, but is this like a screenshot from
`your computer system?
` A. Yes.
` Q. And did you perform the SPICE simulations
`yourself?
` A. Yes.
` Q. Did anyone help you?
` A. No.
` Q. And did you select all the parameters for
`the simulations yourself?
` A. I selected the parameters based on
`Dr. Pedram's input and some prior art literature,
`particularly Voss, that specified transistor
`sizings, and then made the final adjustments to make
`the circuit operate correctly.
` Q. On the left-hand side of the figure on
`page 7 is a diagram of a SPICE simulation you
`performed for Figure 4 of the '674 patent, right?
` A. Yes.
` Q. And at the bottom of the Figure 4
`simulation diagram, there are a number of
`programming statements, including three ".model"
`statements, correct?
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` A. Yes.
` Q. The ".model" statements set the parameters
`for the transistors in the circuit under simulation,
`correct?
` A. Yes.
` Q. And specifically the ".model Nchan1"
`statement sets parameters for both M6 and M7 in the
`Figure 4 simulation, correct?
` A. Yes.
` Q. And the ".model Pchan1" statement sets
`parameters for both M4 and M5, correct?
` A. Yes.
` Q. And the ".model Pchan2" statement sets
`parameters for the feedback transistor M8, correct?
` A. Yes, that's correct.
` Q. Do these model statements represent a
`mathematical model of the transistors in simulation?
` A. The SPICE program has a built-in model for
`MOSFETs with some default parameters, and the
`parameters that can't use the defaults can be
`explicitly set.
` So this sets a few of the parameters, and
`the rest of the parameters are at the default
`values.
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` Q. Are these .model statements based on any
`real-world physical semiconductor processing?
` MS. REICHEL: Objection. Form.
` THE WITNESS: The model statements for
`Nchan 1 and Pchan1 used the width and length
`parameters from the Voss reference. The thresholds
`are adjusted to make the circuit trip appropriately
`at the 3-volt level.
`BY MR. COCHRAN:
` Q. In each of the .model statements, you have
`set a VTO value of 2.3 volts for the NMOS devices
`and negative 2.3 volts for the PMOS devices,
`correct?
` A. Yes.
` Q. And "VTO" is the turn-on threshold of the
`transistor, correct?
` A. Yes.
` Q. The pulse statement sets parameters for
`V2, which supplies the Vcore voltage, correct?
` A. Yes. That's the voltage source that makes
`the input rise and fall, to see the reaction of
`different voltage levels.
` Q. In the pulse statement here in Figure 7 --
`page 7, sorry -- you set the maximum Vcore value at
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`3.3 volts, correct?
` A. In this particular simulation, I did. In
`others, I varied and showed variations around
`3 volts, for instance.
` Q. Underneath the .model statements, there is
`a statement that says ".tran 10u."
` A. Yes.
` Q. What is that?
` A. The -- it's actually 10u or micro. So
`that's saying to run the simulation for a total of
`10 microseconds.
` Q. On this same diagram, below the inverters
`A1 and A2 on the left-hand side, there are six
`parameters: Vhigh, Vlow, Ref, Trise, Tfall, and Td.
` Do you see that?
` A. Yes.
` Q. What do those parameters do?
` A. They determine the high value of the
`inverter. So that when it's driving a high value,
`it would drive to 5 volts; the low value, it will
`drive to low -- to zero volts.
` And the reference is 2.5 volts, which
`means that when the input crosses 2.5 volts, it will
`switch the inverter.
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` And then the rise and fall and delay are
`all set to 5 nanoseconds just so that there are not
`instantaneous changes that could affect the
`simulations.
` Q. And how did you determine those values?
` A. Typical for CMOS is to have the threshold
`set at half of the -- the voltage. So this is a
`5-volt circuit, so I made the threshold half of the
`5 volts.
` Q. On the right-hand side of the figure on
`page 7 is a diagram of the SPICE simulation you
`performed for the Steinacker/Doyle/Park combination,
`right?
` A. Yes.
` Q. At the bottom of this figure are the same
`programming statements, including three .model
`statements, correct?
` A. Yes.
` Q. And here, the ".model Nchan1" statement
`sets parameters for both transistors P17A-1 and
`P17A-2, correct?
` A. Yes, that's right.
` Q. And the ".model Pchan1" statement sets
`parameters for both N16A-1 and N16A-2, correct?
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` A. That's right.
` In this simulation, I labeled the
`transistors based on the labels in the Doyle
`reference, and that's why they have different names
`than in the '674 circuit.
` Q. And the ".model Pchan2" statement sets
`parameters for the feedback transistor P18A,
`correct?
` A. Yes, that's right.
` Q. In the Steinacker/Doyle/Park diagram on
`the right-hand side, below the two inverters, are
`three parameters: Vhigh, Vlow and Ref.
` Do you see that?
` A. Yes.
` Q. Why does the Steinacker/Doyle/Park
`simulation not include the Trise, Tfall, and Td
`parameters that are included in the Figure 4
`simulation?
` A. Those were set to the same values, it
`looks like. When you print out a schematic, there's
`an option to show those parameters or not, and it
`looks like I neglected to flag those to be
`displayed.
` Q. The ".model Pchan1" statement in the
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`Steinacker/Doyle/Park simulation sets a transistor
`width, W, of 2.5u, micros, correct?
` A. Correct. That Pchan1 model is set at
`2.5u, yes.
` Q. So that means the transistor width for
`both P17A-1 and P17A-2 in your simulation is set to
`2.5u, correct?
` A. Yes.
` Q. If you look at the Figure 4 simulation on
`the left-hand side, the ".model Pchan1" statement
`sets a transistor width, W, of 5u for both M4 and
`M5, correct?
` A. Yes.
` Q. So the transistors M4 and M5 in your
`simulation in Figure 4 are twice the size of P17A-1
`and P17A-2 in your simulation of the
`Steinacker/Doyle/Park circuit, correct?
` A. Yes. The halving of the width parameter
`is done because of the Park reference, which says
`that when you replace a single transistor with a
`pair of series transistors, you should cut the width
`in half.
` Q. In each of the .model statements, you set
`the transistor length to 0.8 micro, correct?
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` A. Yes.
` Q. This 0.8 micro transistor length is the
`minimum feature size for the transistors in your
`simulation, correct?
` A. Yes.
` Q. And the VTO value for a transistor is
`dependent on the minimum feature size and supply
`voltage, correct?
` A. In this simulation, you can directly set
`the threshold value. So the threshold is forced by
`the VTO statement and not dependent on the -- on
`that minimum feature size parameter.
` Q. Setting the VTO to 2.3 volts, is that
`consistent with transistors operating at 5 volts and
`having a minimum feature size of 0.8 micros?
` A. These are the parameters I took from the
`Voss reference. I could have used other width
`parameters. And the circuit will function the same
`or nearly the same at different width and length
`parameter sizes as long as you keep the
`width-to-length ratio the same.
` Q. Did you perform any of those simulations?
` A. As I was developing the simulations, I did
`try some other sizes and found simulations would
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`produce about the same results.
` Q. Did you save those results?
` A. No.
` Q. Are you aware of any existing technology
`with this high VTO value for transistors operating
`at 5 volts with this small of a minimum feature
`size?
` A. I didn't look at the different types of
`transistors for different voltage values. I picked
`one set which gave good results or the expected
`results for the '674 circuit, and then I stuck with
`the similar parameters for the prior art circuits.
` Q. If the transistor has a VTO of 2.3 volts
`and it's using a 5-volt source, isn't it true that
`there's very little noise margin for a transistor of
`that design?
` A. That isn't something that I evaluated in
`my simulations.
` Q. Did you try other VTO values, other than
`2.3 volts, when you were simulating circuits?
` A. Yes. In each of these circuits, I varied
`the VTO values to adjust the places where it would
`trigger, to make the triggering level at about
`3 volts.
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` Q. And what were the different values that
`you used?
` A. I don't remember what they were. Usually
`varied it by a couple tenths of a volt up and down
`and maybe somewhere between 3 volts and 2 volts.
` Q. Did you save those results?
` A. No. Those results are very easy to run.
`Once you have the simulation running, it's like a
`spreadsheet where you can just change numbers and
`see what the -- what the results are.
` Q. For transistors operating at 5 volts with
`this minimum feature size, 0.8 micros, wouldn't it
`be more typical to have a threshold voltage of
`1 volt?
` A. There are some circuits where you would
`have a low threshold and some circuits where you'd
`have a higher threshold.
` And the '674 circuit -- or the '674 patent
`doesn't give you any guidance on how to pick these
`different parameters. So I picked some that made
`the circuit operate as expected.
` Q. Did you perform any simulations with a V
`turn-on voltage closer to 1 volt?
` A. I don't remember trying to make it work at
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`such a low voltage, since that wouldn't be typical
`for a 3.3-volt circuit.
` Q. So for a 3.3-volt circuit, it would not be
`typical to have a turn-on voltage of 1 volt?
` A. I did the simulations based on an
`assumption that it was a 3.3-volt circuit that
`needed to trip around 10 percent of its maximum --
`or 90 percent of its maximum value, and so I
`didn't -- I wasn't trying to explore the entire
`space of the way these circuits could be designed.
` I was looking to see if the problems that
`Dr. Pedram reported actually occurred in these
`circuits. And I didn't find those problems.
` Q. Can you turn to page 5 of your
`Supplemental Declaration, specifically paragraph 7.
` In paragraph 7, about two-thirds of the
`way down, you state:
` "Where possible, I used channel
` length and width parameters based on
` the Voss reference (Exhibit 1022) that
` was available prior to the critical
` date of the '674 patent. For other
` parameters, such as transconductance,
` I relied on the LTSpice default
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` settings."
` Do you see that?
` A. Yes.
` Q. Now, here are you referring to the
`parameter settings used in the SPICE simulations
`throughout the report, or only the simulations shown
`on page 7?
` A. This is specifically referring to the ones
`on page 7. In most cases, it applies to the other
`simulations, but not in all cases.
` Q. Okay.
` MR. COCHRAN: I'm going to hand the
`witness what has previously been marked as
`Exhibit 1022.
` (Deposition Exhibit No. 1022 marked for
` identification.)
`BY MR. COCHRAN:
` Q. Do you recognize this document?
` A. Yes. This is the Voss reference I was
`referring to earlier.
` Q. And you've studied the Voss reference?
` A. I have read through it briefly, but I
`primarily just used it for the scaling parameters
`for the P- and N-channel transistors.
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` HORST - IPR2018-01315; -01316
` Q. Can you please refer to column 5 in the
`text of Voss, starting at around line 48, which is
`towards the bottom of the left-hand side.
` I'm going to ask you to read -- just read
`to yourself column 5, starting at line 48, where it
`says "The size of transistors P2, N2 and N4," and go
`all the way down to the bottom.
` A. Yes.
` Q. You're a fast reader.
` This paragraph in Voss specifies the
`channel width and length for a number of
`transistors, correct?
` A. Yes.
` Q. And if you turn to Figure 3 of Voss, these
`are the same transistor channel width and length
`parameters shown in Figure 3, correct?
` A. It's describing at least some of the
`Figure 3, yes.
` Q. Are these transistor channel width and
`length parameters the same ones that you referred to
`in your Supplemental Declaration when you wrote:
` "Where possible, I used channel
` length and width parameters based on
` the Voss reference"?
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` A. Yes. There, I was specifically referring
`to the stage 1 of the Voss reference, those -- that
`input P- and N-channel.
` Q. Could you turn to column 5, back to column
`5 of Voss, line -- starting on line 10.
` The Voss patent states, at column 5, line
`10:
` . . . "the present invention has
` application for use as a TTL address
` buffer to convert TTL input signals to
` CMOS-compatible levels."
` Do you see that?
` A. Yes.
` Q. And if you look down in column 5, around
`line 52, toward the bottom, Voss states "in a
`preferred embodiment of the present invention;" and
`then he goes on to specify the transistor width and
`length parameters that we've been discussing that
`you used to do your simulations, correct?
` A. Yes.
` Q. The parameters specified in Voss that you
`relied on in your simulations were selected for
`Voss's preferred embodiment, correct?
` A. These are values that Voss selected for at
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`least one of the preferred embodiments.
` Q. Could you turn back to your Declaration,
`page 7.
` In the simulations shown on page 7, the
`PMOS and NMOS channel length that you used of 0.8
`micros were selected based on Voss, correct?
` A. I selected them based on the input stage
`of Voss.
` Q. And the NMOS channel width value of
`25 micros and the PMOS channel width value of
`5 micros were selected based on Voss, correct?
` A. It say the two values, I got that from
`Voss.
` Q. In paragraph 9 of your Declaration, in the
`figures, you state a different value was chosen for
`the width of the feedback P-channel to make this
`transistor weaker than in the Voss circuit due to
`the difference in the circuits.
` Do you see that?
` A. Yes.
` Q. And here you're referring to your
`selection of a width of 1 micro for Pchan2 in both
`the Figure 4 simulation and the
`Steinacker/Doyle/Park simulation; is that right?
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` A. That's right.
` Q. And when you wrote that a different value
`was chosen for this feedback transistor to make it
`weaker than in Voss, what transistor in the Voss
`circuit are you referring to?
` A. This transistor is weaker than all the
`transistors in the Voss circuit.
` Q. Does Voss have a feedback transistor?
` A. Voss has a feedback transistor, but it
`doesn't operate quite the same because of some other
`parts of the circuit.
` So I didn't completely analyze the way the
`Voss circuit would work here. I was just concerned
`with picking values that would make the '674 circuit
`operate correctly.
` Q. Well, what is the -- referring back to
`Voss, Figure 3, what is the feedback transistor in
`Voss?
` A. There's a feedback transistor, P3, but its
`gate is separately controlled. So it's not
`automatically inserted and removed as are the '674
`and the prior art circuits.
` Q. Why did you need to make Pchan2 in your
`simulations weaker than in the Voss circuit?
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` A. When I ran the '674 circuit with a
`stronger Pchan2, the circuit fails to operate
`completely. So the circuit does not detect the
`power on because the Pchan2 current is too high, and
`it's fighting with the two N-channel transistors.
` So you have to adjust these parameters in
`such a way that the voltage divider formed from the
`P-channel and N-channel give a transition voltage to
`the inverter at the right point.
` Q. When you simulated -- when you conducted
`your simulations with a stronger Pchan2, the
`simulation failed; is that correct?
` A. Yes, the '674 failed. And I don't
`remember if I ran it with the other circuits, but
`it's -- you have to have a weaker feedback
`transistor for this type of circuit to work.
` Q. Did you save those results?
` A. I don't believe so.
` Q. Can you turn to page 8 of your
`Declaration, paragraph 12.
` In paragraph 12, you state:
` "The strength of the stacked
` P-channel transistors has been set
` according to Park. When replacing the
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` Doyle P-channel with Park's pair of
` stacked transistors, the W/L
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