A Sequence Independent Power-on-Reset
`Circuit for Multi-Voltage Systems
`
`Qadeer A. Khan, G.K.Siddhartha
`Freescale Semiconductor, Noida, India
`{siddhartha.gk3freescale. com
`current consumption associated with the generation of POR
`Abstract- With the advent of multiple supply domains on a
`signals for use in battery operated applications.
`single chip, issues related to power sequencing are becoming a
`major hurdle for system designers. Existing POR strategies fail
`to cope up with these issues. We propose a scheme in which the
`power on reset generation is independent of the sequence of
`supply ramp-up. The circuit implementation of the proposed
`methodology has been realized for a dual supply system. The
`basic circuit is modified so as to consume zero static current.
`An attempt to reduce any leakage current during supply
`rampup has also been made successfully. Simulation results
`verify the sequence independence concept and low power
`consumption. Further the proposed realization is modular
`enough to be extended for more number of supplies.
`
`Fig. 1 shows the above scenario in a general perspective
`with 'n' number of supplies. It is clear from the figure that
`the signal RESET (assumed to be active LOW) is not driven
`till the last supply VDDn does not ramp-up. The dotted lines
`show the region (POR Region) where the RESET is driven
`and recognized by different supply domains.
`
`1.
`INTRODUCTION
`Many integrated
`voltage
`multiple
`utilize
`systems
`domains [1], i.e., the different parts of the chip operate at
`different power supply voltages. When a digital circuit is
`powered up, it is usually reset to establish a predetermined
`state (i.e., initial digital values are populated in registers,
`memory, etc.).
`For chips
`containing
`multiple
`voltage
`domains, some existing POR (Power-on-Reset) techniques
`only detect the ramp-up of the power supply that occurs last
`in time. Until this time, however, the state of the POR signal
`or signals is undetermined. This may lead to unexpected
`behavior of the chip, such as contention in tri-state logic
`and/or undesirable R/W operation of memory
`circuits
`circuits. All such conditions can lead to excessive and
`undesirable current consumption. The need for multi-voltage
`supervision and voltage detection mechanism is addressed in
`[2]. Some other POR techniques are shown in [3-7] but they
`are either sequence-dependent or detect a single supply with
`reference to the other. Since the ramp-up sequence of such
`circuits needs to be predefined, a random power-up sequence
`may lead to system failure. Some designs also use separate
`POR circuits for different supply domains. This can also lead
`to synchronization issues between them.
`Accordingly,
`it
`is
`desirable
`to have
`sequence
`a
`independent POR methodology for use in a multi-voltage
`architecture. In addition, power supplies have large ramp-up
`times
`and hence
`it
`is
`desirable
`to have
`circuit
`a
`implementation that minimizes steady state and dynamic
`
`_
`
`_
`
`l
`
`5
`
`I
`
`*VOD1
`
`Vci
`
`RESET
`
`+
`I
`
`POR Region
`
`Figure 1. Waveform showing conventional POR Methodology
`Till then ti
`the last supply VDDn appears the RESET is
`not driven to any logic level. Also, if the ramp-up sequence
`is changed, some supply domains may not be able to register
`a valid reset and will malfunction.
`111.
`PROPOSED PORMETHODOLOGY
`Fig. 2 shows the proposed POR methodology where the
`resetgeneration is sequenceindependent. UnliketheRESET
`waveform in Fig. 1 the RESET is asserted LOW as soon as
`any supply appears and hence avoids the hazards mentioned
`
`0-7803-9390-2/06/$20.00 ©)2006 IEEE
`
`1271
`
`ISCAS 2006
`
`1
`
`APPLE 1015
`
`

`

`in Section I. The RESET is de-asserted at the ramp-up of the
`last supply.
`
`/
`
`I _
`
`_
`
`Thus, the POR remains asserted if any of the supply is
`absent. POR is de-asserted when all the supplies are ramped
`up. POR Thresholds can be adjusted by appropriate sizing of
`the transistors. The drawback of this circuit is that if the
`voltage levels of vddl and vdd2 are not equal, there will be
`isteady state power consumption in the circuit once both the
`supplies ramp up. This power consumption is proportional to
`the difference between the two supplies and is hence not
`suitable for low-power applications. To reduce the static
`\power consumption, it is required to add control circuitry to
`the PMOS gates of the circuit in Fig. 3 to ensure that the
`pull-up paths are completely turned off once all the supplies
`are ramped up.
`
`Sequence Independent
`
`,,,,,,,,--------
`
`ss>L/
`
`|
`
`VDD1VDD2/..N.NDDn
`
`VDD2I...NDDnNDI
`
`VDDnNDD1NDD2L... .__/_
`
`RESET _
`
`RESET
`
`driven low
`driven low
`~-POR Region
`
`Low POWER IMPLEMENTATION
`V.
`I--------~~~~ | S Fig. 4 shows the POR circuit with control circuitry for
`two-supplies. Assuming vdd2 ramps-up first. Node nl is
`pulled LOW by M5 and PMOS MI turns OFF. Due to
`capacitive coupling (CO) the node n2 follows vdd2, output of
`inv2 goes LOW and hence the PMOS MO charges output
`node por out to logic HIGH. When supply vddl ramps up,
`M4 pulls node n2 LOW and hence output inv2 goes HIGH
`turning OFF MO. NMOS M2 and M3 turn ON and por_out
`goes LOW. At steady state, both PMOS are OFF and there is
`no path from supplies VDDl and VDD2 to ground. Since the
`circuit is symmetric w.r.t. VDDl and VDD2 the sequence of
`supplies will not affect the operation thus making the circuit
`independent of supply ramp-up sequence. The inverters, inv3
`and inv4, are used to level shift the node por_out to the
`respective supply domains.
`Ydd2
`
`Figure 2. Waveform showing Proposed Reset Methodology
`
`IV. NAND LOGIC AS A POR
`The basic implementation of the proposed methodology
`can be realized using a dual-supply NAND gate as shown in
`Fig. 3. As shown in Table 1, if one input is 0 (Logic LOW),
`the output is l(Logic HIGH) and only when all the inputs are
`1 (Logic HIGH) the output switches to 0 (Logic LOW).
`When none of the supplies are present, the node POR_OUT
`remains floating.
`
`vdd2
`
`vddl
`
`vdd1l d MO
`
`Ml Ivdd2
`
`porouL. porro
`
`vddl-I; M2
`
`dd2Q-
`
`hM3
`
`vddl
`
`CO
`
`n2
`
`vl
`irh'2
`
`--I MO Ml
`
`vddl-
`
`vdd2-
`
`M2
`
`M3
`
`Cl
`
`M
`
`-vdd
`
`out_vddl
`out_Add2
`
`n
`n
`
`inrvl
`
`vddl
`
`Ydd2
`
`Figure 3.
`
`Basic NAND gate structure as multi-voltage POR.
`
`Figure 4.
`
`Dual Supply POR with Zero static current consumption
`
`TABLE I.
`VDD1
`1
`1
`o______
`o°o
`
`LOGIC TABLE FOR NAND GATE AS A POR
`POR OUT
`VDD2
`1
`1
`0
`0
`i
`0
`l______
`o_____
`x
`
`o
`
`Though circuit in Fig. 4 does not consume any steady
`state current, there exists a path between the two supplies,
`during the period when only one supply is ON and the other
`is not present (ground), through MO and Ml. To avoid this
`situation, the circuit in Fig. 5 has PMOS M6 and M7 to
`cutoff the direct path between the two supplies during ramp-
`~~~~~~~~~~up.Now, consider a situation when the node por_out is high
`indicating that only one of the supplies has ramped up. The
`body diodes ofthe PMOS pull up structure ofthe supply that
`is not ramped up can get forward biased and cause a huge
`
`1272
`
`2
`
`

`

`drain from the supplies. Thus, even though M6 and M7 turn
`OFF, their body diodes conduct and create a leakage path.
`To prevent this body leakage, an adaptive body bias scheme
`5, the body is
`has been employed. As shown in Fig.
`dynamically switched from the output voltage level (when
`only one supply is present) to the respective supply voltage
`level by controlling PMOS transistors M8 and M9.
`
`porout
`
`out Ydd2
`
`vdd2
`
`edd1+ 104
`
`Ms
`
`F eddd
`
`°-ddl
`
`437.857n
`
`..0
`
`1.676u
`
`901.471u
`1.6
`
`1.6
`
`.1
`
`bvd2
`
`Vdd21q
`
`bvddl
`
`outvdd
`
`1-2"2.274m
`vddl
`
`-
`
`1
`
`-
`
`_
`
`_1
`
`.1
`
`b~~~~~~~~~~~~~~~~~~~~fme(msec)
`
`8.841 m -~1
`
`wavout-~
`
`Figure 7. POR response with ramp-up sequences.IVDD > VDD2
`
`n
`
`J
`
`L_
`
`-391.11.1
`
`vddl9'30
`RSLT
`invATO
`VI.r
`1.1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11.~F
`l
`Thecircuitswereimplemented in 90nm CMOS Bulklt00
`166
`u_d12f|
`hwte
`ig
`Process and siulte inSIE ig
`n
`POLOUV~~~~~~~~~pM8vdd2-] M3~ ~ ~ ~~ ~~~~oA dd
`bvddl
`o_d2437.857n
`
`vdd2
`
`~~~~~~~~~~~~1.623n
`
`2216
`
`Figure 5.
`
`Dual Supply POR with Ultra low current consumption
`
`Frd2
`2ffil l
`
`vddlf
`
`l
`
`lltl
`
`ouvdladl ou d2rmanas edLWwe ayo
`SimuLATioN RiESULTS
`VI.
`The circuits were implemented in 9Onm CMOS Bulk
`Process and simulated in SPICE. Fig. 6 and Fig. 7 show the
`waveforms with two different ramp-up sequences. It can be
`inferred that irrespective of the sequence, the reset signals
`out_vddl and out_vdd2 remain asserted LOW when any of r 1 6vdd2 4/
`ly s not present and de-asserts only after both the
`supplies have ramped up. From Fig. 8 it can be seen that the
`cuffrent drawn from the supplies is negligible during and after
`power up. Fig. 9 shows simulation results for the adaptive
`body-biasing technique employed.VDD2
`
`ou
`
`ddl
`
`I.7u
`
`1.1
`
`Ume (msec)
`
`.61.6
`
`_
`
`Fgr .Wvfrssoigcretcnupinwt
`Fu8W ef
`ng curn consumpti with ramp-ups
`
`oth
`
`suppl
`
`is
`
`out vdd2
`
`out vddl
`
`vddl
`
`1.745u
`
`n.0
`
`por out
`
`901.475u
`
`1.6
`
`-12731.6
`~~~~~~~~~~~~~~~~~~~~~~~~~bulk_Vdd2
`
`.3i .75L.rbuk7dd9m,
`
`vdd2
`
`1.6
`
`1.6
`
`1.6
`
`~~~~~~1.6
`
`1.6
`
`vdd2
`
`~~~~~~~~~~~~~~~~~~~~~~~~~~~~por out
`
`1.1~~~~~~~~~~~~~~~~.9
`
`.6
`
`1.6
`
`bulk_vddl
`
`vddl
`
`_
`
`_
`
`3
`
`

`

`EXTENSION FOR MORE THAN Two SUPPLIES
`VII.
`Fig. 10 shows the modularity of the circuit by using two
`dual-supply POR circuits (shown in Fig. 4 and Fig. 5) to
`realize a quad-supply POR circuit. The outputs of the
`individual dual-supply POR circuit are combined in a Sync
`Logic that synchronizes all the resets such that they are
`deasserted at the same time while maintaining the sequence
`independent nature of the circuit. The same architecture can
`be used for a tri-supply POR circuit by grouping vdd3 with
`vdd2 or vddl in the second dual-supply POR circuit.
`
`u
`
`vcpor outd12
`
`u py r ;
`
`POR;tCircu:MitOUt Cdd2
`I
`
`_
`
`Ir-
`
`> > > >
`
`N
`
`|1tv d
`
`|Sync| rst_vdd2
`Logic
`rst vdd13
`
`Dual Supply
`POR Circuit
`
`out_vdd3
`out vdd4
`
`rst vdd4
`
`vd D
`
`vIdd
`
`X d3
`
`vdd4
`
`If vddl ramps up later in time with respect to other
`supplies, it is ensured that the signal rst vddl goes low as
`soon as vddl ramps-up. Thus, once all the supplies ramp-up
`andpor_out_12 goes high and out_vdd3/out vdd4 goes low
`reset de-asserts. All the Sync structures are similar and
`operate in the same fashion. As soon as any supply ramps up,
`the reset cor espondig to that supply gets asserted. The reset
`de-asserts only when all the supplies ramp-up. The circuit
`avoids any kind of static current consumption due to
`difference in the levels ofthe supplies.
`p; =,Fig. 12 shows the generalized Sync Logic structure for it
`supply (where i =1 to n; and n is the number of supplies).
`The operation is similar to the circuit in Fig. 11.
`
`vddi
`
`-- ------------------ -
`
`:trll_vddi
`MP1 jL
`~~~~~~~~~~~~MPI
`:ctrln
`MPn'
`M
`
`C
`
`vddi
`
`por out3grp_i-j
`
`rst_vddi
`
`1
`
`M
`
`1
`
`MNI0
`
`LMN1nMNl
`,
`
`out vddk
`
`M
`
`o
`
`Figure 10. POR Generation for Four Supplies using Dual Supply POR
`
`I
`
`Fig. 11 shows the circuit implementation of Sync Logic.
`It consists of four similar structures to generate the resets
`rst_vddl, rst_vdd2, rst_vdd3, and rst_vdd4 at the respective
`supply levels. It primarily contains a NOR gate logic and
`uses the outputs generated from the two Dual Supply POR
`circuits. Consider the Logic portion
`for generation of
`rst vddl. Initially, if vddl ramps-up first, then por out 12
`goes HIGH. Also capacitor C couples the supply to
`ctrl_vddl and is latched at vddl level. Thus, the node
`rst_vddl goes low. Now, if vdd2 ramps-up por out 12 goes
`low, but since ctrl_vddl is latched, rst_vddl remains low.
`Else if vdd3/vdd4 ramp-up, outcvdd3/out_vdd4 goes high so
`signal
`as to turn off the pull-down NMOS receiving
`out_vdd3/out_vdd4 at the gate, but since por_out_12 is high
`rst t-vl remains low,
`rst-vddl remains low.
`
`vddl
`
`vdd2
`
`VIII. CONCLUSION
`A sequence Independent POR methodology suitable for a
`multi-supply domain IC's has been presented. The concept
`ensures the reset synchronization between multi voltage
`domai s. The POR iS driven at the appearance of the very
`first supply and prevents any malfunctioning of the chip.
`This eases post-silicon testability and can be used to arrive at
`the optimum power-up sequence after fabrication of the chip.
`The technique has been successfully implemented for dual-
`supply with zero static current and negligible dynamic
`current. The circuit implementation is modular in nature and
`can be easily extended for more than two supplies.
`
`por_out12
`
`st vddl
`
`vdd3
`
`c
`
`=I|
`
`por._out 12
`>,4
`
`rstvdd2
`
`c
`
`=0
`
`out_vdd4
`
`;
`
`v
`
`=p} out_vdd3ffi
`
`ffi
`
`vdd4
`
`p1 out vdd3
`out vdd4
`
`_vdd3rn
`por_out_34-t>
`
`_C
`
`-.c
`arl-ut 34
`pov Out 34
`rst_vdd4
`< or_ou_34_
`out vddl
`out_vdd2
`
`Figure 11. POR Sync Logic for 4 supplies
`
`1
`
`[1]
`
`[2]
`
`[7]
`
`1274
`
`REFERENCES
`Jui-Ming Chang; Pedram, M., Energy minimization using multiple
`|supply voltages, IEEE Transactions on Very Large Scale Integration
`(VLSI) Systems, Volume 5, Issue 4, Dec. 1997 Page(s):436 - 443
`URL:http://www.commsdesign.com/design_corner/showArticle.jhtml
`?articleID= 16502296
`Circuit for independent power up sequencing of a multi voltage chip,
`[3]
`--cIntel Corporation, US06236250, Salmon et. al., May 22, 2001.
`Powerup sequence artificial voltage supply circuit, ATI International
`[4]
`t_wdSRL, US6160430, Drapkin et. al., Dec. 12, 2000.
`Supply
`Voltage
`Circuit,
`[5]
`Detection
`Altera
`US6870400B1, Chong et
`al., March22, 2005
`out vddl
`[6] PwrUp! oe Down Deeto Cirui, Msad echloie
`out_vdd2
`Limited, Hong Sek Kim, US6593790B2, July15, 2003
`Power Up detection with low current draw for dual power supply
`circuits, US6853221B1, National Semiconductors, Wert, D. Joseph,
`Feb8, 2005
`
`Corporation,
`
`4
`
`