`
`
`4.2
`A New Technique for Standby Leakage Reduction in High-Performance Circuits
`
`Yibin Ye, Shekhar Borkar and Vivek De
`Microcomputer Research Labs
`Intel Corporation, Hillsboro, OR 97124, USA
`
`Abstract
`time constant (Fig. 4) is, therefore, determined by 1) drain-
`bodyjunction and gate-overlap capacitances per unit width, 2)
`A new standby leakage control technique, which exploits the
`the input conditions immediately before the stack transistors
`leakage reduction offered by transistor stacks with “more than
`are turned ‘off’, and 3)
`transistor
`subthreshold leakage
`one ‘off’ device”, demonstrates 2X reduction in standby
`current, which depends strongly on temperature and Vt.
`leakage power for a 32-bit static CMOS adder in a low-Vt,
`Therefore,
`the convergence rate of
`leakage current
`in
`sub-1V, 0.1 Em technology. Leakage reduction is achieved
`transistor stacks increases rapidly with Vt reduction and
`
`with minimal and_processoverheads in area, power
`
`
`
`temperature increase (Figs. 4 & 5). For minimum-Vt devices
`technology. The dynamics of
`leakage reduction due to
`in a sub-1V, 0.1 lum technology, this time constant in 2-nMOS
`transistor stacks, and its influence on the overall
`leakage
`stacks at 110°C ranges from 5-5Ons depending on input
`poweroflarge circuits are elucidated for the first time.
`conditions before both devices are turned ‘off’.
`
`I. Introduction
`III. Dependence of Adder Leakage on Input Vectors
`
`A number as_multiple-thresholdof techniques such
`
`
`
`Increase in the active and standby leakage ofthe 32-bit static
`(MTCMOS) [1], dual-Vt [2] and reverse body bias [2,3] have
`CMOS Kogg-Stone adder with Vt-reduction is shown to be
`been proposed in the past for reduction of processor leakage
`smaller than that in individual transistors (Fig. 6) due to the
`power during standby mode. In this paper, we propose a new
`presence of a Significant number of transistor stacks in the
`standby leakage control scheme which exploits the large
`design. The standby leakage power varies by 30%-40% (Fig.
`reduction in leakage current achievable by simultaneously
`7) depending on the input vector, which determines the
`turning off more than one transistor in nMOS or pMOS
`numberoftransistor stacks in the design with more than one
`“stacks” (i.e. series-connected devices) between supply &
`‘off device. The adder leakage during active operation is
`ground. Typically, a large circuit block contains a significant
`dictated by the sequence of input vectors as well as the
`number of logic gates where transistor “stacks” are already
`operating clock frequency (Fig. 8). Magnitude of the stack
`present (e.g. pMOS stack in NOR or nMOSstack in NAND
`leakage time constant at elevated temperaturesrelative to the
`gates). The technique described here enables effective leakage
`time
`interval
`between
`consecutive
`switching
`events
`reduction during standby mode byinstalling a vector at the
`determines the extent of convergence of the leakage to steady-
`inputs of the circuit block so as to maximize the number of
`state value. As a result, the active leakage corresponding to
`nMOSand pMOSstacks with “more than one ‘off’ device”. In
`each input vector becomes higher as the clock frequency
`contrast to techniques reported in the past [1-3]. the proposed
`increases from 100 to 1000 MHz (Fig. 8), resulting in larger
`scheme offers leakage reduction with minimal overheads in
`average leakage powerat higher frequencies.
`area, power and process
`technology.
`In particular,
`this
`technique can eliminate the need for a high-Vt device for
`standby leakage reduction in a sub-1V,0.1 jim technology.
`We use extensive circuit simulations of individual
`logic gates and a 32-bit static CMOS adder, designed in a sub-
`iV, 0.1 wm technology,
`to 1) elucidate the dynamics of
`leakage reduction due to transistor stacks, 2) examine its
`influence on the overall leakage power of the adder during
`both active and standby modes of operation, and 3) determine
`the standby leakage reductions yielded by application of the
`new leakage control
`technique. Two different Vt values are
`considered throughout the analysis. The low-Vt
`is 100mV
`smaller than the high-Vt.
`
`IV. Standby Leakage Control by Input Vector Activation
`Fig. 9 shows an implementation of the new leakage reduction
`technique where a “standby” control signal, derived from the
`“clock gating’
`signal,
`is used to generate and store a
`predetermined vector in the static input latches of the adder
`during “standby” mode so as to maximize the number of
`nMOS and pMOSstacks with “more than one ‘off’ device”.
`Since the desired input vector for leakage minimization is
`encoded by using a NAND or NORgate in the feedback loop
`of the static latch (Fig. 9), minimal penalty is incurred in
`adder performance. As shown in Fig. 10, up to 2X reduction
`in standby leakage can be achieved by this technique. In order
`that the additional switching energy dissipated by the adder
`and latches, during entry intu and exit from “standby mode”,
`be less than 10% ofthe total leakage energy saved by this
`technique during standby, the adder must remain in standby
`modefor at least 5 us (Fig. 11).
`
`II. Leakage Reduction due to Transistor Stacks
`A 2-input NAND gate is used to illustrate the dynamics of
`leakage reduction in 2-transistor stacks with both devices ‘off?
`(Fig. 1). From the de solution of nMOS subthreshold current
`characteristics (Fig. 1),
`it
`is clear that
`the leakage current
`through a 2-transistor stack is approximately an order of
`magnitude smaller than the leakage ofa single transistor. This
`reduction in leakage is due primarily to 1) negative gate-to-
`source biasing and 2) body-effect induced Vt increase in MI,
`or 3) reduced drain-to-source voltage in M2 which causesits
`Vt to increase, as the voltage Vm at the intermediate node
`converges to ~100mV (Fig. 1). Thus, as shown in Fig. 2,
`smaller amounts of leakage reduction are obtained at higher
`temperatures due to larger subthreshold swing. For 3- or 4-
`transistor stacks,
`the leakage reduction is found to be 2-3X
`larger (Fig. 3) in both nMOS and pMOS.
`The time required for the leakage currentin transistor
`stacks to converge toits final value is dictated by the rate of
`charging or discharging of the capacitance at the intermediate
`node by the subthreshold drain current of M1 or M2. This
`
`40
`
`0-7803-4766-8/98/$10.00 © 1998 IEEE
`
`Vv. Conclusions
`technique,
`We demonstrate a new standby leakage control
`which exploits the leakage reduction offered by transistor
`stacks with “more than one ‘off device”. Up to 2X reduction
`in standby leakage power can be achieved by this technique
`with minimal
`overheads
`in
`area, power
`and_ process
`technology. We also elucidate the dynamics of leakage
`reduction due to transistor stacks, and its influence on overall
`leakage poweroflarge circuits.
`References
`[1] S. Thompsonet. al., 1997 Symp. VLSI Tech., pp. 69-70
`[2] S. Mutohez. al., IEEE JSSC, Aug. 1995, pp. 847-854
`[3] T. Kuroda et. al., IEEE JSSC, Nov. 1996, pp. 1770-1779
`
`1998 Symposium on VLSI Circuits Digest of Technical Papers
`
`APPLE 1013
`
`APPLE 1013
`
`1
`
`

`

`
`
`Standby Leakage Current (mA)
`
`2 0% 0%
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`High Vt Low Vt
` Input2: A=0, B=1
`
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`
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`Fig. 10: Adder leakage current reduction by
`“best ” input vector activation compared t
`average and worst standby leakage
`
`Fig. 11: Standby leakage power savings and
`the minimum time required in standby mode
`
`1998 Symposium on VLSICircuits Digest of Technical Papers
`
`44
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`Fig. 6: Leakage currentincrease with Vt
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`Fig.2: Leakage reduction by 2-nMOS & 2-
`pMOSstacks at different Vt and T
`
`Fig. 3: Leakage current reduction by 2-, 3-,
`& 4-transistor stacks at T=30°C
`
`1
`
`Input]: A=], B=0.
`
`Fig. 7: Distribution of standby leakage current in the adderfor a large
`numberof random input vectors
`F: frequency in MHz
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`F: frequency in MHz
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`Active Leakage Current (mA)
`
`Fig. 8(a): Distribution of active leakage
`current of the adder with low-Vt devices
`at different clock frequencies
`
`Fig. 8(b): Distribution of active lcakage
`current of the adder with high-Vt devices
`at different clock frequencies
`
`Input 2
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`Time (ns)
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`Fig. 4: Temporal behavior of leakage
`current in transistor stacks for different
`standby
`ft
`standby
`temperatures andinitia. input conditions
`clk—Standby
`(b) A latchto store "0"
`(a) Block diagram
`(c) A latch to store "1"
`Fig. 9: An implementation of the standby leakage control schemethrough input vectoractivation
`Low Vt
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`Fig. 5: Dependenceof the time constant
`for stack leakage on Vt, temperature and
`initial input conditions
`
`2
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`