EXHIBITD
`
`to Declaration of Dr. Gregory L. Chesson in Support of Microsoft's
`Opposition to Alacritech'sMotion for Preliminary Injunction
`
`DEFS-ALA0007117
`Ex.1024.001
`
`DELL
`
`

`

`-r::!!'I Protocol Engine,s
`iD :CC Incorporated
`
`Protocol Engine® Handbook
`
`1
`
`DEFS-ALA0007118
`Ex.1024.002
`
`DELL
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 3 of 46
`
`( -·. ~
`"· T
`
`,
`
`/
`
`j
`
`( , . , . "·· •..
`.
`......__. ..
`..
`
`(*
`
`2
`
`DEFS-ALA0007119
`DEFS-ALA0007119
`Ex.1024.003
`DELL Ex.1024.003
`
`DELL
`
`

`

`> 4 Protocol Engines
`b C
`lncorporal1d
`
`• Sil Icon Graphics
`
`CompUsr Systems
`
`This document contains copyrighted information proprietary to
`Protocol Engines9 Inc. and Silicon Graphics• Computer Systems.
`The information in this document is accurate as of the publication date only, and is subject
`to change witJ,out notice. PEI, SGI, and the authors of the attached documents are not responsible
`for any inadvertent errors, or any consequences resulting from the use of any information contained herein.
`
`( __
`
`\
`
`Copyright© 1990, Protocol Engines• Inc. and Silicon Graphics• Computer Systems.
`
`3
`
`DEFS-ALA000? 120
`Ex.1024.004
`
`DELL
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 5 of 46
`
`l
`[
`
`L3SdiHO3d
`
`4
`
`DEFS-ALA0007121
`DEFS-ALA000? 121
`Ex.1024.005
`DELL Ex.1024.005
`
`DELL
`
`

`

`•
`-
`
`4 Protocol Engines
`C
`Incorporated
`
`PE Chlpset
`
`PRELIMINARY
`(subject to change without notice)
`
`to 200 Mbps end-to-end
`
`1. Features
`• provides up
`throughput
`• hardware support fm XTP, TCP, ISO, and
`XNS checksums
`• programmable support for multiple protocols
`• supports multicast, priority sorting, and other
`advanced features.
`
`2. General Description
`The Protocol Engine• chipset offers real-time protocol
`processing for high-speed networks. A wide range of
`cost-performance subsystem solutions are available
`through various configurations based on the PE
`ChipseL The chipset (shown in Figure 1) consists of
`four chips: MPORT, HPORT, BCIL, and CP. A
`basic configuration consists of MPORT, HPORT, and
`BCIL
`MPORT (MAC Port) provides an intelligent medium
`iK:cess control (MAC) layer interface to FDDI and
`other generic MACs. MPORT performs various tasks
`in its datapatb, including checksumming, protocol
`ilentification, and address recognition. One to three
`MAC interfaces are supp<Xted by the architecture. A
`
`high-speed MAC, such as FDDI, requires a dedicated
`MPORT. Lower-speed MACs, such as Ethernet, can
`share an MPORT with the aid of external logic and
`buffering.
`HPORT (Host Port) provides an intelligent direct
`memory access (DMA) engine with a synchronous
`bus inttrface (HBus) to the hosL The· HBus is
`C<IDpab°ble with industry standard buses (e.g., SBus,
`VME) and is easily intafaced to others. HPORT can
`interface to a data soun:e (e.g., sensor) or a data sink
`(e.g., image buffer). One or two HPORT chips can
`be used in the PE subsystem. The architecture
`supports combinations of MPORT and HPORT chips
`up to a combined maximum of four.
`BCIL (Buffer Controller) manages the external direct
`random access memory (DRAM) for buffering frames
`and storing state infonnation. The chipset assumes the
`use of generic, page-mode DRAM chips.
`CP (Control Processor) provides low latency, high
`perfonnance processing for management functions,
`error recovery. and protocol processing functions not
`handled by MPORT, HPORT, or BCIL components.
`The multi-thread instruction architecture of this chip
`minimizes context switching. and branching overhead,
`and maximizes processm- efficiency.
`
`T..,,_111191
`
`CP
`
`acn
`
`lllPORT
`
`oa..
`
`To MAC Fnm lllAC
`
`Figure 1. PE Chlpaet.
`
`5
`
`'Oc:rabor l!l!IO
`
`1
`
`DEFS-ALA000? 122
`Ex.1024.006
`
`DELL
`
`

`

`3. Basic Configuration
`A basic configuration of the PE Chipset uses the
`(Figure 2
`HPORT, MPORT, and BCIL chips.
`illusttates a basic configuration.) In addition to these
`three chips, two memory blocks are required: Control
`Memory (CM) and Network Buffer Memory (NBM).
`Control Memory is based on static, random access
`memory (SRAM); Network Buffer Memory is based
`on dynamic, random access memory (DRAM).
`
`3.1 HPORT
`Data arriving from the host is processed by Host Port
`(HPOR'l). HPORT packetizes the dala into proper
`into the
`inserts proper values
`packet si7.e and
`number,
`sequence
`(e.g.,
`fields
`header/ttailer
`checksum). The packets are temporarily stcred in
`Network Buffer Memory before they are sent to the
`MAC layer by MPORT, when the next service
`opportunity arrives.
`
`3.2 MPORT
`MAC Port (MPOR'l) provides a duplex interface to
`one medium access control (MAC) device. Each
`received frame is processed appropriately depending
`on its. address and protocol type. Various address
`types are supported, including local, broad<:aSt. and
`multicast addresses, as well as a number of wild card
`conditions. MPORT executes checksumming, byte
`swapping, and other data manipulations, while data
`the datapath. The header/trailer
`through
`flows
`information is filtered to an on-chip Packet Processor.
`The packet processor is a programmable micro(cid:173)
`the header/ttailer dala and
`It processes
`engine.
`decides the disposition of the packet.
`The received packets are stored in Network Buffer
`Memory. A number of programmable modes are
`provided for deciding if and how packets will be
`further processed. "Raw data" mode causes packets to
`be delivered to the host via HPORT without further
`processing. This allows the use of existing protocol
`codes with ·minimum or no modification. Otbec modes
`activate further processing of the packets in order to
`achieve faster end-to-end throughpuL The chipset acts
`as a fasapath protocol ~r. Software must be
`provided (in CP, in the host. or in another nearby
`CPU) to do non-faslpath processing.
`
`3.3 BCTL
`The Buffer Controller (BCIL) both manages Network
`Buffer Memory and arbittates access to iL BCIL
`generates DRAM control signals and address signals
`
`' Ocliibcr 1990
`
`PEChipset
`
`for reading from and writing to Network Buffer
`Memory. BCIL also performs periodic DRAM
`refresh cycles.
`
`3.4 Control Memory
`Control Memory (CM) is used for storing control
`infmnation. It is accessed by the MPORT, HPORT,
`and BCIL chips for storing/retrieving various dala
`structures, including tables, maps, control blocks, and
`com~d blocks. The locations where the dala
`structures reside are programmable through on-chip
`registers. The structures are accessed through page
`registers and pointers.
`Control Memory is accessible by words only. (Each
`word is 32 bits.) Optional byte parity can be included.
`The maximum Control Memory si7.e supported by the
`chipset is 256k words. For an end-host with two
`thousand active connections, a minimum of 32k words
`of Control Memory is recommended.
`
`3.5 Network Buffer Memory
`Network Buffel" Memory (NBM) is used to buffer
`network traffic. Both received frames and transmitting
`frames are buffered in Network Btiffer Memory.
`Like Control Memory, Network Buffer Memory is
`accessible by 32-bit words only. Network Buffer
`Memory can be constructed by 256kx4 or 1Mx4
`DRAMs. It is organized by modules. Each module is
`32-bits wide with four bits of optional byte .parity. Up
`to four modules are supported in each bank of
`memory. Up to two banks are supported by this
`In a non-interleaved NBM (Network
`architecture.
`Buffer Memory) structure, one bank of memory is
`used. In an interleaved memory, two are used. The
`minimum Network Buffer Memory si7.e is 256k words
`(1 MByte) and the maximum size is SM words (32
`MBytes).
`In addition to being a temporary repositay for frame
`data, Network Buffer Memory is also used for stming
`the bulk of context-related information fOI' each
`connection. Various dala structures reside in Network
`Duffel" Memory to facilitate storing, organizing, and
`moving data. The dala structures, their locations, and
`their si7.es are programmable via the on-chip registers
`in MPORT, HPORT, and BCIL.
`
`3.6 OPTIONS
`BCIL can have optional Instruction Memory (BIM)
`connected to it direcdy. This memory provides an
`expansion area for firmware that overflows the on(cid:173)
`chip instruction memory.
`
`2
`
`SA
`
`DEFS-ALA000? 123
`Ex.1024.007
`
`DELL
`
`

`

`c
`
`PEChipset
`
`;
`
`•BIM
`
`:"" ............ .
`,_.., ;
`................ ,
`
`iiiiAu•! =--·
`
`C8ue
`
`DBue
`
`To MAC From MAC
`
`Figure 2. Basic Configuration.
`
`To/From Haet
`
`BCTL
`
`llPOAT
`
`Tolfrom Hoet
`
`1
`
`HPORT
`
`CP
`
`BCTL
`
`MPORT1
`
`NBM
`
`;w. .. -.,._
`
`..
`
`:" .............. .
`i::. .. i
`~=:"~
`.................. ,
`
`- ,
`
`FDOI
`
`IMC
`PHY
`PMD
`
`-,
`\
`I
`I
`I
`I
`':t- 'V
`I ' . , \
`I
`I
`
`llPOAT2
`
`PHY
`PMD
`
`\
`
`'
`
`,
`
`CBue
`
`DBue
`
`Figure 3. An Extended Configuration for Dual-attach FDDI.
`
`9 Ocaobor 1990
`
`6
`
`3
`
`DEFS-ALA000? 124
`Ex.1024.008
`
`DELL
`
`

`

`4. Extended Configurations
`A number of extended configuratims are available.
`These involve adding a CP chip and/ol inaeasing the
`number of MPORT and/or HPORT chips.
`
`4.1 CP
`Addition of a CP chip to the basic configuration
`provides significant performance enhancement. As
`shown in Figures 3. 4, and s. CP is connected to CBus
`and DBus. These two buses provide CP direct access
`to the memories that store pertinent information for
`protocol processing. With multi-thread architecture,
`CP is able to attend to multiple processes without
`incmring context switching overhead. CP also bas
`dedicated hardware
`to perform routine network
`processing functions.
`Like the chips of the basic configmation, CP can own
`some of the dara structures in Network Buffer
`Memory (NBM).
`
`4.2 Two MPORTs
`A second MPORT can be added to the basic
`configuration. It could be connected to a second MAC
`
`PEChipset
`
`layer device that may be the same type as the first one,
`or may be different This configmation could be ~
`to construct a dual MAC. dual aaacb FDDI station in
`orda to off a a higher level of redlUldancy. (See
`Figure 3.) Or, the second MPORT could be used as a
`gateway to connect two networks as illusarated in
`Figure 4. In this configuration. the packets received
`from one MAC go to Network Buffer Memory and
`then are delivered to the other MPORT. which
`tmnsfers the data to the other MAC. 1be packets are
`not~ by HPORT and are not passed over the
`HBus. ·and hence do not require any host intervention.
`A third use for a second MPORT could be to consttuct
`a bridge. This cooJd be done by connecting the
`second MPORT to a different type of MAC than the
`first
`
`4.3 Three MPORTs
`A third MPORT can be added thus making it possible
`to implement any ccmbination of the above. For
`example. a three MPORT system can be configured
`for both dual MAC FDDI and a bridge/gateway
`application.
`
`(~,
`
`CP
`
`CP(cid:173)-
`
`NIM
`
`iiiWe ... --
`
`Figure 4. An Extended Configuration for an FDDI Gateway.
`
`Dllua
`
`t0.....1'90
`
`7
`
`4
`
`DEFS-ALA000? 125
`Ex.1024.009
`
`DELL
`
`

`

`PEChipset
`
`4.4 Two HPORTs
`A se.cond HPORT can be adde.d
`the basic
`to
`configuratian. This HPORT can be connected to a
`data sink m a data source. or both. Typical data
`sensors and
`analog-to-digital
`somces
`include
`converters with adequate buffers. A typical data sink
`is an image buffer. A typical data sink and source is a
`frame buffer m ~ storage device. Data can be fed
`directly into the data sink/source device via the second
`the host bus. This
`HPORT without ttaversing
`significantly improves the data throughput to these
`devices.
`The seccnd HPORT could also be connected to the
`router backplane. 1bis configuration provides high
`pe.rformance routing fer high bandwidth network
`media. (See Figure 5.)
`
`--
`1=--= I
`
`cu
`
`Rub -
`
`CP
`
`8CTL
`
`t!!! ----
`
`Figure 5. Extended ConftguraUon with two HPORTL
`
`(_
`
`8
`
`s
`
`DEFS-ALA000? 126
`Ex.1024.010
`
`DELL
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 11 of 46
`
`LHuOdiN
`
`9
`
`DEFS-ALA0007127
`DEFS-ALA000? 127
`Ex.1024.011
`DELL Ex.1024.011
`
`DELL
`
`

`

`r
`-
`
`zc Protocol Engines
`l1IC0f710'tlled
`2Q
`
`MPORT
`
`1. Features
`• one micron CMOS technology
`• 33MHz system clock
`• synchroni7.ation to external MAC device clock.
`upto2SMHz
`• asyncbronous MAC device clock and system
`clock
`• two simplex. 9-bit channels: one to and one
`from MAC device
`• handles peak dala rate to 200M bitSt's for each
`simplex channel
`• separate. on-chip receiver and
`FIFOs
`• 32-bit packet processing engine
`• hardware support for XlP, TCP, ISO. and
`XNS checksums
`• pogrammable support for multiple protocols
`
`ttansmitter
`
`2. General Description
`MAC Port (MPOR1) of the Protocol Engine• chipset
`is a programmable controller that supports high-speed
`
`PRELIMINARY
`(subject to change wi1hout notice)
`
`protocol processing. It provides hardware interfaces
`to the medium access control (MAC) device, the dala
`bus (DBus). and the con1rol bus (CBus).
`The MAC interface provides a b~wide, duplex dala
`channel to the MAC device. This channel is operated
`by the MAC device clock, up to 2S MHz. The MAC
`device clock may be asynchronous to the PB Cbipset's
`system clock.
`the DBus interlace, MPORT accesses
`11uough
`Netwolt Buffer Memory to stme received frames and
`to retrieve frames for transmission.
`intaface, MPORT accesses
`the CBus
`Through
`, Conlrol Memory and sencWreceives conlrol messages
`to peer devices.
`With these three interfaces. an on-chip pogrammable
`processor. and datapath functional units, MPORT
`performs checksumming. header processing, packet
`demultiplexing, and other functions. The user has the
`freedom to program a variety of protocols and
`policies. limited to the on-chip hardware resources.
`
`CP
`
`8C1L
`
`Te lllAC " - lllAC
`
`Flglft 1. PE Chlpaet.
`
`10
`
`' Ocllabs 19'0
`
`1
`
`DEFS-ALA000? 128
`Ex.1024.012
`
`~···
`
`;'
`I
`\"_
`
`DELL
`
`

`

`MPORT
`
`~
`
`PIN
`
`CAD
`CDP
`ems-
`am
`CWi"'
`CRQ
`arr-
`CEii"
`ar
`CSCM
`CSBCTL
`CSCP'"
`DDATA
`DDP
`DTG
`DRQ
`oor
`i5WR
`Ma.IC
`MDO
`MPO
`MDI
`MPI
`Olben
`ax
`RESiff"
`fiS
`TCK
`1MS
`m1
`TDO
`TRST
`
`Function
`
`Type
`
`#ofpins
`
`CBm~
`CBm~pmy
`CBm eddlaa lbObe
`CBuanm
`CBmwrile
`CBmn:qaat
`CBmgnnt
`CBmemir
`CBu ac1ec:t in
`CBm aelect OUl for CM (cmbOl memory)
`CBm aelect OUl for BCll. (bufferc:mmler)
`CBm IClecl out for CP (cmbOl poceuor)
`
`Dlluadala
`DBua dala p.my
`DButag
`Dlluaiequat
`Dlluagna
`DBuwrila
`
`MAC cllMce dock
`MACdalaoalpUl
`MAC pmy OUlplll
`MAC dala input
`MAC pmy input
`TBD
`
`Clock
`Reset
`
`Test inrcrm1 scm
`Testcloc:k
`Test mode select
`Testdalain
`Test dala out
`Test reset
`
`Table 1. llPORT Pin SUmmary.
`
`32
`4
`
`1
`1
`1
`1
`
`32
`4
`4
`
`1
`8
`1
`8
`
`LtO
`LtO
`LtO
`LtO
`LtO
`0
`I
`LtO
`I
`0
`0
`0
`
`LtO
`LtO
`LtO
`0
`I
`0
`
`I
`0
`0
`I
`I
`
`I
`I
`
`I
`I
`I
`I
`0
`I
`
`9 Ocliabor 1990
`
`11
`
`3
`
`DEFS-ALA000? 129
`Ex.1024.013
`
`DELL
`
`

`

`CBusPins
`
`Symbol
`CAD[31:0]
`
`CDP[3:0]
`
`CADS
`
`CiID
`
`CWR"
`
`CRQ
`
`CGT
`
`CBRR
`
`csr
`
`CSCM
`
`CSBC'IL
`
`CSCP
`
`,0...-1990
`
`MPORT
`
`J/O Descripdon
`J/O Address/data bus. It is ai-stared when CBus is not granted. When CBus is granted,
`address is driven onto this bus dming address cycle, and dala is driven onto this bm
`during dala cycle. 1be data is driven by MPORT in a write transfer, or it is driven by
`a slave device in a read 1ransfer.
`
`J/O Byte parity for the CAD(31:0] bus. CDP has the same timing as CAD[31:0]. CDP[3]
`covezs the CAD(31:24], and so on.
`
`J/O Address Slrobe. When CBus is granted, it is an· outpuL lls assertion indicates that
`address is being driven onto CAD[31:0] by MPORT.
`When CBus is not granted, it is an inpuL lls assertion along with the assertion of
`CSI indicates that CAD[31:0] carries ~ driven by the current CBus master to
`address a slave register on MPORT.
`
`I/O Read strobe. When CBus is granted, it is an outpUL Its assertion indicates a read
`transfer.
`When CBus is not granted, it is an inpuL Its assertion indicates that the cmrent CB us
`master is making a read transfer.
`
`I/O Write sttobe. When CBus is granted, it is an outpuL Its assertion indicates a write
`transfer.
`When CBus is not granted, it is an input. Its asSC21ion indicates that the current CBus
`master is making a write transfer.
`
`0
`
`I
`
`CBus request. This signal is asserted to request CBus mastership. It may remain
`asserted to request multiple transactions fm a bm tenure.
`
`CBus granL This input indicates the granting of CBus mastership.
`
`J/O CBus error. This pin is both input and output. The~ drain, active low output
`reports CBus error to the peer devices which have CERR pins connected together.
`The input circuitry deteclS CBus errors reported by any device connected on CBus.
`
`I
`
`0
`
`0
`
`0
`
`Olip select input 1be assertion of this pin indicates that the current CBus master is
`making a transaction with MPORT, as a slave deviee.
`
`Control Memmy sele.ct It is ai-stated when CBus is not granted. It is asserted when
`CBus is granted and MPORT is addreaing Control Memory.
`
`Ben. select It is ai-stated when CBus is not granted. It is asserted when CBus is
`granted and MPORT is addressing BC'IL.
`
`CP select. It is ai-stated when CBus is not granted. It is asserted when CBus is
`granted and MPORT is addressing CP.
`
`12
`
`4
`
`DEFS-ALA000? 130
`Ex.1024.014
`
`DELL
`
`

`

`MPORT
`
`Symbol
`DDATA[31:0}
`
`DDP[3:0]
`
`DTG[3:0]
`
`DRQ
`
`DGT
`
`i5WR"
`
`i
`
`.. ,.
`<·;'1_
`
`I/O
`I/O
`
`I/O
`
`I/O
`
`0
`
`I
`
`0
`
`Description
`Data bus. It is tti-stated when DBus is not granted. When DBus is granted,
`data is driven ODID this bus in a write transaction ID the Netwodc Buffe.r Memory.
`Data is driven by the Network Buffer Memory in a read transaction.
`
`Byte parity fm' the DDATA[31:0]. It has the same timing as DDATA[31:0]. DDP[3]
`covers the DDATA[31:24], and so on.
`
`Tags. These tag bits are tti-stated when DBus is not granted. When DBus is granted,
`the same timing as
`they are outputs in a write transaction, driven with
`DDATA[31:0]. ~ tag bits are sensed by BC'IL to determine the data typeS and
`the status on DDATA[31:0].
`They are inputs in a read transaction. MPORT senses these tag bits to determine the
`data typeS and status on DDATA[31:0], indicated by BC'IL.
`
`DBus request. This signal is asserted to request DBus masteisbip. It may remain
`asserted to request multiple transactions f<r a bus tenure.
`
`DBus granL This input indicates the granting of DBus mastaship.
`
`DBus write sttobe. This signal, when negated, indicates the requested DBus
`transactions are reads. When asserted, it indicates the requested DBus transactions
`are writes.
`
`MAC Interface Pins
`
`Symbol
`MCLK
`
`M00[7:0]
`
`MPO
`
`MD1[7:0]
`
`MPI
`
`TBD
`
`I/O
`I
`
`DescriptioD
`MAC clock. This clock is used ID synchroni7.e with the extanal MAC device.
`It may be asynchronous to the system clock, Cl.IC. The on-chip dual-clock FIFO
`synchronizes MCLK and CLK.
`
`0
`
`0
`
`I
`
`I
`
`Data oulpUt ID MAC device.
`
`Parity for the data output to MAC device.
`
`Data input from MAC device.
`
`Parity for the data input from MAC device.
`
`The cmtrol signals f<r the MAC device interface are to-be-determined.
`
`(
`
`1.. ••
`
`to..ai.1'!10
`
`13
`
`s
`
`DEFS-ALA000? 131
`Ex.1024.015
`
`DELL
`
`

`

`c
`
`System Control Pins
`
`MPORT
`
`l/O Description
`I
`System clock. This input signal provides synchronization for the on-chip circuitry.
`
`I
`
`System reset. This input signal resets on-chip circuitry to a known stare. It should
`remain as.ated for at least 512 CLK cycles to assure proper reset of the chip.
`
`l/O Description
`Test internal scan. Assertion of this signal selects the internal scan test.
`I
`
`I
`
`I
`
`I
`
`0
`
`I
`
`Test clock. This input signal is used to synchronize on-chip testing circuitry.
`
`Test mode selecL This signal is used to select among various test modes.
`
`Test data inpuL This pin is used for input test data.
`
`Test data OUlpDL This pin is used for OUlpnt test data.
`
`Test reset. This pin is used to reset test modes.
`
`Symbol
`
`CLK
`
`RESET
`
`Test Pins
`
`Symbol
`TiS
`
`TCK
`
`TMS
`
`IDI
`
`TOO
`
`TRST
`
`Power Pins
`
`1:
`
`-·
`
`( •.
`
`\
`
`(_
`
`'Odobor 19'0
`
`14
`
`6
`
`DEFS-ALA000? 132
`Ex.1024.016
`
`DELL
`
`

`

`MPORT
`
`the packet in the frame, extracts certain information,
`4. Functional Description
`and delivers it to the Packet Processing Unit
`MPORT (MAC Port) transfers fiames between the
`A Checksummer validales the checksum on the packet
`extemal MAC device and Network Buffer Memory
`flowing through the Receive Pipeline Unit Packet
`input tiame passes ~
`the
`(NBM). When
`Processm finnware determines the actions to be taken
`MPORT, processing is done in the datapatb. This
`in the event of checksum failure or other failure.
`processing includes checksumming, byte swapping,
`identification,
`protOCOl
`parsing,
`header/trail«
`demultiplexing. etc.
`The processing is done in various functional blocks
`that are illustrated in Figure 3.
`There are six map functional blocks in MPORT:
`MAC Intaface Unit (MIU), Receive Pipeline Unit,
`Transmit Pipeline Unit, DBus Interface Unit {DIU),
`Packet Processing Unit (PPU) and CBus lntaface
`.
`Unit(CRJ).
`
`4.3 Transmit Plpellne Unit
`
`4.1 MAC Interface Unit (MIU}
`
`The MAC Interface Unit contains the state machines
`to interface to the external MAC devices. It has an
`eight bit data input bus and an eight bit data oulpUt bus
`to connect to the MAC. Both buses have parity bits.
`The parity can be optionally tmned off. The conttol
`signals interfacing to the MAC device have not been
`finali7.ed.
`
`4.2 Receive Plpellne Unit
`
`The Receive Pipeline Unit lw a single directional data
`flow. The data flow starts from MIU. It is fed into a
`Receive MAC FIFO. The data coming out of the
`Receive MAC FIFO flows into a Receive Da&apadl,
`then goes to a Receive DBus FIFO. The data coming
`out of Receive DBus FIFO goes to a DBus Inraface
`Unit (DIU). DIU will store the data into Network
`Buffer Memory via DBus.
`The Receive MAC FIFO is opaated by both MCLK
`and O.K. MCLK is used to feed data into the FIFO
`and CLK is used to retrieve data from FIFO. This
`scheme allows the MAC device, running oo MCLK,
`to be asyncluonous to the system clock, O.K.
`The data, embodied in frames, flows into the Receive
`Datapath to obtain a series of processing steps. The
`data are word aligned, padded with fill-paami if
`necessary, byte swapped if necessary to become big(cid:173)
`endian. These pocessing steps are controlled by a
`is a programmable
`Proto Parser. Proto Parser
`proces.90f'. Its micro program is down-loaded at boot
`time. It can be programmed to adapt to various media
`and various protocols. Proto Parsec counts the bytes in
`frames and examines their header to determine further
`action. Proto Parser recogni7.Cs the profOCOl used by
`
`9 Oclalm 19'0
`
`15
`
`Like the Receive Pipeline Unit, the Transmit Pipeline
`Unit is a single directional datapath. The data flow
`starts from DIU. The data flows into a Transmit DBus
`FIFO, through a Transmit Datapath and a Transmit
`MAC FIFO and ends at the MAC Interface Unit
`(MIU).
`The Transmit MAC FIFO is similar to the Receive
`MAC FIFO with opposite data flow directioo. The
`data flow into the FIFO is clocked by CLK and the
`data flow out of the FIFO is clocked by MCLK to
`provide synchroni7.ation between two clock systems.
`
`4.4 DBus Interface Unit (DIU)
`The DBus Interface Unit contains state machine· for
`DBus control. It performs burst read/write on the
`DBus to maximize DBus efficiency. Two operating
`modes are available: the non-interleaved mode and the
`interleaved mode.
`The non-interleaved mode works with non-interleaved
`to deliver 320 Mbps
`Netwmk Buffer Memory
`bandwidth on DBus. The interleaved mode wmks with
`interleaved Network. Buffer Memory to deliver 700
`Mbpsbandwidth on DBus.
`
`4.5 Packet Processing Unit (PPU)
`
`The Packet Processing Unit contains a Packet
`Processor and Instruction Memory. The pogram for
`the Packet Processor is down-loaded into Instruction
`Memory at boot time. The Packet Processor processes
`the information received from the Receive Pipeline
`Unit As a result of the processing in Packet Processor,
`the receiving packets are demultiplexed to each
`context They are also propezly disposed accmling to
`the information retrieved from the header/trailer in the
`packet.
`
`4.6 CBus Interface Unit (CIU)
`
`The CBus Interface Unit interfaces to CBus to access
`the Conttol Memory and other devices in the PE
`Chipset. The Packet Proces.u' may access the data
`
`7
`
`DEFS-ALA000? 133
`Ex.1024.017
`
`DELL
`
`

`

`MPORT
`
`base stored in Control Memory, or request slave
`access to the other devices attached oo CBus. These
`the Packet
`uansactioos provide information for
`Proceaor to decide the disposition of the packet being
`proc:essed, updates information in Control Mrmay to
`facilitate pnx:eaing for the following packets, and
`receives and provides commands to peer devices.
`
`(
`
`16
`
`8
`
`DEFS-ALA000? 134
`Ex.1024.018
`
`DELL
`
`

`

`Case 3:04-cv-03284-JSW Document 69-4 Filed 02/04/05 Page 19 of 46
`
`LuOdH
`
`17
`17
`
`DEFS-ALA0007135
`DEFS-ALA000? 135
`Ex.1024.019
`DELL Ex.1024.019
`
`DELL
`
`

`

`• < Protocol Engines
`Incorporated
`C
`P
`
`PRELIMINARY
`(subject to change without notice)
`
`HPORT
`
`1. Features
`• one micron CMOS te.chnology
`• 33MHz system clock
`• syncbrmi7.ation to external host bus clock. up
`to25MHz
`• asynchronous host bus clock and system clock
`transmiuer
`intemal
`receiver and
`• separate
`FIFOs
`• 32-bit host interface with parity
`• performs checksum generatioo, packetization,
`byte swapping. word alignment, and other
`'
`functions
`• hardware support for XTP, TCP, ISO, and
`XNS checksums
`• pogrammable support for multiple protocols
`• supports both big- and little-endian hosts.
`
`2. General Description
`Host Port (HPORT) of the Protocol Engine• chipset is
`a programmable controller that supports high-speed
`three extmUil
`protocol processing:
`It provides
`
`hardware interfaces: host bus (HBus), data bus
`(DBus), and control bus (CBus).
`11uough HBus, HPORT provides DMA and slave
`intelfaces to the host bus or to a dedicated bus
`coonecting to a data sinlc/soun::e device, such as image
`buffer and sellS<X'. HBus is opezated by a separate
`clock. HCLK, to synchronize to the host bus.
`11uough · DBus. HPORT accesses Netwodt Buffer
`Memory to store output pactets, to retrieve received
`packets, and to update the buffer management data
`structures.
`Through CBus, HPORT accesses Control Memory
`and sends/receives control messages to peer devices. It
`also povides a datapath for the host to make slave
`accesses to HPORT's peer devices..
`these buses, an on-chip pogrammable
`11uough
`processor, and the datapath functiooal unit. the
`HPORT perfonns checksum generation, packetization,
`intelligent DMA. and other functions. HPORT can
`support a variety of protoeols and custom host
`interfaces.
`
`C.
`
`CP
`
`llCTL
`
`Te llAC Fw.- llAC
`
`Flgan 1. PE Chlpaet.
`
`18
`
`1
`
`DEFS-ALA000? 136
`Ex.1024.020
`
`DELL
`
`

`

`3. Pin Description
`
`HPORT
`
`HAD P1:oJ
`HOP P:OI
`lmz~
`Rm(~
`tllD
`HA P:oJ
`IDl
`fml'Tllm
`AD
`ACEllR
`RRa
`RaT
`HCUC
`AllllEI'
`HllODE
`
`CUC
`
`llQI 11:111 ,.
`
`TCK
`TUS
`TDI
`TOO
`TRST
`
`Figure 2. HPORT Symbol Dl-aram.
`
`-T
`
`--
`
`Rx
`
`Ra
`
`.....
`
`FFO
`
`All
`D8US
`FIFO
`
`,..
`D8US
`FFO
`
`- -
`
`Figure 3. HPORT Block Diagram.
`
`---
`
`-
`
`19
`
`2
`
`DEFS-ALA000? 137
`Ex.1024.021
`
`DELL
`
`

`

`HPORT
`
`20
`
`3
`
`DEFS-ALA000? 138
`Ex.1024.022
`
`DELL
`
`

`

`HPORT
`
`CBusPins
`
`Symbol
`CAD[31:0]
`
`Description
`110
`I&O Address/data bus. It is bi-stated when CBus is not granted. When CBus is granted.
`address is driven onto thiS bus during address cycle. and data is driven onto this
`bus during dala cycle. The data is driven by HPORT in a write ttansfer, er it is
`driven by a slave device in a read ttansfC'l'.
`
`CDP[3:0]
`
`I/O
`
`Byte parity fer the CAD[31:0] bus. It has the same timing as the CAD[31:0].
`CDP[3] covas the CAD[31:24], and so on.
`
`CADS
`
`I/O
`
`Address strobe. When CBus is granted. it is an outpuL Its assertion indicates that
`address is being driven onto CAD[31:0] by HPORT.
`When CBus is not granted, it is an inpuL Its assertion along with the assertion of
`CSI indicates that CAD[31:0] carries address driven by the current CBus master
`to address a slave register on HPORT.
`
`CiID
`
`IJO
`
`Read strobe. When CBus is granted. it is asserted to indicate a read b30Sfer.
`When CBus is not granted. it is an inpuL Its assertion indicates that the current
`CBus master is making a read ttansfer.
`
`CWR
`
`CRQ
`
`COT"
`
`CERR
`
`CSI
`
`CSCM
`
`CSBCTL
`
`CSCP
`
`J/O Write strobe. When CBus is granted, it is asserted to indicate a write ttansfer.
`When CBus is not granted, it is an inpUL Its assertion indicates that the current
`CBus masta' is making a write transfC'l'.
`
`0
`
`I
`
`I/O
`
`I
`
`0
`
`0
`
`0
`
`CBus request. This signal is asserted to request CBus mastership. It may remain
`asserted to iequest multiple transactions fer a bus tenure.
`
`CBus granL This input indicates the granting of CBus mastership.
`
`CBus enor. This pin is both input and oulpUL The open drain, active low output
`reports CBus error to the peer devices which have CERR pins connected
`togethez. The ~put circuiuy detects CBus emrs repmt.ed by any device
`connected on CBus.
`
`Olip select in. The assertion of this pin indicates that the current CBus master is
`making a transaction with HPORT, as a slave device.
`
`Conuol Memory selecL It is bi-stated when CBus is not granted. It is asserted
`when CBus is granted and HPORT is addressing Conuol Memory.
`
`BCIL selecL It is bi-stated when CBus is not granted. It is asserted when CBus is
`granted and HPORT is addressing BCTL.
`
`CP select It is tri-stated when CBus is not granted. It is asserted when CBus is
`granted and HPORT is addressing CP.
`
`(
`'-----
`
`21
`
`4
`
`DEFS-ALA000? 139
`Ex.1024.023
`
`DELL
`
`

`

`HPORT
`
`110 Description
`J/O Data bus. It is tri-stared when DBus is not granted. When DBus is granted, data is driven mto
`this bus in a write transaction to the Netwmk Buff« Memory. Data is driven by the Netwodc
`Buffer Memory in a read aansaction.
`
`J/O Byte parity for the DDATA[31:0]. It bu the same timing as DDATA[31:0]. DDP(3] covers
`the DDATA[31:24), and so on.
`
`J/O Tags. These tag bits are tri-stared when DBus is not granted. When DBus is granted, they are
`oulpUts in a write aansaction, driven with the same timing as DDATA[3l:OJ. These tag bits
`are sensed by BCil. to determine the data typeS and the slalUS on DDATA[31:0].
`They are inputs in a read transactim. HPORT senses these tag bits to determine the data
`typeS and status on DDATA[31:0], indicated by BCil..
`
`0
`
`I
`
`I
`
`DBus requesL This signal is aaerted to request DBus mastership. It may remain a.w.rted to
`request multiple ttansactkms for a bus tenure.
`
`DBus granL This input indicates the granting of DBus mastership.
`
`DBus write sttobes. This signal, when negated, indicates the requested DBus ttansactions are
`reads. When merted, it indicates the requested DBus ttansactions are writes.
`
`DBusPins
`
`Symbol
`DDATA[31:0]
`
`DDP [3:0)
`
`DTG[3:0)
`
`DRQ
`
`DOT
`
`DWR
`
`HBusPins
`
`Symbol
`HAD[31:0]
`
`110 Description
`J/O HBus addresB/dara. Data and addresses are transferred over these lines. When HPORT is HBus master,
`these lines are inputs in reads and outputs in writes for data transfers. When HPORT is HBus slaw,
`they are the other way around.
`
`HDP[3:()]
`
`IJO HBus data byte parity. These signals provide byte parity for HAD[31:0]. HDP(3] coven HAD[31:24),
`and so on. They can be optionally turned off.
`
`HSJZ[2:0}
`
`IJO HBus si7.e. These encoded lines indicate the transfer size of HAD[31:0). They are outputs~
`HPORT is HBus muter. They are inputs when it is not.
`The coding of these signals are as follows.
`HSJZ[2:0} Function
`WMI (four byte) ttansfer
`()()()
`Byte transf«
`001
`010
`Half-word (two byte) ttansfer
`011
`Reserved
`Four wMI burst (16 bytes)
`100
`Eight word burst (32 bytes)
`101
`110
`Sixteen word burst (64 bytes)
`Two word burst (8 bytes)
`111
`
`Continwd on nut page
`
`'OclallW 1'90
`
`22
`
`s
`
`DEFS-ALA000? 140
`Ex.1024.024
`
`DELL
`
`

`

`HPORT
`
`HBus Pins continued
`
`Symbol
`HACK [2:0)
`
`HRD
`
`HA[7:0]
`
`HCsr
`
`HINTREQ
`
`HAS"
`
`HI.ERR
`
`HRQ
`
`HGT'"
`
`HCLK
`
`HRESET
`
`HMO DE
`
`110 Description
`J/O HBus acknowledgment These encoded acknowledgment signals are used to terminate
`HBus cycles. They are inputs when HPORT is HBus master. They are oulputs when it is DOL
`The coding of these signals are as follows.
`HACK (2.-0) Function
`000
`Idle/wait
`Error acknowledgment
`001
`Byte (data) acknowledgment
`010
`Rerun acknowledgment
`011
`Word (data) acknowledgment
`100
`Reserved
`101
`Half.;word (data) acknowledgment
`110
`Reserved
`111
`
`J/O HBus read. This signal indicates HBus data transfer direction. When it is asserted, it indicates a
`read cycle. Else, it indicates a write cycle.
`This line is an oulpUt when HPORT is HBus master. It is input when HPORT is not.
`
`I
`
`I
`
`0
`
`I
`
`I
`
`0
`
`I
`
`I
`
`I
`
`I
`
`HBus slave address. These addrea lines presents physical addresses d