throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of:
`U.S. Patent No.:
`Issue Date:
`Appl. Serial No.:
`Filing Date:
`Title:
`
` John Jianhong Zhu et al.
` 9,024,418 Attorney Docket No.: 39521-0045IP2
` May 5, 2015
` 13/829,864
` March 14, 2013
` LOCAL INTERCONNECT STRUCTURES FOR
`HIGH DENSITY
`
`
`
`DECLARATION OF DAVID KUAN-YU LIU, PH.D.
`
` My name is Dr. David Kuan-Yu Liu. I understand that I am
`
`submitting a declaration in connection with Inter Partes review (“IPR”)
`
`proceedings before the United States Patent and Trademark Office for U.S. Patent
`
`Number 9,024,418 (“’418 Patent”).
`
`
`
`I have been retained by Fish & Richardson P.C. (“Counsel”), on
`
`behalf of Apple Inc. to offer technical opinions with respect to the ’418 Patent and
`
`the references cited in this IPR. My compensation is not based on the outcome of
`
`my opinions.
`
` My curriculum vitae (“CV”) is provided as Exhibit 1004.
`
`
`
`I am not a lawyer. As set forth in my CV, I hold M.S. and Ph.D.
`
`degrees in Electrical Engineering from Stanford University and have 20 years of
`
`experience as an engineer and engineering manager/director of Complementary
`
`Metal Oxide Semiconductor (CMOS) technology development. I hold over 90
`
`1
`
`APPLE 1014
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`U.S. patents, a large number of which are directed to CMOS processes and
`
`semiconductor technology.
`
`
`
`The vast majority of my patents are in the area of CMOS high density
`
`circuit and memory architecture. As such, I am intimately familiar with the
`
`concept of having a compact layout of transistors to implement a library of logic
`
`gate functions. For example, US Patent Nos. 6,693,027 and 8,988,103 relate to the
`
`use of novel device physics to facilitate compact and high performance logic gate
`
`functions.
`
`
`
`I have also authored several technical papers that have been published
`
`in well-respected, peer-reviewed journals, such as the IEEE Electron Device
`
`Letters, the IEEE Journal of Solid-State Circuits, and the IEEE Transactions on
`
`Electron Devices. As an example, I worked on a new conductivity-modulated
`
`Power MOSFET that features a buried minority-carrier injector to enhance the
`
`current conduction capability of the Power MOSFET. This work was published in
`
`the IEEE Transactions on Electron Devices.
`
`
`
`During my career, I have worked at some of the leading technology
`
`companies in the world, such as Texas Instruments, Advanced Micro Devices,
`
`Altera Corporation (now a subsidiary of Intel Corp.), and Xilinx. At these
`
`2
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`companies, my work focused on various aspects of CMOS and semiconductor
`
`technology.
`
`
`
`The following provides a chronological highlight of my experience as
`
`discussed above and in my CV. From 1989 to 1992, I was a member of technical
`
`staff at Texas Instruments, Inc. At Texas Instruments, my job responsibilities at
`
`Texas Instruments also included process integration, device modeling, high-
`
`voltage CMOS process integration, and investigating novel source-side injection
`
`mechanisms for Flash EPROM channel hot-electron programming.
`
`
`
`From 1992 to 1995, I was a member of the technical staff at Advanced
`
`Micro Devices, Inc. (AMD) where I was a key contributor in optimizing Flash cell
`
`and periphery devices in AMD’s CMOS-based 0.5um and 0.35um Flash EPROM
`
`technology. My job responsibilities at AMD also included process integration,
`
`device modeling, and development of triple-well process technology for
`
`accommodate x-decoder transistors and high voltage transistors for negative gate
`
`erase operation. While at AMD, I was awarded a Spotlight Award for developing
`
`a method of manufacturing a self-aligned source (SAS) etch for a NOR flash
`
`memory.
`
`
`
`I spent the next five years of my career in managerial and director
`
`roles at several California-based semiconductor companies. I was responsible for
`
`3
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`increasing yield and for leading teams of engineers working to develop next-
`
`generation memory devices.
`
`
`
`In 2000, I co-founded Progressant Technologies in Fremont,
`
`California. Progressant Technologies developed IP for negative differential
`
`resistance transistor technology and was eventually acquired by Synopsys, Inc.
`
` From 2000 to 2004, I was a Senior Manager at Xilinx, Incorporated,
`
`where I was responsible for developing nonvolatile memory process technology
`
`for flash and CPLD product applications, as well as advanced CMOS process
`
`technology (specifically 75nm CMOS technology node, a half node version
`
`between 90nm and 65nm).
`
` From 2004 to 2007, I was a Senior Scientist at Maxim Integrated
`
`Products where I was responsible for developing Embedded Non-volatile Memory
`
`process technology for Power Management product applications.
`
` Since 2007, I have served as a technical consultant where I have
`
`provided expert advice regarding Flash memory technology, CMOS process
`
`technology, and semiconductor device physics.
`
`
`
`
`
`I am not now, and have never been an employee of the Petitioner.
`
`In writing this Declaration, I have considered the following: my own
`
`knowledge and experience, including my work experience in the fields of
`
`4
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`semiconductor design and processes; and my experience in working with others
`
`involved in those fields. I have reviewed the ’418 Patent, including the claims of
`
`the patent in view of the specification and the file history. In addition, I have
`
`reviewed the following documents:
`
` U.S. Patent No. 9,024,418 (“’418 patent” or “Ex. 1001”), and its
`
`accompanying prosecution history (“’418 Prosecution History” or
`
`“Ex. 1002”)
`
` Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2001
`
`(“Razavi” or “Ex. 1008”)
`
` Chenming Hu, Modern Semiconductor Devices for Integrated
`
`Circuits, 195-258, 2010 (“Hu” or “Ex. 1009”)
`
` U.S. Patent No. 8,026,536 ("Yoshida" or "Ex. 1015")
`
` U.S. Patent No. 9,355,910 ("Liaw" or "Ex. 1016")
`
` U.S. Patent No. 4,570,176 ("Kolwicz" or "Ex. 1017")
`
` U.S. Patent No. 5,376,585 (“Lin” or “Ex. 1018”)
`
` U.S. Patent No. 7,335,583 (“Chang” or “Ex. 1019”)
`
` U.S. Patent No. 6,818,547 (“Chen” or “Ex. 1020”)
`
` U.S. Patent No. 6,767,827 (“Okada” or “Ex. 1021”)
`
` U.S. Patent No. 6,969,952 (“Gedamu or “Ex. 1022”)
`
`5
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
` James B. Kuo and Ker-Wei Su, CMOS VLSI Engineering Sili
`
`con-on-Insulator (SOI), 123-131, 1998 (“Kuo” or “Ex. 1023”)
`
` Counsel has informed me that I should consider these materials
`
`through the lens of one of ordinary skill in the art related to the ’418 patent at the
`
`time of the earliest effective priority date (“Critical Date”) of the ’418 Patent, and
`
`I have done so during my review of these materials. My understanding is that the
`
`Critical Date in this case is March 14, 2013, the filing date of U.S. Application No.
`
`13/829,864, from which the ’418 patent issued.
`
`
`
`I am familiar with the knowledge and capabilities of one of ordinary
`
`skill in the areas mentioned above, notably including the areas of semiconductors
`
`and semiconductor processes. My experience working in industry has allowed me
`
`to become directly and personally familiar with the level of skill of individuals and
`
`the general state of the art in these areas. Unless otherwise stated, my testimony
`
`below refers to the knowledge of one of ordinary skill (as described in Section II
`
`below) in the fields as of the Critical Date, or before.
`
` This declaration is organized as follows:
`
`I.
`
`II.
`
`Brief Overview of the ’418 Patent
`
`Level of Ordinary Skill in the Art
`
`III. Terminology
`
`6
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`IV. Discussion of References
`
`V.
`
`Legal Principles
`
`VI. Conclusion and Additional Remarks
`
`I.
`
`Brief Overview of the ’418 Patent
`
` The ’418 Patent includes 20 claims, of which claim 1, 12 and 17 are
`
`independent. Claims 2-11, 13-16, and 18-20 depend directly or indirectly from
`
`claims 1, 12, and 17, respectively. The technology in the ’418 Patent generally
`
`relates to a local interconnect structure that includes a gate-directed local
`
`interconnect coupled to an adjacent gate layer through a diffusion-directed local
`
`interconnect. ’418 Patent at Abstract. For the purposes of my analysis of the art
`
`and claimed features, I have understood the term “couple” as including direct or
`
`indirect connections, which Counsel informed me is not inconsistent with how
`
`courts have interpreted “couple.”
`
`Design Trade-offs Discussed by the ’418 Patent
`
` The Background section of the ’418 Patent (“The Background”)
`
`describes the design trade-offs when trying to implement high density circuits in
`
`sub-micron processes. ’418 Patent at 1:10-2:22. The discussion of design trade-
`
`offs begins in the ’418 Patent with the need to have high density circuits while
`
`sustaining sufficient transistor strength. ’418 Patent at 1:15-25. The Background
`
`7
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`notes that “[t]o achieve high density yet have adequate transistor strength, strain
`
`engineering techniques have been developed so that the crystal lattice for the
`
`semiconductor substrate is strained in the diffusion region used to form the
`
`transistor source and drains.” ’418 Patent at 1:16-20.
`
` However, one design trade-off here is that straining techniques, such
`
`as compressive strain or tensile strain, introduce “a number of constraints into the
`
`layout process.” Id. at 1:26-58. For example, shorter diffusion regions that are
`
`provided for individual transistors may relax the strain and reduce the enhancement
`
`in the transistor strength compared to longer diffusion regions, or continuous
`
`diffusion regions, that are shared by multiple transistors. Id. On the other hand,
`
`implementing continuous diffusion regions shared by multiple transistors may
`
`cause one or more of the multiple transistors to be electrically shorted. Id.
`
` One solution noted in the ’418 Patent is to use a blocking transistor to
`
`isolate two neighboring transistors. Id. at 1:66-2:10. For example, as shown in the
`
`’418 Patent’s FIG. 2 below, a blocking transistor 201 may be used to isolate
`
`transistors 100 and 101. Id. The “diffusion region 200 is continuous for both
`
`transistors such that it can develop adequate lattice strain for satisfactory transistor
`
`strength.” Id. at 1:64-66.
`
`8
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`
`
` Yet, the introduction of a blocking transistor results in another trade
`
`off with chip density. In particular, the ’418 Patent explains that when blocking
`
`transistors were used, chip density decreased and layout designs became difficult
`
`to implement at the desired density. Id. at 2:10-18.
`
`Layout for Implementing High-Density Circuit with sufficient transistor
`strength
`
` To address the limitations and trade-offs noted above, the ’418 Patent
`
`discloses a circuit architecture that purportedly “provide[d] an advantageously
`
`dense local interconnect coupling for blocking transistors”. Id. at 5:49-41. An
`
`aerial layout view of the circuit implementation proposed by the ’418 Patent is
`
`provided in FIGS. 4A and 4B (reproduced below).
`
`9
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`’418 Patent at FIGS. 4A (left) and 4B (right) (with colored annotations)
`
`
`
`
`
` As shown in FIGS. 4A and 4B, the ’418 Patent proposes
`
`implementing a blocking transistor 430 between two transistors, a first transistor
`
`405 and a second transistor 420, all in a common diffusion region OD 400. Id. at
`
`6:6-29. The following sentences from the ’418 Patent describe the layouts in
`
`FIGS. 4A and 4B.
`
`
`
`“A gate layer 410, a gate layer 425, and a gate layer 415 form the
`
`gates for transistor 405, blocking transistor 430, and transistor 420, respectively.”
`
`Id. at 6:15-17. “A gate-directed local interconnect 440 couples (through a
`
`corresponding level 1 gate-directed interconnect, which is not illustrated) to a drain
`
`10
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`(D) for transistor 405. Similarly, a gate-directed local interconnect 435 couples to
`
`a source for transistor 420. A via V0 coupled to gate-directed local interconnect
`
`435 provides the appropriate source voltage for transistor 420.” Id. at 6:17-23.
`
`
`
`In the ’418 Patent, "gated-directed" appears to refer to layers and
`
`elements that extend according to a "gate-layer" pitch or parallel to a gate structure,
`
`and "diffusion-directed" appears to refer to layers or elements that "extend in a
`
`diffusion-directed direction that is generally orthogonal to the gate-directed
`
`direction." Id. at 2:36-44.
`
`
`
`In FIG. 4A, a diffusion-directed local interconnect 445 “couples
`
`between gate layer 425 and gate-directed local interconnect 435 to provide the bias
`
`to gate layer 425 to turn blocking transistor 430 fully off.” Id. at 6:36-39. In FIG.
`
`4B, similarly, “a diffusion-directed local interconnect 450 couples between gate-
`
`directed local interconnect 435 and gate layer 425 analogous to the coupling
`
`provided by diffusion-directed local interconnect 445 of Figure 4A.” Id. at 7:9-12.
`
`In my opinion, the main difference between FIGS. 4A and 4B is the location of the
`
`diffusion-directed local interconnect. For example, in FIG. 4B, the diffusion-
`
`directed local interconnect 450 overlaps a portion of the diffusion region OD 400.
`
`In contrast, in FIG. 4A, the diffusion-directed local interconnect 450 does not
`
`11
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`overlap any portion of the diffusion region OD 400, and is placed outside of the
`
`diffusion region OD 400.
`
`
`
`In addition to the layout of transistors in a circuit, as indicated by the
`
`Abstract and Summary of the ’418 Patent, an important aspect of the ’418 Patent is
`
`the local interconnect structure “that includes a gate-directed local interconnect
`
`coupled to an adjacent gate layer through a diffusion-directed local interconnect.”
`
`’418 Patent at Abstract, 2:44-67. FIG. 3 (shown below) depicts a lateral view or
`
`vertical profile of the interconnect structures.
`
` The interconnect structure includes three levels of interconnects
`
`formed between the diffusion region 305 and a first metal layer M1. The first level
`
`
`
`12
`
`’418 Patent at FIG. 3 (with colored annotations)
`
`
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`of interconnects include interconnects Llc 310 and gate layer 300. Id. at 4:5-17,
`
`4:44-46. The first level of interconnects are formed on the continuous diffusion
`
`region 305 and provide direct electrical coupling to diffusion region 305. Id.
`
`Level 1 local interconnects must be gate-directed local interconnects. Id. at 4:47-
`
`50.
`
` The second level of interconnects include interconnects Lla 315 and
`
`Llb 320. Id. at 4:5-17. The second level of interconnects are formed between the
`
`first level and the third level of interconnects and “couple to first metal layer Ml
`
`(or higher metal layers) through vias such as a via V0.” Id. at 4:19-23. Level 2
`
`local interconnects can be either gate-directed local interconnects (e.g., 315) or
`
`diffusion-directed local interconnects (e.g., 320). Id. at 4:47-54, 2:46-49. Level 2
`
`interconnects are distinguished from level 1 interconnects in that level 1
`
`interconnects are “directly couple[d] to a continuous diffusion region” and are
`
`implemented at “the level for a gate layer.” ‘418 Patent at 4:4-23.
`
` Level 3 interconnects include vias, e.g., via V0, and are arranged
`
`between level 2 interconnects and a first metal layer Ml. Id. at 4:19-23. ‘418
`
`Patent at 4:4-23. Level 3 interconnects are distinguished from level 2
`
`interconnects in that level 2 interconnects do not include vias that connect to metal
`
`layer M1. Id.
`
`13
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
` The ’418 Patent contends that the combination of the interconnect
`
`structure shown in FIG. 3 and the layout structure shown in FIG. 4A or FIG. 4B
`
`would address the design trade-offs and issues discussed above in paragraphs. Id.
`
`at 2:10-44, 5:1-64. In particular, a blocking transistor can be implemented between
`
`two transistors so that satisfactory transistor strength and a continuous diffusion
`
`region may be provided for multiple transistors. Id. At the same time, the
`
`interconnect structure helps with providing the requisite chip density. Id. at 6:58-
`
`7:23.
`
` The embodiments disclosed in the ’418 Patent could be implemented
`
`in various types of circuits. For instance, FIGS. 5A-5C appear to disclose a diode-
`
`connected transistor in which a diffusion-directed local interconnect is used. ’418
`
`Patent at 3:20-33. FIGS. 6A-6B disclose an inverter-to-inverter circuit in which a
`
`diffusion-directed local interconnect is used. ’418 Patent at 3:34-40. Although
`
`just limited types of circuits are described in the ’418 Patent, it is my
`
`understanding that the embodiments disclosed in the ’418 Patent could be
`
`implemented in other types of circuits as well.
`
` Notwithstanding the above, as noted in Section IV, based on my
`
`knowledge and experience in the industry, prior to the Critical Date, there existed
`
`numerous products, publications, and patents that implemented or described the
`
`14
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`embodiments claimed in the ’418 patent. As detailed in Section IV below, the
`
`circuit and circuit implementations disclosed in the ’418 patent were well-known
`
`in the prior art. To the extent there was any problem to be solved in the ’418
`
`patent, it had already been solved in the prior art systems before the Critical Date.
`
`
`
`II. Level of Ordinary Skill in the Art as of the Critical Date
`
`
`
`It is my understanding that obviousness and claim interpretation,
`
`among other things, are determined, in part, from the point of view of a person of
`
`ordinary skill in the art as of the Critical Date of the ’418 Patent (“APOSITA”).
`
`APOSITA would have had a Master’s of Science Degree (or a similar technical
`
`Master’s Degree, or higher degree) in an academic area emphasizing electrical
`
`engineering or computer engineering with a concentration in semiconductors or,
`
`alternatively, a Bachelors Degree (or higher degree) in an academic area
`
`emphasizing electrical or computer engineering and having two or more years of
`
`experience in integrated circuit design and/or semiconductor processing.
`
`Additional education in a relevant field, such as computer engineering, or electrical
`
`engineering, or industry experience may compensate for a deficit in one of the
`
`other aspects of the requirements stated above. Unless noted otherwise in this
`
`15
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`Petition, references to what would have been known or understood by APOSITA
`
`refer to the knowledge of APOSITA as of the Critical Date, or before.
`
`
`
`III. Terminology
`
`
`
`I am not a lawyer. However, I have been informed that, during an IPR
`
`proceeding involving the ’418 Patent, claim terminology is given the broadest
`
`reasonable interpretation (BRI) at the time of the Critical Date. Counsel has also
`
`informed me that PTAB is considering a change of the claim interpretation
`
`standard from BRI to the Phillips standard under which the words of the claims
`
`should be given their ordinary meaning.
`
`
`
`I have been requested to provide some guidance in this proceeding
`
`with respect to the terms below. In response to the request, I considered the
`
`context of the terms within the claims, use of the terms within the specification, my
`
`understanding of how APOSITA would have understood the terms as of the
`
`Critical Date, and have provided my interpretation below. I have used the Critical
`
`Date as the point in time for claim interpretation purposes, although in many cases
`
`the same analysis would hold true even at an earlier time than the Critical Date.
`
`
`
`
`
`16
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`A.
`
`“ means” for coupling
`
` Based on my review, I believe the “means” in “means for coupling,”
`
`as recited in claims 17-19 encompasses a “diffusion-directed local interconnect.”
`
`
`
`I base my opinion, in part, from the disclosure in the ’418 Patent,
`
`which states that “[t]he diffusion-directed local interconnect [ ] serves as a means
`
`for coupling one of the gate-directed local interconnects to the gate layer.” ’418
`
`Patent at 5:62-64. The “diffusion-directed local interconnect 445 [ ] couples
`
`between gate layer 425 and gate-directed local interconnect 435” and “diffusion-
`
`directed local interconnect 450 couples between gate-directed local interconnect
`
`435 and gate layer 425 analogous to the coupling provided by diffusion-directed
`
`local inter-connect 445.” ’418 Patent at 6:36-38, 7:9-12; see also FIGS. 4A, 4B,
`
`5A, 5B. Based on this explicit description in the ’418 Patent, in my opinion, the
`
`“means” in “means for coupling” encompasses a “diffusion-directed local
`
`interconnect.”
`
`B.
`
`“continuous” diffusion region
`
` Based on my review of the ’418 Patent, my understanding is that the
`
`“continuous” in “continuous diffusion region,” as recited in claims 2-4, 9, 14, 15,
`
`and 17-20, encompasses a diffusion region that does not include any isolation
`
`region.
`
`17
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`
`
` Here again, I base my opinion, in part, from the disclosure in the ’418
`
`Patent. A continuous diffusion region 200 is shown in FIG. 2 of the ’418 Patent
`
`(shown below) to be located between the annotated red lines and extending from
`
`the right to the left sides of FIG. 2. ’418 Patent at 1:59-1:66. The depicted
`
`continuous diffusion region 200 includes doped regions such as p-type doped
`
`regions for a PMOS transistor or n-type doped regions for a NMOS transistor, and
`
`may include multiple source and drain regions. ’418 Patent at 2:2-2:10, FIG. 2.
`
`This is a well-known composition of a continuous diffusion region, as indicated by
`
`the label of “PRIOR ART” on FIG. 2. The multiple source and drain regions and
`
`gate layers 110, 120, 205 correspond, respectively, to multiple transistors 100, 102,
`
`201 that are implemented in the single continuous diffusion region. ’418 Patent at
`
`5:9-24. For example, a single continuous diffusion region 200 is implemented for
`
`transistors 100, 101, and blocking transistor 201. ’418 Patent at 1:66-2:10.
`
`18
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`Transistor
`
`Blocking
`transistor
`
` Transistor
`
`Source
`
`Drain
`
`Continuous
`Diffusion
`Region
`
`Source
`
`Drain
`
`polysilicon
`gate layer
`
`polysilicon
`gate layer
`
`polysilicon
`gate layer
`
`
`
`’418 Patent at FIGS. 2 (with colored annotations)
`
` While the ’418 Patent illustrates a continuous diffusion region 200, I
`
`could not locate an express definition of a “continuous” diffusion region in the
`
`’418 Patent. However, based on my knowledge and experience in this area, I am
`
`aware that a diffusion region is referred to as “continuous” when it does not
`
`include any isolation regions (e.g., shallow trench isolation, local oxidation of
`
`silicon (LOCOS) regions) thereby allowing the diffusion region 200 to be
`
`uninterrupted or “continuous.” My understanding of a “continuous” diffusion
`
`region, as depicted in the’418 Patent, is consistent with the interpretation other
`
`references and persons of ordinary skill in the art would have. For example, as
`
`shown in Chang’s FIG. 3A below, regions 306, 308, 310, and 312 are each
`
`continuous diffusion regions which are separated by isolation regions 314 but do
`
`19
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`not include any isolation region within the respective regions 306, 308, 310, and
`
`312. Chang at 3:11-17. Accordingly, in my opinion, the “continuous” in
`
`“continuous diffusion region” recited in the’418 Patent would be correctly
`
`understood as encompassing a diffusion region that does not include any isolation
`
`region.
`
`Continuous
`diffusion
`regions
`
`Isolation
`regions
`
`
`
`Chang at FIG. 3A (with colored annotations)
`
`
`
`
`
`
`
`20
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`IV. Discussion of References
`
` The following exemplary references demonstrate the prevalence of the
`
`claimed features in the prior art.
`
`A. Yoshida
`
` Yoshida describes implementations of a ring oscillator (also referred
`
`to as semiconductor device 10 in Yoshida) that includes an odd number of
`
`inverters. Yoshida at 1:7-15, 1:53-67. Yoshida describes problems with ring
`
`oscillators that are implemented in a small area, and, in particular, that the “desired
`
`operational speed [of the ring oscillator] cannot be obtained.” Id. at 1:21-25. The
`
`reduced operations speed can be attributed to parasitic capacitance between various
`
`elements in the ring oscillator. Id. at 1:25-48.
`
` To reduce parasitic capacitance and improve ring oscillator
`
`operational speed, Yoshida discloses particular implementations of ring oscillators
`
`using MOS transistors. Id. at 4:66-5:5; Abstract. An example of an
`
`implementation is shown below in Yoshida’s FIG. 4.
`
`21
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`PMOS
`section
`
`NMOS
`section
`
`
`
`Yoshida at FIG. 4 (with colored annotations)
`
`Yoshida’s FIG. 4 depicts a ring oscillator that includes a PMOS section 31
`
`and a NMOS section 32. Yoshida at 8:58-65. “The PMOS section 31 and NMOS
`
`section 32 are arranged in parallel to each other in the lengthwise direction, with
`
`the pMOS transistors 14-1 to 14-3 of PMOS section 31 and the respective nMOS
`
`transistors 14-1 to 14-3 of NMOS section 32 opposing each other.” Id. at 8:65-9:3.
`
`22
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`Yoshida’s FIG. 1 (included below) provides a more detailed view of the PMOS
`
`section 31.
`
`
`
`
`Dummy gates
`
`Drain regions
`
`Transistors
`
`Source
`regions
`
`Gate
`Electrode
`12
`
`
`
`Yoshida at FIG. 1 (with colored annotations)
`
` As shown in FIG. 1, a “single pMOS transistor 14 is configured by a
`
`single drain region 13b, a pair of source regions 13a on both sides of the drain
`
`region 13b, and a pair of (normal) gate electrodes 12 formed on the semiconductor
`
`substrate 11 at the portion between the source 13a and drain region 13b. The
`
`depicted portion of the semiconductor device 10 includes therein three transistors
`
`14-1, 14-2, and 14-3. The source regions 13a formed in the vicinity of both the
`
`23
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`edges of the semiconductor substrate 11 outside the corresponding dummy gate
`
`electrode 12a are dummy sources.” Id. at 7:32-41. “[G]ate electrodes 12 [are]
`
`arranged at a constant pitch or constant interval on the semiconductor substrate
`
`11.” Id. at 2:5-6. “The dummy gate electrodes 12a are maintained at the same
`
`potential as the potential of the source regions 13a [ ] by using interconnects not
`
`shown.” Id. at 7:28-31. My understanding is that the lines shown in red in FIG. 1
`
`depict the connection between the dummy gate electrodes 12a and the source
`
`regions 13a, although the interconnects used to implement such connections are
`
`not depicted in Yoshida. Id. at 7:28-31.
`
` More details of Yoshida’s pMOS section 31 are provided in Yoshida’s
`
`FIG. 2, shown below, which “is a sectional view taken along II-II line in FIG. 1.”
`
`Id. at 5:37-38.
`
`first-layer source line
`
`first-layer drain line
`
`Source
`region
`
`Dummy gate
`
`Drain region Gate Electrode
`Yoshida at FIG. 2 (with colored annotations)
`
`
`
`24
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
` FIG. 2 depicts the drain regions 13b, source regions 13a, gate
`
`electrodes 12, dummy gate 12a formed on the semiconductor substrate 11, as
`
`described above with reference to FIG. 1. In addition, FIG. 2 shows a first-layer
`
`source line/interconnect 17a and a first-layer drain line/interconnect 17b. The
`
`“first-layer source line 17a is connected via the first-layer source contacts 16a
`
`disposed adjacent to each other to the source regions 13a.” Yoshida at 7:41-43,
`
`2:38-40. The first-layer drain line/interconnect 17b is connected via the first-layer
`
`drain contacts 16b to the drain regions 13b. Id. at 2:31-48. Lines 17a and 17b
`
`function as local interconnects that connect to the source regions 13a and drain
`
`regions 13b, respectively. See Id. at 7:46, 2:57.
`
`
`
`In my opinion, the subject matter in Yoshida is similar to the ’418
`
`Patent at least because both relate to implementing semiconductor devices in a
`
`small area, and disclose efficient semiconductor layout techniques to optimize the
`
`usage of the chip or substrate area. For instance, in Yoshida, the semiconductor
`
`device 10 (ring oscillator) includes gate electrodes 12/12a that are implemented at
`
`a constant pitch and a single dummy gate electrode 12a is shared for two different
`
`transistors. The reduction of a dummy gate electrode 12a and use of constant gate
`
`pitches are just some examples of how Yoshida reduces the chip area required to
`
`implement its semiconductor device 10. Yoshida at 2:5-6, 7:25. The following
`
`25
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
`explanation provides a more detailed description of Yoshida’s efficient layout
`
`implementation.
`
` Below I have provided a simplified version of Yoshida’s FIG. 1. The
`
`depiction below, consistent with Yoshida’s FIG. 1, illustrates a series of transistors
`
`14 attached to each other by dummy gate electrodes 12a and bordered at two ends
`
`by dummy sources 13a and dummy gates 12a. Yoshida at 7:36-41.
`
`
`
`Dummy
`source 13a
`
`
`
`mos
`
`p
`
`1
`
`mos
`
`p
`
`1
`
`
`
`
`
`mos
`
`p
`
`1
`
`
`
`4
`4
`4
`Dummy gate electrodes 12a
`(
`(
`(
`
`Dummy
`source 13a
`
`14-3)
`14-1)
`14-2)
` Two dummy gate electrodes 12a are disposed at two ends of each
`
`transistor cell e.g., left and right border of the transistor cell. Yoshida at 7:23-41.
`
`
`
`
`
`
`
`
`
`
`
`
`
`p
`
`1
`
`mos
`
`4
`
`Dummy gate electrodes 12a
`
`26
`
`

`

`Declaration of Dr. David Kuan-Yu Liu
`U.S. Patent No.: 9,024,418
`Attorney Docket No.: 39521-0045IP2
`
`
` The equivalent depiction of this cell in Yoshida’s FIGS. 1 and 2
`
`would appear as follows:
`1
`
`1
`
`2a
`
`12a
`
`2a
`
`12a
`
`
`
`
`12a
` (portion of FIG. 1) (portion of FIG. 2)
`
`
`
`12a
`
` To implement high density circuits with multiple transistors, Yoshida
`
`arranges multiple transistor cells next to each other to form a gate array structure.
`
`To optimize utilization of chip real estate and because the dummy gate electrode
`
`12a of each PMOS transistor is tied to a common power source line such as Vdd,
`
`two neighboring transistors cells can be combined, t

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket