111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US007919787B2
`
`c12) United States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,919,787 B2
`*Apr. 5, 2011
`
`(54) SEMICONDUCTOR DEVICE WITH A LIGHT
`EMITTING SEMICONDUCTOR DIE
`
`(75)
`
`Inventors: Kong Weng Lee, San Jose, CA (US);
`Kee Yean Ng, Penang (MY); Yew
`Cheong Kuan, Penang (MY); Cheng
`Why Tan, Penang (MY); Gin Ghee Tan,
`Penang (MY)
`
`(73) Assignee: Avago Technologies ECBU IP
`(Singapore) Pte. Ltd. (SG)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 494 days.
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 11/838,301
`
`(22) Filed:
`
`Aug. 14, 2007
`
`(65)
`
`Prior Publication Data
`
`US 2007/0272940 AI
`
`Nov. 29, 2007
`
`Related U.S. Application Data
`
`(63) Continuation-in-part of application No. 10/608,605,
`filed on Jun. 27, 2003, now Pat. No. 7,256,486.
`
`(51)
`
`Int. Cl.
`(2010.01)
`HOJL 33100
`(2010.01)
`HOJL 23148
`(52) U.S. Cl. .................. 257/99; 257/778; 257/E33.056;
`257/E33.062; 257/E33.065; 257/E33.066
`(58) Field of Classification Search . ... ... ... ... .. ... .. 257/99,
`257/778, E33.056, E33.062, E33.065, E33.066
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`2,907,925 A
`10/1959 Parsons
`4,843,280 A * 6/1989 Lumbard et al ............... 313/500
`
`5,006,673 A
`5,177,593 A
`5,298,687 A
`5,440,075 A
`5,640,048 A
`5,670,797 A
`5,986,885 A
`6,084,295 A
`6,191,477 B1
`6,242,280 B1 *
`6,262,513 B1 *
`6,268,654 B1
`6,362,525 B1
`6,383,835 B1
`6,392,294 B1 *
`6,620,720 B1
`
`4/1991 Freyman eta!.
`111993 Abe
`3/1994 Rapoport et a!.
`8/1995 Kawakita eta!.
`6/1997 Selna
`9/1997 Okazaki
`1111999 Wyland
`7/2000 Horiuchi et a!.
`2/2001 Hashemi
`6/2001 Koay eta!. .................... 438/106
`7/2001 Furukawa eta!.
`310/313 R
`7/2001 Glenn et a!.
`3/2002 Rahim
`5/2002 Hata eta!.
`5/2002 Yamaguchi ................... 257/690
`9/2003 Moyer et a!.
`(Continued)
`
`OTHER PUBLICATIONS
`
`Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., "Hand(cid:173)
`book of Multilevel Metallization for Integrated Circuits," Noyes
`Pub!., Westwood, New Jersey (1993), pp. 868-872.
`
`(Continued)
`
`Primary Examiner- Shouxiang Hu
`
`(57)
`
`ABSTRACT
`
`A semiconductor device includes a light emitting semicon(cid:173)
`ductor die mounted on at least one of first and second elec(cid:173)
`trically conductive bonding pads, which are located on a first
`major surface of a substrate of the device. The light emitting
`semiconductor die has an anode and a cathode, which are
`electrically connected to the first and second electrically con(cid:173)
`ductive bonding pads. The semiconductor device further
`includes first and second electrically conductive connecting
`pads, which are located on a second major surface of the
`substrate. The first and second electrically conductive bond(cid:173)
`ing pads are electrically connected to the first and second
`electrically conductive connecting pads via first and second
`electrically conductive interconnecting elements.
`
`14 Claims, 10 Drawing Sheets
`
`- ./..1~~- -
`
`-
`
`1- -
`I
`I
`
`750
`
`762
`760
`-;.:{-I ~~.:
`I l
`I
`I
`l
`----1
`I ' - '
`' - ' I
`
`·---
`
`,~aoo
`
`710
`
`760~
`
`/730
`
`770
`
`752
`(
`
`750
`J-~62
`/732
`
`,~aoo
`
`712
`1/
`710
`.1--772
`714
`
`712
`
`740
`
`742
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`US 7,919,787 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`6,707,247 B2
`3/2004 Murano
`6,828,510 B1
`12/2004 Asai et al.
`8/2006 Teng
`7,098,593 B2
`7,256,486 B2 * 8/2007 Lee et al ....................... 257/690
`2002/0139990 A1
`10/2002 Suehiro eta!.
`2002/0179335 A1
`12/2002 Curcio eta!.
`2003/0017645 A1
`112003 Kabayashi eta!.
`2003/0020126 A1
`112003 Sakamoto et a!.
`2003/0040138 A1
`2/2003 Kabayashi eta!.
`2003/0168256 A1
`9/2003 Chien
`
`2004/0222433 A1 * 1112004 Mazzochette et al ........... 257/99
`
`OTHER PUBLICATIONS
`
`Electronic Packaging and Production, "Innovative PCB Reinforce(cid:173)
`ment," (Feb. 1997), p. 1.
`Johannes Adam, "New Correlations Between Electrical Current and
`Temperature Rise in PCB Traces," Proc. 20th IEEE Semi-Therm
`Symp., (Mar. 2004), pp. 1-8.
`* cited by examiner
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 1 of 10
`
`US 7,919,787 B2
`
`FIG.1 A
`
`100
`
`FIG.2A
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 2 of 10
`
`US 7,919,787 B2
`
`110 112
`"\
`~--
`
`FIG.1 B
`................ ~
`1F
`
`r130
`
`HJO
`
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`
`122 (132
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`·~"
`
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`L.__._ _ _ . __ .. ___________ __ .
`
`FIG. 1 F
`
`FIG.1 E
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 3 of 10
`
`US 7,919,787 B2
`
`132
`
`120
`
`FIG.2B
`2F 252
`
`110
`
`- - - ! - - -
`- - -----+-------·-··--
`2F
`FIG.2D
`
`100
`
`FIG.2C
`
`11
`
`254
`
`200/252
`FIG.2F
`
`FIG.2E
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 4 of 10
`
`US 7,919,787 B2
`
`FIG.4A
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 5 of 10
`
`US 7,919,787 B2
`
`300
`
`310 312
`~ ~-
`
`FIG.38
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`
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`FIG. 3D
`
`300
`
`FIG.3C
`
`FIG.3F
`
`FIG.3E
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 6 of 10
`
`US 7,919,787 B2
`
`250
`
`320
`FIG.4B
`
`r)
`310
`
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`312
`4F 300/400
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`330
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`
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`~--+-~~----~~
`
`400
`
`31
`
`250
`
`400/
`FIG.4F
`
`FIG.4E
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 7 of 10
`
`US 7,919,787 B2
`
`518
`
`;r J
`
`FIG.5A
`
`519
`)
`
`1 r 1
`
`FIG. 58
`
`512
`
`530
`
`532
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`531
`
`~~=r==t==~..............,~:::::r---""""'"==:::;;:=::*::::::==-,-+-·-
`542 522
`541
`521
`543 _.- 523
`
`I
`
`I
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 8 of 10
`
`US 7,919,787 B2
`
`l
`l
`
`'
`'
`
`520
`
`542.- 522
`
`521
`
`523
`
`FIG.6A
`
`FIG.6B
`
`520
`
`542- 522
`
`541 ___.
`
`521
`
`543-' 523
`
`FIG.6C
`
`521
`
`543- 523
`
`FIG.6D
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 9 of 10
`
`US 7,919,787 B2
`
`740
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`
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`
`\
`742
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`U.S. Patent
`
`Apr. 5, 2011
`
`Sheet 10 of 10
`
`US 7,919,787 B2
`
`,~aoo
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`740
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`
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`
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`10
`
`740
`
`........
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`1
`SEMICONDUCTOR DEVICE WITH A LIGHT
`EMITTING SEMICONDUCTOR DIE
`
`2
`mount a semiconductor die that requires a high-temperature
`die attach process in a conventional packaging device.
`
`US 7,919,787 B2
`
`RELATED APPLICATION
`
`SUMMARY OF THE INVENTION
`
`This application is a continuation-in-part of U.S. patent
`application Ser. No. 10/608,605, filed Jun. 27,2003 now U.S.
`Pat. No. 7,256,486, which is related to U.S. patent application
`Ser. No. 10/608,606, filed Jun. 27, 2003. Both disclosures are
`specifically incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`Many types of conventional semiconductor device are
`composed of a semiconductor die mounted in a packaging
`device. One type of packaging device widely used in the
`industry includes a metal lead frame. A metallization layer of
`aluminum located on the bottom surface of the semiconduc-
`tor die is bonded to a conductive surface that forms part of the
`lead frame to attach and electrically connect the die to the lead
`frame. Additionally, electrical connections are made between
`bonding pads on the top surface of the die and other leads of
`the lead frame to provide additional electrical connections to
`the die. The lead frame and semiconductor die are then encap(cid:173)
`sulated to complete the semiconductor device. The packaging
`device protects the semiconductor die and provides electrical
`and mechanical connections to the die that are compatible
`with conventional printed circuit board assembly processes.
`In such conventional semiconductor devices, the bottom 30
`surface of the die is typically bonded to the conductive surface
`of the lead frame using a silver epoxy adhesive that cures at a
`relatively low temperature, typically about 120° C. The cur(cid:173)
`ing temperature of the silver epoxy adhesive is compatible
`with the other materials of the packaging device.
`The volume of the packaging device used in such conven(cid:173)
`tional semiconductor devices, i.e., the lead frame and the
`encapsulant, is typically many times that of the semiconduc-
`tor die. This makes such conventional semiconductor devices
`unsuitable for use in applications in which a high packing 40
`density is required. A high packing density allows miniatur(cid:173)
`ization and other benefits. Therefore, what is needed is a
`semiconductor packaging device that is comparable in vol(cid:173)
`ume with the semiconductor die and that is compatible with
`conventional printed circuit board assembly processes.
`Recently, semiconductor die having a substrate surface
`metallization layer of a gold-tin alloy (80% Au:20% Sn
`approximately) have been introduced in light-emitting
`devices. Such semiconductor die typically have a substrate of
`sapphire, silicon carbide or a Group III-V semiconductor 50
`material, such as gallium arsenide. Semiconductor devices
`having substrates of the first two substrate materials have
`layers of Group III-V semiconductor materials, such as gal(cid:173)
`lium nitride, deposited on their substrates. The die attach
`process for such semiconductor die uses a gold-tin eutectic, 55
`which has a melting point of about 280° C. Temperatures as
`high as about 350° C. can be encountered in the die attach
`process for such die. Such high temperatures are incompat(cid:173)
`ible with the materials of many conventional packaging
`devices. Thus, what is also needed is a packaging device for 60
`semiconductor die that use a high-temperature die attach
`process.
`Many printed circuit assembly processes and assembly
`equipment require the use of standard semiconductor device
`packages. Modifying such processes to use a new semicon(cid:173)
`ductor device package can be expensive and can interrupt
`production. Therefore, what is additionally needed is a way to
`
`10
`
`A semiconductor device includes a light emitting semicon(cid:173)
`ductor die mounted on at least one of first and second elec(cid:173)
`trically conductive bonding pads, which are located on a first
`major surface of a substrate of the device. The light emitting
`semiconductor die has an anode and a cathode, which are
`electrically connected to the first and second electrically con-
`ductive bonding pads. The semiconductor device further
`includes first and second electrically conductive connecting
`pads, which are located on a second major surface of the
`15 substrate. The first and second electrically conductive bond(cid:173)
`ing pads are electrically connected to the first and second
`electrically conductive connecting pads via first and second
`electrically conductive interconnecting elements.
`A semiconductor device in accordance with an embodi-
`20 ment of the invention includes a substantially planar sub(cid:173)
`strate, first and second electrically conductive bonding pads,
`a light emitting semiconductor die, first and second electri(cid:173)
`cally conductive connecting pads, and first and second elec(cid:173)
`trically conductive interconnecting elements. The substan-
`25 tially planar substrate has first and second major surfaces. The
`first and second major surfaces are opposed surfaces. The first
`and second electrically conductive bonding pads are located
`on the first major surface. The light emitting semiconductor
`die has at least one of an anode and a cathode on a bottom
`major surface of the light emitting semiconductor die. The
`anode and the cathode of the light emitting semiconductor die
`are electrically connected to the first and second electrically
`conductive bonding pads. The semiconductor light emitting
`die is mounted on at least the first electrically conductive
`35 bonding pad such that one of the anode and the cathode on the
`bottom major surface of the light emitting semiconductor die
`is electrically connected to the first electrically conductive
`bonding pad. The first and second electrically conductive
`connecting pads are located on the second major surface. The
`first electrically conductive interconnecting element is elec(cid:173)
`trically connected to the first electrically conductive bonding
`pad and the first electrically conductive connecting pad. The
`second electrically conductive interconnecting element is
`electrically connected to the second electrically conductive
`45 bonding pad and the second electrically conductive connect(cid:173)
`ing pad. In an embodiment, at least one of the first and second
`electrically conductive interconnecting elements is located
`on at least one sidewall of the substantially planar substrate.
`A semiconductor device in accordance with another
`embodiment of the invention includes a substantially planar
`substrate, first and second electrically conductive bonding
`pads, a light emitting semiconductor die, first and second
`electrically conductive connecting pads, and first and second
`electrically conductive interconnecting elements. The sub-
`stantially planar substrate has first and second major surfaces.
`The first and second major surfaces are opposed surfaces. The
`first and second electrically conductive bonding pads are
`located on the first major surface. The light emitting semi(cid:173)
`conductor die has an anode and a cathode on a bottom major
`surface of the light emitting semiconductor die. The semicon(cid:173)
`ductor light emitting die is mounted on the first and second
`electrically conductive bonding pads such that the anode of
`the light emitting semiconductor die is electrically connected
`to the first electrically conductive bonding pad and the cath-
`65 ode of the light emitting semiconductor die is electrically
`connected to the second electrically conductive bonding pad.
`The first and second electrically conductive connecting pads
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`US 7,919,787 B2
`
`3
`are located on the second major surface. The first electrically
`conductive interconnecting element is electrically connected
`to the first electrically conductive bonding pad and the first
`electrically conductive connecting pad. The second electri(cid:173)
`cally conductive interconnecting element is electrically con(cid:173)
`nected to the second electrically conductive bonding pad and
`the second electrically conductive connecting pad
`Other aspects and advantages of the present invention will
`become apparent from the following detailed description,
`taken in conjunction with the accompanying drawings, ill us- 10
`trated by way of example of the principles of the invention.
`
`4
`ment 122 is electrically conductive and is located in through
`hole 118. Mounting pad 130 and bonding pad 132 are elec(cid:173)
`trically conductive, are separate from one another and are
`located on the portions of the major surface 112 of substrate
`110 in which through holes 116 and 118 are respectively
`located. Connecting pads 140 and 142 are electrically con(cid:173)
`ductive, are separate from one another and are located on the
`portions of the major surface 114 of substrate 110 in which
`through holes 116 and 118 are respectively located.
`Mounting pad 130 and connecting pad 140 are electrically
`connected to opposite ends of interconnecting element 120.
`Thus, interconnecting element 120 extending through sub(cid:173)
`strate 110 in through hole 116 electrically connects mounting
`pad 130 to connecting pad 140. Bonding pad 132 and con-
`15 necting pad 142 are electrically connected to opposite ends of
`interconnecting element 122. Thus, interconnecting element
`122 extending through substrate 110 in through hole 118
`electrically connects bonding pad 132 to connecting pad 142.
`The material of substrate 110 is a thermally-conductive
`20 ceramic such as alumina or beryllia. In an embodiment, the
`material of the substrate was Kyocera.RTM. Type A440
`ceramic sold by Kyocera Corp., of Kyoto, Japan. Typical
`dimensions of the substrate are in the range from about 0.5
`mm square to about 2 mm square. Rectangular configurations
`25 are also possible. Alternative substrate materials include
`semiconductors, such as silicon, and epoxy laminates, such as
`those used in printed-circuit boards. Other materials that have
`a high thermal conductivity and a low electrical conductivity
`can be used instead of those exemplified above. The coeffi-
`30 cient of thermal expansion of the substrate material relative to
`that of the semiconductor die to be mounted on packaging
`device 100 should also be considered in choosing the sub(cid:173)
`strate material.
`As will be described in more detail below, substrate 110 is
`35 part of a wafer (not shown) from which typically several
`hundred packaging devices 100 are fabricated by batch pro(cid:173)
`cessing. After fabrication of the packaging devices, the wafer
`is singulated into individual packaging devices. Alternatively,
`the packaging devices may be left in wafer form after fabri-
`40 cation. In this case, singulation is not performed until after at
`least a die attach process has been performed to attach a
`semiconductor die to each mounting pad 130 on the wafer. In
`some embodiments, wafer-scale wire bonding, encapsulation
`and testing are also performed prior to singulation. Full elec-
`45 trical testing, including light output testing, may be per(cid:173)
`formed on the wafer.
`The material of interconnecting elements 120, 122 is metal
`or another electrically-conductive material. In an embodi(cid:173)
`ment, the material of the interconnecting elements is tung-
`50 sten, but any electrically-conductive material capable of
`forming a low-resistance electrical connection with the pads,
`i.e., mounting pad 130, bonding pad 132 and connecting pads
`140, 142, and capable of withstanding the temperature of the
`die-attach process may be used. As noted above, packaging
`55 device 100 may be subject to a temperature as high as about
`350° C. when a gold-tin eutectic is used to attach a semicon(cid:173)
`ductor die to the mounting pad 130 of the packaging device.
`Interconnecting elements 120, 122 may be located relative to
`mounting pad 130 and bonding pad 132, respectively, else-
`60 where than the centers shown. Moreover, more than one inter(cid:173)
`connecting element may be located within either or both of
`the mounting pad and the bonding pad.
`The material of pads 130, 132, 140, 142 is metal or another
`electrically-conductive material. Important considerations in
`65 selecting the material of the pads are adhesion to substrate
`110, an ability to form a durable, low-resistance electrical
`connection with interconnecting elements 120 and 122 and an
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A, lB, 1C, 1D, 1E and 1F are respectively an
`isometric view, a side view, a front view, a top view, a bottom
`view and a cross-sectional view of a first embodiment of a
`packaging device in accordance with the invention. The
`cross-sectional view ofFIG. 1F is along the section line 1F -1F
`inFIG.lD.
`FIGS. 2A, 2B, 2C, 2D, 2E and 2F are respectively an
`isometric view, a side view, a front view, a top view, a bottom
`view and a cross-sectional view of a first embodiment of a
`semiconductor device in accordance with the invention. The
`cross-sectional view ofFIG. 2F is along the section line 2F -2F
`in FIG. 2D.
`FIGS. 3A, 3B, 3C, 3D, 3E and 3F are respectively an
`isometric view, a side view, a front view, a top view, a bottom
`view and a cross-sectional view of a second embodiment of a
`packaging device in accordance with the invention. The
`cross-sectional view ofFIG. 3F is along the section line 3F-3F
`in FIG. 3D.
`FIGS. 4A, 4B, 4C, 4D, 4E and 4F are respectively an
`isometric view, a side view, a front view, a top view, a bottom
`view and a cross-sectional view of a second embodiment of a
`semiconductor device in accordance with the invention. The
`cross-sectional view ofF I G. 4F is along the section line 4 F -4 F
`in FIG. 4D.
`FIGS. SA-SCare side views illustrating a method in accor(cid:173)
`dance with the invention for fabricating a packaging device
`for a semiconductor die.
`FIG. SD is a side view illustrating an optional additional
`process that may be included in the method illustrated in
`FIGS. SA-SC.
`FIGS. 6A-6D are side views illustrating a method in accor(cid:173)
`dance with the invention for fabricating a semiconductor
`device.
`FIGS. 7A and 7B are respectively a top view and a side
`view of a semiconductor device in accordance with another
`embodiment of the invention.
`FIGS. SA, SB and SC are respectively a top view and
`different side views of a semiconductor device in accordance
`with another embodiment of the invention.
`
`DETAILED DESCRIPTION
`
`FIGS. 1A-1F are schematic diagrams illustrating a first
`exemplary embodiment 100 of a packaging device for a semi(cid:173)
`conductor die in accordance with the invention. Packaging
`device 100 is composed of a substrate 110, interconnecting
`elements 120 and 122, a mounting pad 130, a bonding pad
`132 and connecting pads 140 and 142 (FIG. 1E).
`Substrate 110 is substantially planar, has opposed major
`surfaces 112 and 114 and defines through holes 116 and 118
`that extend through the substrate between major surfaces 112
`and 114. Interconnecting element 120 is electrically conduc(cid:173)
`tive and is located in through hole 116. Interconnecting ele-
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`US 7,919,787 B2
`
`5
`ability to withstand the temperature of the die attach process.
`In an embodiment, the structure of the pads is a seed layer of
`tungsten covered with layer of nickel about 1.2 f.tm to about
`8.9 flill thick that is in tum covered with a layer of gold about
`0.75 flill thick. Other metals, alloys, conductive materials and
`multi-layer structures of such materials can be used.
`Packaging device 100 is used to package a semiconductor
`die. A semiconductor device in which a semiconductor die is
`packaged using packaging device 100 described above will
`be described next.
`FIGS. 2A-2F are schematic diagrams illustrating an exem(cid:173)
`plary embodiment 200 of a semiconductor device in accor(cid:173)
`dance with the invention. Semiconductor device 200 incor(cid:173)
`porates packaging device 100 in accordance with the
`invention. Elements of semiconductor device 200 that corre(cid:173)
`spond to elements of packaging device 100 described above
`with reference to FIGS. 1A-1F are indicated using the same
`reference numerals and will not be described again in detail.
`Semiconductor device 200 is composed of packaging
`device 100 described above with reference to FIGS. 1A-1F, a
`semiconductor die 250, encapsulant 252 and a bonding wire
`254. In the example shown, semiconductor die 250 embodies
`a light-emitting diode and has anode and cathode electrodes
`(not shown) covering at least parts of its opposed major sur(cid:173)
`faces. Semiconductor die 250 is mounted on packaging
`device 100 with the metallization on its bottom major surface
`attached to mounting pad 130. Encapsulant 252 covers the
`semiconductor die and the part of the major surface 112 of
`substrate 100 where mounting pad 130 and bonding pad 132
`are located. Bonding wire 254 extends between a bonding pad
`located on the top major surface of semiconductor die 250 and
`bonding pad 132.
`The bonding pad on the top major surface of semiconduc(cid:173)
`tor die 250 is typically part of or connected to the anode
`electrode of the light-emitting diode. The metallization on the
`bottom major surface of semiconductor die 250 typically
`constitutes the cathode electrode of the light-emitting diode.
`Thus, the anode electrode of semiconductor die 250 is elec(cid:173)
`trically connected to connecting pad 142 by bonding wire
`254, bonding pad 132 and interconnecting element 122, and
`the cathode electrode of semiconductor die 250 is electrically
`connected to connecting pad 140 by mounting pad 130 and
`interconnecting element 120.
`Encapsulant 252 has a thickness greater than the maximum
`height of bonding wire 254 above major surface 112. In the
`example shown, the encapsulant is transparent to enable
`semiconductor device 200 to emit the light generated by
`semiconductor die 250.
`Semiconductor die 250 is composed of one or more layers
`(not shown) of any semiconductor material composed of ele(cid:173)
`ments from Groups II, III, IV, V and VI of the periodic table
`in binary, ternary, quaternary or other form. Semiconductor
`die 250 may additionally include a non-semiconductor sub(cid:173)
`strate material, such as sapphire, metal electrode materials
`and dielectric insulating materials, as is known in the art.
`In an embodiment of the above-described example in
`which semiconductor die 250 embodies a light-emitting
`diode, semiconductor die 250 is composed of a substrate of
`silicon carbide that supports one or more layers of (indium)
`gallium nitride. Such a light-emitting diode generates light in
`a wavelength range extending from ultra-violet to green. The
`bottom major surface (not shown) of the substrate remote
`from the layers of (indium) gallium nitride is coated with a
`metallization layer of a gold-tin alloy. A gold-tin eutectic
`attaches the semiconductor die to mounting pad 130, as
`described above, to provide a mechanical and electrical con(cid:173)
`nection between the semiconductor die and the mounting pad.
`
`6
`The material ofbonding wire 254 is gold. A process known
`in the art as low-loop wire bonding is used to connect the
`bonding wire between the anode electrode of semiconductor
`die 250 and bonding pad 132. Using low-loop wire bonding
`minimizes the maximum height of the bonding wire above
`substrate 110, and, therefore, reduces the overall height of
`semiconductor device 200. Other processes for providing an
`electrical connection between a bonding pad on a semicon(cid:173)
`ductor die and a bonding pad on a packaging device are
`10 known in the art and may be used instead, especially in
`applications in which device height is a less important con(cid:173)
`sideration.
`The material of encapsulant 252 is clear epoxy. Alternative
`15 encapsulant materials include silicone. Embodiments of
`semiconductor device 200 that neither emit nor detect light
`can use an opaque encapsulant.
`In the example of semiconductor device 200 described
`above, semiconductor die 250 is embodied as a light-emitting
`20 diode. Semiconductor die 250 may alternatively embody
`another type of diode without modification to packaging
`device 100. Versions of packaging device 100 maybe used to
`package semiconductor die other than those that embody
`such electrical components as diodes that have only two elec-
`25 trades. Versions of packaging device 100 may be used to
`package semiconductor die that embody such electronic cir(cid:173)
`cuit elements as transistors and integrated circuits that have
`more than two electrodes. Such versions of packaging device
`100 have a number of bonding pads, interconnecting ele-
`30 ments and connecting pads corresponding to the number of
`bonding pads located on the top major surface of the semi(cid:173)
`conductor die. For example, a version of packaging device
`100 for packaging a semiconductor die that embodies a tran(cid:173)
`sistor having collector, base and emitter electrodes, and in
`35 which the substrate metallization provides the collector elec(cid:173)
`trode, has two bonding pads, two interconnecting elements
`and two connecting pads. Wire bonds connect the emitter
`bonding pad on the semiconductor die to one of the bonding
`pads on the packaging device and the base bonding pad on the
`40 semiconductor die to the other of the bonding pads on the
`packaging device.
`The connecting pads, e.g., connecting pads 140 and 142, of
`embodiments of packaging device 100 having multiple con(cid:173)
`necting pads may be arranged to conform with an industry
`45 standard pad layout to facilitate printed circuit layout. In such
`embodiments, the interconnecting elements may be offset
`from the centers of the respective mounting pads, bonding
`pads and connecting pads to allow the connecting pad layout
`to conform with such a standard pad layout. In some embodi-
`50 ments, one or more of the mounting pad, bonding pads and
`connecting pads may have a shape that differs from the regu(cid:173)
`lar shapes illustrated. Some irregular shapes include two main
`regions electrically connected by a narrow track. For
`example, an irregularly-shaped bonding pad includes a region
`55 to which the bonding wire is attached, a region connected to
`the interconnecting element and a narrow track interconnect(cid:173)
`ing the two regions.
`Some versions of packaging device may accommodate two
`or more semiconductor die. In such versions, mounting pad
`60 130 is sized large enough to accommodate the two or more
`semiconductor die. Additionally, such versions include suffi(cid:173)
`cient bonding pads, interconnecting elements and connecting
`pads to make the required number of electrical connections to
`the semiconductor die. Alternatively, the packaging device
`65 may include two or more mounting pads. The mounting pads
`may be electrically connected to one another and thence to a
`common interconnecting element and connecting pad. Alter-
`
`EVERLIGHT ELECTRONICS CO., LTD.
`Exhibit 1001
`
`

`

`US 7,919,787 B2
`
`7
`natively, each mounting pad may be electrically connected to
`a corresponding connecting pad by a respective interconnect(cid:173)
`ing element.
`Semiconductor device 200 is used by mounting it on a
`printed circuit board or other substrate using conventional
`surface-mount techniques or other techniques known in the
`art. Semiconductor device 200 is placed on a surface of the
`printed circuit board with connecting pads 140 and 142
`aligned with respective pads on the printed circuit board. The
`printed circuit board is then passed across a solder wave to
`form a solder joint between connecting pads 140 and 142 and
`the respective pads on the printed circuit board. Alternatively,
`semiconductor device 200 may be affixed to a printed circuit
`board by a process known as infra-red reflow soldering in
`which a pattern of solder is applied to the printed circuit board
`using a stencil, semiconductor device 200 and, optionally,
`other components are loaded onto the printed circuit board
`and the printed circuit board assembly is irradiated with infra(cid:173)
`red light to heat and reflow the solder. Other processes for
`attaching electronic components to printed circuit boards are 20
`known in the art and may alternatively be used. Packaging
`device 100 and semiconductor device 200 may additionally
`include adhesive regions on the major surface 114 of substrate
`110 external to connecting pads 140 and 142 to hold the
`semiconductor device in place on the printed circuit board
`during soldering.
`In semiconductor device 200, packaging device 100 and
`encapsulant 252 collectively have a volume that is only about
`15 times the volume of semiconductor die 250. Thus, pack(cid:173)
`aging device 100 is well suited for use in high packing density
`applications. Moreover, packaging device 100 is fabricated
`from materials capable of withstanding the high temperatures
`involved in a die attach process that uses a gold-tin eutectic.
`Accordingly, packag