UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`____________
`
`Record of Oral Hearing
`Held: October 10, 2019
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`____________
`
`Record of Oral Hearing
`Held: October 10, 2019
`____________
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`SCOTT B. HOWARD, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`KEN HOOVER, ESQUIRE
`W. KARL RENNER, ESQUIRE
`TIMOTHY W. RIFFE, ESQUIRE
`WHITNEY A. REICHEL, ESQUIRE
`Fish & Richardson P.C.
`1000 Maine Avenue, S.W.
`Washington, D.C. 20024
`202-626-6447
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`DAVID B. COCHRAN, ESQUIRE
`JOSHUA R. NIGHTINGALE, ESQUIRE
`Jones Day
`North Point
`901 Lakeside Avenue
`Cleveland, Ohio 44114-1190
`216-586-7302
`
`
`
`
`The above-entitled matter came on for hearing on Tuesday, October 10,
`2019, commencing at 3:58 p.m., at the U.S. Patent and Trademark Office,
`600 Dulany Street, Alexandria, Virginia.
`
`
`
`
`
`
`
`2
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`
`P R O C E E D I N G S
`- - - - -
`JUDGE JEFFERSON: Thank you. You can be seated we'll wait for
`
`the other judges to join us, although I think they can hear us.
`
`JUDGE GALLIGAN: This is Judge Galligan in the Texas Regional
`Office. Can you hear me?
`
`JUDGE JEFFERSON: Yes, I can.
`
`JUDGE GALLIGAN: Great.
`
`JUDGE HOWARD: And this is Judge Howard, can you hear me?
`
`JUDGE JEFFERSON: Yes; yes, we can. You can proceed, Judge
`Galligan -- or, Judge Howard, I'm sorry.
`
`JUDGE GALLIGAN: Great. Thank you. Good afternoon, I'm
`Administrative Patent Judge Galligan; and I'm joining from the Texas
`Regional Office as I said. Before you is Judge Jefferson; and on video is
`Judge Howard. This an IPR, an Inter Partes Review in IPR 2018-1249; U.S.
`Patent 7,693,002. Petitioner is Apple, and Qualcomm is the Patent Owner;
`and we issued an oral hearing in this case allocating 45 minutes of argument
`to each party; and now I'd like to ask Counsel for each side to come forth
`and make appearances at the podium and please make sure the green light is
`on, on the microphone. Petitioner, please, first.
`
`MR. RENNER: Good afternoon, Your Honors. This is Karl Renner
`from Fish & Richardson; and I'm joined by several colleagues -- Tim Riffe,
`Ken Hoover, and Whitney Reichel on behalf of Apple.
`
`JUDGE GALLIGAN: Great. And while I have you up there, how
`much rebuttal time would you like to reserve of your 45 minutes?
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`3
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`MR. RENNER: Thank you, Your Honor; we'll reserve 15 minutes.
`
`JUDGE GALLIGAN: Okay; thank you.
`
`MR. RENNER: Also we have printed demonstratives. May we
`
`approach Judge Jefferson with them?
`
`JUDGE GALLIGAN: Yes.
`
`MR. RENNER: Thank you.
`
`JUDGE GALLIGAN: Patent Owner?
`
`MR. COCHRAN: Good afternoon. Dave Cochran from Jones Day
`on behalf of the Patent Owner, Qualcomm. With me today is an associate
`from Jones Day, Josh Nightingale. We also have our trial technician, Alan
`Eaton; and with us in the audience we have Ron Zhang, Ken Vu, Steve
`Worth, and Yi Tang who are representatives of Qualcomm.
`
`JUDGE GALLIGAN: Thank you. And would you like to reserve
`sur-rebuttal time?
`
`MR. COCHRAN: Yeah; I'd like to reserve 10 minutes; and we also
`have a set of demonstratives for Judge Jefferson if you'd like to receive
`those.
`
`JUDGE JEFFERSON: Thank you.
`
`JUDGE GALLIGAN: Thank you, Counsel. Petitioner, you may
`proceed first; after that Patent Owner may respond. Petitioner, you'll get
`your 15 minutes of rebuttal time if you have that much left; and then Patent
`Owner, you are entitled to your sur-rebuttal time. Because Judge Howard
`and I are remote, please identify with particularity and for the purpose of the
`record, the transcript, anything you cite -- for instance, the demonstratives
`and the briefing. We have access to everything. Just please state the slide
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`4
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`number, or the page of the petition, or whatever you're looking at. And with
`that, Petitioner, you may begin.
`
`MR. HOOVER: Good afternoon, Your Honors. My name is Ken
`Hoover; along with my colleagues Tim Riffe, Karl Renner, and Whitney
`Reichel. We represent Petitioner, Apple.
`
`Slide 2 -- Your Honors, during our presentation today, we plan to
`focus our time on several distinct issues that have arisen during the briefings
`in this IPR rather than repeating an element-by-element analysis of the
`petition. I will be providing an overview of the '002 Patent itself, and
`addressing issues 1 and 3; my colleague, Tim Riffe, will address issue 2.
`
`Slide 3 - First, I'd like to provide a very brief overview of the '002
`Patent. On slide 4, the focus of the '002 Patent is on a wordline driver
`system for memory arrays; and in particular, figure 1 of the '002 Patent
`provides the most high level illustration of the patent's content. The '002
`Patent, itself, describes figure 1 as a block diagram of a particular illustrative
`embodiment of a wordline driver system, including a plurality of groups of
`wordline drivers associated with the memory array.
`
`On slide 5, we see that Qualcomm's expert, Dr. Pedram explained
`during his deposition that figure 1 is a functional block diagram and as such
`a POSITA wouldn't understand such drawings to provide the artisan with a
`functional illustration of a system; and is not intended to illustrate the
`specific circuit implementation of that system.
`
`Slide 6 - So we intend to begin with issue 1, with the Asano/Itoh
`ground. We're beginning with what is the second ground from our petition
`because it's the most straightforward one of the two grounds presented and
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`5
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`it's not dependent on the claim construction issue. Furthermore, this ground
`addresses all but three of the challenged claims in the IPR.
`
`Slide 7 - Slide 7 provides the text to claim 1 of the '002 Patent. Claim
`1 of the '002 Patent is directed to a circuit device comprising separate first
`and second logic. Among other things, the first logic decodes the first
`portion of the memory and the second -- MAC memory address, excuse me -
`- and the second logic decodes the second portion of the memory address.
`
`Notably, however, Patent Owner does not argue that Asano and Itoh
`do not teach the elements of the claims, instead they're arguing it boils down
`to the idea that a POSITA would not be motivated to build a decoder using
`textbook circuits.
`
`Slide 8 - Shows figure 2 from Asano. Similar to the '002 Patent,
`Asano discloses a wordline driver/address decoder system for a computer
`memory. Also similar to figure 1 of the '002 Patent, Asano represents its
`system as a functional block diagram. As we have seen, Dr. Pedram noted
`that the POSITA would understand such a diagram to be intended to show
`the function of system, not necessarily a circuit layout.
`
`The point of dispute for this ground is about the overlapping green
`and yellow lines on Asano's predecoder, 202, in this annotated figure.
`However, as we'll demonstrate, within the predecoder both experts agree that
`there is separate and distinct logic circuitry to produce separate and distinct
`predecoder outputs.
`
`In slide 9 -- And when you take a close look at Asano's figure, there's
`a single address coming in to the predecoder; but the reference teaches that
`this six-bit address is used to produce three separate and distinct outputs.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`6
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`The circled outputs on the annotated diagram in the second logic, the x or
`line select signal and the y or line select signal, and then separately the
`wordline enable signals as part of the first logic.
`
`In the interest of time, we're going to move to slide 12. In slide 12,
`Dr. Horst analyzes -- actually, slide 12 provides a summary of Dr. Horst's
`analysis of the text of Asano and his conclusion that of those six address
`input bits, three of those bits are decoded to create the eight-bit x wordline
`select signal; two of those bits are used to create the four-bit wordline select
`signal; and one address bit is decoded to produce the two-bit wordline
`enable signal -- that's per Asano.
`
`So, the question becomes -- and I would like to mention that the slides
`I skipped over provide a summary of Dr. Horst's analysis. So, the question
`then at issue becomes how would a POSITA have implemented the structure
`of the predecoder in Asano in order to produce these results. The evidence
`shows that the experts agree that in implementing Asano's predecoder, the
`POSITA would require separate logic circuits to decode each of these
`separate output signals.
`
`In slide 13 -- One reason we know that's the case is that's precisely
`how Dr. Pedram, Qualcomm's expert, said that he would teach his students
`to produce a similar set of outputs based on a similar grouping of bits.
`Specifically, when asked, are you saying you would use one set of AND
`gates to decode one bit; another set to decode two bits; and another to
`decode three bits, Dr. Pedram agreed. He did, however, note that -- on slide
`13 -- instead of using an AND gate to decode one bit -- he wouldn't use an
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`7
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`AND gate to decode one bit, but he would use -- that would be decoded
`differently -- but he would use separate AND gates for the other sets of bits.
`
`And then when we turn to slide 14, that's, precisely, what we see in
`Asano's textbook. We see a figure that shows -- in the subfigure a -- one
`input bit coming in to decode and produce two output bits. In subfigure b,
`we see two address input bits coming in to decode four output bits; and in
`subfigure c, we see three input address bits coming in to decode and produce
`eight output bits. Hence, the artisan's motivation for looking to this textbook
`is simply his or her desire to build Asano's predecoder circuit using standard
`logic circuits. And what would this implementation look like? In slide 15,
`Dr. Horst provided an annotated diagram where what we see here is in
`green, we see separate first logic circuitry decoding one bit to produce the
`wordline enable signals, and separate yellow, second logic circuitry to
`decode the remaining five bits and produce the x, y select output signals.
`
`Slide 16 - While the Patent Owner has characterized this motivation
`for this ground as impermissible hindsight, as the petition explained and Dr.
`Horst supported, the person of ordinary skill would have been motivated to
`use Itoh's textbook logic circuits to build Asano's predecoder, which was
`represented just by a functional element in a functional block diagram.
`There's really nothing more here at issue than the use of old elements,
`according to their known and intended function, to produce a predictable
`result. Your Honors have any questions?
`
`JUDGE GALLIGAN: Nothing from me; thank you.
`
`MR. HOOVER: Then, I'll introduce Tim to discuss the claim
`construction.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`8
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`MR. RIFFE: Good afternoon, Your Honors -- Tim Riffe on behalf of
`
`Apple, again. I'll be speaking with you for the next few minutes regarding
`Patent Owner's construction of a clock signal and why that's improper. In
`order to overcome the prior art of records -- some of which that you just
`heard from Mr. Hoover on which is part of the record -- Qualcomm
`proposes, effectively, to add a limitation to the claims being a narrowing
`claim construction that we believe is improper.
`
`Specifically, Qualcomm proposed adding a limitation to establish an
`undisclosed characteristic of an inferentially claimed signal -- an input signal
`to the '002 memory encoder circuit. There's no intrinsic evidence that
`supports this narrowing construction. Instead the intrinsic evidence
`confirms that the term is agnostic to either type of system. Prior art in the
`same field will confirm this -- as we've shown in the record, and which I'll
`go through with you briefly this afternoon. Qualcomm's only supporting
`evidence is a single generic dictionary that's not of specific to this field and
`an expert that didn't do the correct analysis.
`
`Slide 18, please. Now the primary point of dispute, of course in
`ground 1 of the Sato reference is the term clock signal that appears twice in
`claim 1. In the context of claim 1 -- as I mentioned earlier -- this term is an
`electronic input signal to the '002 Patent's wordline driver and address
`decoder system. Nothing in claim 1 itself, or the written description,
`indicates that the specific characteristics of this signal are critical to or even
`change the function of the claimed circuit device. Indeed, as we can see
`reproduced on slide 18, the term clock signal is, at best, inferentially claimed
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`9
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`as I mentioned earlier; and simply is the input to the wordline driver, the
`address decoder.
`
`As the record shows, the only alleged intrinsic evidence that supports
`Patent Owner's narrow construction is the patent's use of the term clock
`signal itself; and to support Patent Owner's contention, you must find that in
`spite of the evidence to the contrary -- some of which we'll go over with you
`this afternoon -- intrinsically, the term clock signal, itself, requires it to be
`periodic because Patent Owner provides no additional support.
`
`Slide 19, please. Here we show the competing constructions. Now,
`Petitioner -- in our petition and as we stand here today -- believes that this
`should get its plain and ordinary meaning. However, because Qualcomm
`raised this as a claim construction issue we, of course, responded to that
`proposed construction.
`
`Now, the next slides I go over with Your Honors -- slides 20 and 21 --
`support the notion that clock signal must be interpreted broad enough to
`encompass certain types of clock signals -- and those are modified clock
`signals; and those are termed conditional clock signals in the art -- we'll see
`some examples of those, and there are examples of those in the '002 Patent --
`and gated clock signals. And these particular types of clock signals are
`actually claimed in the '002 Patent; and as the record shows Patent Owner's
`construction reads out these particular claim signals. So, let's take a look at
`some of the examples of why that is.
`
`Slide 20 -- In fact Patent Owner's own expert, Dr. Pedram, admitted
`during his deposition that the conditional clock signals, which are shown as
`124 through 130, in figure 1 of the '002 Patent, those are outputs of the '002
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`10
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`Patent's conditional clock generator, 110 -- as we see in figure 1. Dr.
`Pedram admitted during his deposition that those would not meet Patent
`Owner's construction of the term. But why is that? Because Dr. Pedram
`explicitly stated that the Patent Owner's claim construction requires "always
`running, continuously running" periodic signal being applied to the address
`decoder or what's claimed as the first logic.
`
`Dr. Pedram's acknowledgement about the scope of the Patent Owner's
`claim construction even reads dependent claims -- such as claims 5 and 7 --
`outside the scope of this construction because under Patent Owner's
`construction the conditional clock outputs of claim 5 would no longer
`conform to the scope the applied clock signal of claim 1 under Dr. Pedram's
`reading of the claims; hence, reading the narrowing dependent claim outside
`of the scope of the claims from which it depends.
`
`Now, in Patent Owner's sur-reply they tried to take us to task for this;
`and they make an argument that a person of skill in the art would understand
`that in the '002 Patent, all of the clock outputs are not carrying a clock signal
`at all times -- and the clock signals we're referring to again here are signals
`124 through 130 -- those are the conditional clock signals, if you will -- and,
`therefore, Patent Owner says that the fact that the Patent Owner's
`construction of clock signal does not encompass the fixed voltage levels of
`the non-selected clock outputs is consistent with the intrinsic evidence.
`That's simply not the case.
`
`As Qualcomm's own expert, Dr. Pedram testified, as shown on slide
`20 -- the expert that we have -- he testified that none of the signals -- 124,
`126, 128, and 130 -- meet Qualcomm's definition. So, despite the fact -- we
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`11
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`don't disagree with them that these clock signals that are output from the
`conditional clock generator -- there may be times where if one is output, the
`others have fixed voltage on the output -- that's okay; we agree with them on
`that. What Dr. Pedram says is when you have one of these conditionally
`generated clock signals, they will not meet the definition of Patent Owner's
`proposed construction because of that periodic signal.
`
`Slide 21 - The Petitioner's reply brief presented several of Dr.
`Pedram's own publications that refer to clock signals that can be stopped
`when not in use. In other words, non-periodic clock signals -- as gated
`clocks -- again, the term that we're using here in view of the '002 Patent's
`clock signals.
`
`The Patent Owner acknowledged in its sur-reply that these gated
`clocks are different from a clock signal; and Petitioner agrees. The gated
`clocks represent a subset of clock signals that are not always running; and as
`Dr. Pedram told us such gated clock signals do not meet Patent Owner's
`construction. So, here again, their construction of clock signals, unduly
`restrictive, even though its own expert referred to gated clock signals as
`clock signals in certain of his publications.
`
`The broader term clock signal should be construed to encompass the
`subsets. Why is that? Otherwise, as noted, the gated or conditional clock
`outputs, as claimed in the dependent claims, are read outside of the scope of
`the claims themselves, and that cannot stand. This is especially true where
`neither the claims themselves, nor the intrinsic record provides such
`limitations on the claim term.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`12
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`Now let's look at slide 22 because this is interesting. Qualcomm
`
`provided a definition from the IEEE Dictionary that indicates that the term
`timing signal used by Sato is synonymous with clock signal of the '002
`Patent. Indeed, let's talk about that. As we can see on the slide 22,
`Qualcomm's IEEE Dictionary, specifically, says that clock signal is
`synonymous with clock pulse and timing pulse. So, therefore, we have a
`relationship between clock signal, clock pulse, timing pulse. What is the
`rational deduction from that relationship. Is that clock signal synonymous
`with clock pulse; clock pulse is synonymous with timing pulse; and,
`therefore, clock signal is synonymous with timing signal -- drawing from
`deductive reasoning from their own definition.
`
`We've talked about how clock signals is not limited to the periodic
`signal by virtue of the intrinsic record now; Dr. Pedram's publications, and
`additional intrinsic evidence; now, we'd like to discuss how some non-
`periodic signals of the prior art are actually referred to as clock signals in
`those prior art references such that a person of skill in the art coming to look
`at the '002 Patent would understand that a clock signal is not limited to the
`restrictive periodic clock signal that Qualcomm would have you believe it is.
`
`Let's go look at slide 24. Slide 24, we're looking at the Hayakawa
`reference that we cited to in our Petitioner's briefs. The Hayakawa reference
`provides an example of a prior art reference that refers to a non-periodic
`signal as a clock signal. Specifically, Hayakawa states that its clock signal
`φs is generated in response to an address transition detect signal. Now,
`Petitioner's expert, Dr. Horst, explained in his second declaration that this
`means that Hayakawa's clock signal is triggered based on changes to an
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`13
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`address signal applied to Hayakawa's static RAM. Consequently, the
`generated clock signal follows the pattern of address changes, and would
`generally not be periodic.
`
`Slide 25 -- This is similar to what Dr. Pedram -- again, Qualcomm's
`expert -- said in his declaration with respect to Sato's timing signal because
`it too follows memory access patterns that he characterizes as "highly
`irregular." The point being here is that Dr. Pedram's own analysis supports
`Dr. Horst's opinion that Hayakawa's clock signal would, in fact, be non-
`periodic -- which is what Hayakawa refers to as the clock signal.
`
`Let's go to Slide 26. Now, looking at their supposed intrinsic
`evidence. Dr. Pedram acknowledged that the '002 Patent -- during his
`deposition -- does not contain a specific definition of clock signal. He was
`specifically asked on slide -- and we've reproduced this on slide 26 -- the
`question was, is there any place in the specification of the '002 Patent where
`you believe the inventors have set forth a particular definition of the term
`clock signal? Dr. Pedram responded to that by saying "I've not seen in the
`'002 Patent a precise definition of the clock." And there he was referring
`specifically to the question being asked about clock signal.
`
`Now, the record shows, as we've developed in our briefing, that the
`'002 Patent also does not contain any references to asynchronous vs.
`synchronous systems; any references to the period characteristics of the
`clock signal, e.g., it's frequency, it's period -- some of those other types of
`characteristics; and there's no disclosure of timing control circuitry for either
`synchronous or asynchronous systems, such as those of the Itoh reference --
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`14
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`which you'll hear about -- that Qualcomm points to as support for its
`construction.
`
`So, ultimately, a POSITA would have understood that the focus of the
`'002 Patent is not on a particular type of clock signal. That's an inferentially
`claimed input into what is claimed, which is the generic wordline driver
`system that's agnostic to the implementation in particular types of memory
`systems.
`
`Slide 27, please. So, Patent Owner's intrinsic -- alleged intrinsic
`evidence -- of the periodic clock signal is merely that the '002 Patent does
`not disclose an asynchronous memory system. Patent Owner's support of
`this notion is in paragraph 54 of Dr. Pedram's declaration which merely
`parrots the same statement. But, in fact, the '002 doesn't describe the
`synchronous system either. To be fair, the Patent Owner's response cites to
`several other paragraphs -- and, specifically, 54 through 69 of Dr. Pedram's
`declaration. But if you look at those paragraphs -- and I would ask the
`Board to please do so before the final written decision -- you will note that
`the '002 Patent is not once cited in those paragraphs of Dr. Pedram's
`analysis. So, in essence, the Patent Owner's only intrinsic evidence for
`interpreting clock signal, as narrowly as they would have you do it, is the
`term itself and nothing more. Any questions, Your Honor?
`
`JUDGE JEFFERSON: I don't have any; thanks.
`
`MR. RIFFE: Thank you. I'll turn it back over to Mr. Hoover.
`
`MR. HOOVER: Thank you, Tim. We're on slide 31, and our last
`issue is whether Sato renders obvious the '002 Patent claims. Initially, I
`would like to note that the Board adopts Apple's claim construction, there is
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`15
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`actually no dispute that Sato invalidates the claims of the '002 Patent. What
`I would like to address in the next few minutes, however, is -- time
`permitting -- is first that the Patent Owner's erroneous and irrelevant
`argument that Sato is somehow fundamentally different from the '002
`Patent; but, in fact, they are nearly identical in function and structure. Then
`after that -- time permitting -- I'll discuss how the evidence shows that Sato
`renders the claims obvious even under Patent Owner's narrow construction
`of a mere input signal to the '002 Patent -- the '002 Patent wordline drivers.
`And, finally -- time permitting -- I'll address a few arguments that the Patent
`Owner had about the clock outputs in Sato's predecoder.
`
`Slide 32, claim 1 -- So, just to be clear, there are no specific transistor
`configurations required by the claims; but just to give you a sense for how
`flawed Patent Owner's argument that Sato is somehow fundamentally
`different than the '002 Patent, I'll briefly describe for you how even the
`specific embodiments of both patents operate nearly identically and have
`similar structure. I'll also describe for you how the evidence shows that even
`the disputed clock signal or timing signal serve a similar function in the
`particular embodiments of each system and, consequently, that the Patent
`Owner's attempt to introduce undisclosed characteristics of a clock signal
`into the claim is a last ditch effort to save the patent.
`
`Slide 33 -- By way of reintroducing the Board to Sato, slide 33
`provides a color-coded comparison from the petition between the particular
`embodiments of Sato's figure 3 and the '002 Patent's figure 1. And again,
`the claims do not recite the wordline driver system -- the '002 Patent
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`16
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`wordline driver system -- at this level of particularity. This is an exemplary
`-- this is for example, to show just how similar the two are.
`
`On slide 34, shows a closer comparison of the first logic of each
`embodiment of the respective systems. Here we can see that in green, the
`first logic of each system receives a portion of a memory address, in purple.
`It receives a synchronization signal -- timing signal or a clock signal,
`respectively -- in blue; and it provides four red output signals based on those
`input signals. The output signals are each connected to particular wordline
`driver circuitry in each system, in yellow.
`
`Slide 35 - Illustrates claim 1 with the same color-coded mapping of
`the individual elements from those particular embodiments of each to the
`language of the claims. This is provided for the Board's reference.
`
`Slide 36 -- This slide illustrates -- I'm not going to go through this
`chart in detail; that would be very tedious -- but this provides Dr. Horst's
`chart explaining his detailed transistor-by-transistor analysis of the two
`patents -- the embodiments of the two patents -- to show the near identical
`operations of their respective embodiments and their near-identical usage of
`the clock/timing signals. The chart's reproduced for your convenience.
`
`But in the next three slides what I do plan to do is summarize Dr.
`Horst's analysis graphically. Again, showing that even the particular
`embodiments in each patent apply the synchronization -- respectively,
`clock/timing signals -- identically at the transistor level or line activation
`circuitry; and, hence, Patent Owner's characterization of Sato as
`fundamentally different is just wrong.
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`17
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`Slide 37 -- This slide shows at steady state -- prior to wordline
`
`activation -- shows the signals that are applied to the wordline driver
`transistors in each system prior to the wordline activation.
`
`In slide 38, the clock signals are activated. The clock output's in red
`of the first logic; and the second logic selection signal, in orange, are applied
`to identical transistors, indicated in purple and blue, in an identical manner.
`These are even the same types of transistors.
`
`On slide 39, the wordline is activated. Both Sato's and the '002
`Patent's wordline drivers, in yellow, are activated by the orange selection
`signal from the second logic, as the red clock output is used to operate the
`identical transistors indicated in slide 38.
`
`In slide 40, we have provided a summary for your reference that
`shows the complete mapping between the embodiments of each of the two
`systems; and this image is also provided, annotated, in our petition.
`
`Slide 41 -- Slide 41 now takes the claim -- and we highlight the
`operations that we just described. Again in red, is highlighted the claim
`language that relates to the application of the red clock outputs; and in
`orange, it's highlighted the operations that pertain to the orange second logic
`system as they're applied to the wordline circuitry.
`
`Again, the claims don't require this transistor-to-transistor level of
`detail that we just walked through, but from that discussion, it's clear that
`Sato functions fundamentally the same as the '002 Patent. Thus, these more
`general claim languages -- a lot more general claim language is met. Are
`there any questions on that analysis?
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`
`
`18
`
`
`
`Case IPR2018-01249
`Patent 7,693,002 B2
`
`
`
`On slide 42 -- Next we show Your Honors -- even if Your Honor is
`
`determined that Apple is wrong on the claim construction; and that the term
`clock signal, as used in the '002 Patent, requires continuous, unceasing
`periodic clock signals, as Dr. Pedram's described, Sato expressly teaches that
`his wordline driver -- the x-address decoder -- can be applied in clocked
`static address decoders. Although disputed by the Patent Owner as mere
`opinion of Sato's invention, this disclosure by Sato falls squarely within the
`teaching-suggestion-motivation test for obviousness. The reference, itself,
`suggest an obvious motivation to its disclosed invention.
`
`Indeed, if simply the use of the term clock signal in the '002 Patent is
`sufficient to prove it's limited to synchronous systems and, therefore,
`periodic -- as Tim explained -- surely, Sato's reference to a clock, clocked
`address decoder, provide similar evidence to support its suggested use in
`synchronous systems with a periodic clock input to its address decoder.
`
`And on slide 43, the experts agree that if the person of ordinary skill
`at the time would have had the knowledge and ability to build a clock
`generator, for either the Sato or the '002 Patent -- Dr. Pedram testified as to
`the undisclosed clock generation circuitry in the '002 Patent -- that yes, a
`person of ordinary skill would have been able to use known components and
`build one.
`
`And in the interest of time -- so, in slide 45 -- basically, the Patent
`Owner -- and I would like to touch really briefly -- the Patent Owner has
`suggested that Sato's predecoder doesn't directly apply that same timing
`signal to its outputs and the input; and that somehow that means that Sato
`fails to disclose the outputs, the claimed clock outputs. However, Dr. Horst
`
`1
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`
`
`
`19
`
`
`
`Case IPR2018-01249
`P
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
