`v.
`Qualcomm Incorporated
`IPR2018-01249
`U.S. Patent No. 7,693,002
`
`Patent Owner’s Demonstrative Exhibits
`
`
`
`U.S. Patent No. 7,693,002
`
`U.S. Patent No. 7,693,002
`
`
`
`
`104
`
`132 {- 102
`‘\
`
`
`
`
`K126 :
`:
`I
`I
`C128
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`130
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`I
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`I
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`106
`'
`
`_
`_
`Group of
`Wordline
`.
`Driver
`
`
`
`'
`
`Partially Decoded
`Address (15)
`122
`
`
`
`
`
`
`114
`
`Address<512>
`
`
`Condltlonm clock
`"Clk<3:0="
`generator
`
`
`
`Address<1 :0>
`
`2
`
`Clock
`
`MEMORY
`ARRAY
`
`
`
`Ex. 1001 at Fig. 1
`
`US 7.693.002 B2
`(10) Patent No.:
`(12) United States Patent
`Apr. 6, 2010
`(45) Date of Patent:
`Lin
` DYNAMIC WORD LINE DRIVERS AND
`
`(54)
`
`DECODERS FOR MEMORY ARRAYS
`
`100\
`(75‘)
`Inventor:
`Jemsung Lin, Cardiffby the Sea. CA
`
`
`(US)
`
`
`2004/02
`
`[73) Asslgnee: QUALCOMM lm'urporntcd. San
`200 5/00
`
`
`Diego. CA (US)
`
`
`
`120
`
`\
`
`Partially Decoded
`Addressw)
`u
`
`
`Group of
`
`
`
`
`
`Wordline Mi—
`_LWL‘2
`Driver
`
`WL<3>
`WL 03
`
`4
`b)
`I
`
`(
`124
`
`
`
`u
`
`
`
`
`
`U.S. Patent No. 7,693,002
`
`U.S. Patent No. 7,693,002
`
`HW'HEE [ID]
`
`122
`
`Cauilional clock
`
`’Clk<3:0:r“
`
`gene-mm
`
`Clock
`
`Address<52>
`
`Addfas5<1fl>
`
`3
`
`Paper 11 at 9
`
`
`
`‘002 Patent – Claim 1
`
`‘002 Patent — Claim 1
`
`1. A circuit device comprising:
`first logic to receive a clock signal and a first portion of a
`memory address of a memory array, the first logic to
`decode the first portion of the memory address and to
`apply the clock signal to a selected clock output of a
`plurality of clock outputs associated with a selected
`group of a plurality of wordline drivers that are associ-
`ated with the memory array; and
`second logic to decode a second portion of the memory
`address, the second logic to selectively activate a par-
`Ex. 1001 at 10:65-11:10
`ticular wordline driver of the selected group of wordline
`drivers according to the second portion of the memory
`
`address.
`
`4
`
`EX. 1001 at 10:65-11:10
`
`
`
`Contested Grounds
`
`Ground
`
`Claims
`
`Grounds for Review
`
`1
`
`2
`
`1-28 and 31-37 Obvious over Sato
`
`1-17, 20-28, 31-
`36
`
`Obvious over Asano and Itoh
`
`Paper 2 at 2
`
`5
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`6
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`7
`
`
`
`Sato § 103: The Petition Fails to Establish a
`Prima FacieCase of Obviousness
`
`8
`
`Paper 2 at 9
`
`
`
`Sato § 103: The Petition Fails to Establish a
`Prima FacieCase of Obviousness
`
`Paper 11 at 28
`
`9
`
`
`
`Sato § 103: The Petition Fails to Establish a
`Prima FacieCase of Obviousness
`Deposition of Petitioner’s declarant:
`
`Ex. 2005 at 47:8-10
`
`10
`
`
`
`Sato § 103: The Petition Fails to Establish a
`Prima FacieCase of Obviousness
`
`The Petition:
`
`Paper 2 at 10
`
`Paper 2 at 17
`
`Paper 2 at 19
`
`11
`
`
`
`Sato § 103: The Petition Fails to Establish a
`Prima FacieCase of Obviousness
`
`The Petition:
`
`Paper 2 at 14-15
`
`Paper 2 at 16
`
`Paper 2 at 17
`
`12
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`13
`
`
`
`Claim Construction – “Clock Signal”
`Qualcomm’s proposed construction:
`
`Petitioner’s proposed construction:
`
`Paper 11 (Qualcomm’s Response) at 11
`
`14
`
`Paper 15 (Petitioner Reply) at 1
`
`
`
`Claim Construction – “Clock Signal”
`The ‘002 patent:
`
`Ex. 1001 at 1:11-16
`
`15
`
`
`
`Claim Construction – “Clock Signal”
`
`The ‘002 patent:
`
`16
`
`Ex. 1001 at 1:64-2:12
`
`
`
`Claim Construction – “Clock Signal”
`The IEEE Dictionary:
`
`Ex. 2002 at 9
`
`17
`
`
`
`Claim Construction – “Clock Signal”
`Asynchronous memory systems:
`
`Ex. 2001 (Pedram Decl.) at ¶56
`
`Itoh Fig. 6.14 – “The asynchronous operation
`of a DRAM chip.” (Ex. 2003 at 18.)
`
`18
`
`
`
`Claim Construction – “Clock Signal”
`Synchronous memory systems:
`
`Ex. 2001 (Pedram Decl.) at ¶¶61-62
`
`Itoh Fig. 6.15 – “The synchronous operation
`of a DRAM chip.” (Ex. 2003 at 19.)
`
`19
`
`
`
`Claim Construction – “Clock Signal”
`Dr. Massoud Pedram:
`
`Ex. 2001 (Pedram Decl.) at ¶65
`
`20
`
`
`
`Blank Slide
`
`Blank Slide
`
`21
`
`
`
`Claim Construction – “Clock Signal”
`Petitioner’s dictionary definitions for the term “clock”:
`
`IEEE Dictionary
`Seven (7) entries for the term
`“clock”
`
`Ex. 1014 at 4
`
`Modern Dictionary of Electronics
`Five (5) entries for the term
`“clock”
`
`Ex. 1015 at 3-4
`
`22
`
`
`
`Claim Construction – “Clock Signal”
`Petitioner’s dictionaries:
`
`IEEE Dictionary
`
`Ex. 2002 at 9
`
`Ex. 1014 at 4
`
`Modern Dictionary of Electronics
`
`Ex. 1015 at 3-4
`
`Ex. 1015 at 4
`
`23
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`The ‘002 patent claims:
`
`24
`
`Ex. 1001 at 10:65-11:10
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`
`Sato:
`
`Ex. 1005 at Fig. 4
`
`25
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`
`The Petition:
`
`Paper 2 at 10
`
`26
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`
`Sato:
`
`Ex. 1005 at 3:59-65
`
`27
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`
`Dr. Massoud Pedram:
`
`28
`
`Ex. 2001 at ¶¶97-98
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`Dr. Massoud Pedram:
`
`Ex. 2001 at ¶102
`
`29
`
`Ex. 1005 at Fig. 4
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`Deposition of Petitioner’s declarant:
`
`Ex. 2006 at 87:24-88:5
`
`30
`
`Ex. 1005 at Fig. 3
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Signal”
`
`Sato:
`
`Ex. 1005 at 9:68-10:4
`
`31
`
`Ex. 1005 at Fig. 3
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`32
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`The ‘002 patent claims:
`
`33
`
`Ex. 1001 at 10:65-11:10
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`
`The Petition:
`
`Paper 2 at 19
`
`34
`
`Paper 2 at 20
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`
`Sato’s “timing signal” or “selection control signal” 𝜙ce:
`
`Ex. 1005 at 3:59-61
`
`Ex. 1005 at 4:27-31
`
`Ex. 1005 at 5:48-50
`
`35
`
`Ex. 1005 at 7:1-3
`
`
`
`Sato’s “selection signals” 𝜙x0, 𝜙x1, 𝜙x2, and 𝜙x3:
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`
`Ex. 1005 at 1:48-54
`
`Ex. 1005 at 5:25-42
`
`36
`
`Ex. 1005 at 6:45-56
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`Dr. Massoud Pedram:
`
`Ex. 2001 at ¶76
`
`37
`
`
`
`Sato § 103: Sato Does Not Teach or Suggest
`the Claimed “Clock Output”
`
`Sato:
`
`Ex. 1005 at Fig. 1
`
`Ex. 1005 at 5:25-42
`
`38
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`39
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`40
`
`Paper 11 at 9
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`Deposition of Petitioner’s declarant:
`
`Ex. 2005 at 16:10-14
`
`41
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Asano:
`
`42
`
`Ex. 1006 at Fig. 2
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Petition:
`
`43
`
`Paper 2 at 34
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Dr. Massoud
`Pedram:
`
`44
`
`Ex. 2001 at ¶127
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Asano:
`
`45
`
`Ex. 1006 at Fig. 2
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Asano:
`
`46
`
`Ex. 1006 at Fig. 3
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`
`Petition:
`
`Paper 2 at 35
`
`47
`
`
`
`Asano and Itoh: Petitioner’s Combination is
`Based on Impermissible Hindsight
`Deposition of Dr. Massoud Pedram:
`
`Ex. 1019 at 21:18-21
`
`48
`
`
`
`Patentability
`
`I.
`•
`•
`•
`
`SATO DOES NOT RENDER CLAIMS 1-28 AND 31-37 OBVIOUS
`The Petition Fails to Establish a Prima Facie Case of Obviousness
`Sato Does Not Teach or Suggest the Claimed “Clock Signal”
`Sato Does Not Teach or Suggest the Claimed “Clock Output”
`
`II. ASANO AND ITOH DO NOT RENDER CLAIMS 1-17, 20-28, AND 31-
`36 OBVIOUS
`Petitioner’s Combination is Based on Impermissible Hindsight
`The Petition’s Motivation to Combine Argument is Flawed
`
`•
`•
`
`49
`
`
`
`Asano and Itoh: The Petition’s Motivation to
`Combine Argument is Flawed
`
`Petition:
`
`Paper 2 at 35
`
`50
`
`Paper 2 at 38
`
`
`
`Asano and Itoh: The Petition’s Motivation to
`Combine Argument is Flawed
`
`Petition:
`
`Paper 2 at 35
`
`Ex. 2005 at 52:14-18
`
`Deposition of Petitioner’s declarant:
`
`51
`
`
`
`Asano and Itoh: The Petition’s Motivation to
`Combine Argument is Flawed
`
`52
`
`Paper 11 at 54-55
`
`
`
`Asano and Itoh: The Petition’s Motivation to
`Combine Argument is Flawed
`
`Petition:
`
`Paper 2 at 37
`
`Paper 2 at 42
`
`“The issue is not whether a skilled artisan could [combine the references] or
`whether it would have been trivial to do so. The issue is whether a skilled
`artisan would have been motivated to do so based on teachings of the
`references ....” TRW Automotive US LLC v. Magna Elecs., Inc., IPR2014-
`01355, Paper 21 at 15 (PTAB Nov. 19, 2015) (emphasis added).
`53
`
`
`
`Asano and Itoh: The Petition’s Motivation to
`Combine Argument is Flawed
`
`Petition:
`
`Why?
`
`Why?
`
`Why?
`
`Why?
`
`Paper 17 at 23-25 (quoting Paper 2 at 35)
`
`54
`
`
`
`Case No. IPR2018-01249
`Patent No. 7,693,002
`
`
`
`CERTIFICATE OF SERVICE
`
`
`The undersigned hereby certifies that a copy of the foregoing Patent
`
`Owner’s Demonstrative Exhibits was served on October 7, 2019 by email, as
`
`follows:
`
`W. Karl Renner
`IPR39521-0054IP1@fr.com
`axf-ptab@fr.com
`
`Thomas A. Rozylowicz
`PTABInbound@fr.com
`rozylowicz@fr.com
`tar@fr.com
`
`Timothy W. Riffe
`PTABInbound@fr.com
`riffe@fr.com
`
`Kenneth J. Hoover
`hoover@fr.com
`
`Whitney A. Reichel
`wreichel@fr.com
`
`Date: October 7, 2019
`
`/ Joshua R. Nightingale /
`Joshua R. Nightingale, Reg. No. 67,865
`JONES DAY
`500 Grant Street, Suite 4500
`Pittsburgh, PA 15219
`
`Counsel for Patent Owner
`
`
`
`
`