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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`Apple, Inc.,
`Petitioner,
`v.
`
`Qualcomm Incorporated,
`Patent Owner
`____________________
`Case IPR2018-01249
`U.S. Patent No. 7,693,002
`_____________________
`
`PATENT OWNER SUR-REPLY
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`

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`IPR2018-01249
`U.S. Patent 7,693,002
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`C. 
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`D. 
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`Table of Contents
`Introduction ..................................................................................................... 1 
`Claim Construction – “Clock Signal” ............................................................ 1 
`A. 
`Petitioner’s Criticism Of Dr. Pedram’s Testimony Is Misplaced ........ 1 
`B. 
`Qualcomm’s Construction Is Not Inconsistent With The
`Conditional Clock Outputs Of The ’002 Patent ................................... 2 
`The Reply Does Not Rebut Qualcomm’s Showing That Its
`Construction Is Supported By The Intrinsic Evidence ......................... 3 
`Extrinsic Evidence Shows That Petitioner’s Construction Of
`“Clock Signal” Is Overly Broad ........................................................... 5 
`Itoh Does Not Show That The Claimed “Clock Signal”
`Encompasses Non-Periodic Signals ..................................................... 7 
`Petitioner’s New References Do Not Support Its Construction ........... 9 
`F. 
`G.  Dr. Alpert’s Previous Testimony On The Meaning Of “Clock”
`Is Relevant To The Construction Of “Clock Signal” ......................... 10 
`Petitioner’s Proposed Construction Is Wrong For The Reasons
`Stated In Qualcomm’s Patent Owner Response ................................ 11 
`Sato Does Not Render Obvious Claims 1-28 And 31-37 (Ground 1) .......... 11 
`A. 
`The Petition Failed To Address All Of The Graham Factors ............ 11 
`B. 
`Sato Does Not Disclose The Claimed “Clock Signal” Because
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`E. 
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`H. 
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`Its Selection Control Signal (cid:2038)ce Is Not Periodic ............................... 12 
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`C. 
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`D. 
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`Sato Does Not Render Obvious The Periodic “Clock Signal”
`Required By The Claims .................................................................... 16 
`Sato Does Not Meet The “Clock Signal” Limitation Even
`Under Petitioner’s Proposed Construction ......................................... 19 
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`-ii-
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`

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`Even If Sato’s Selection Control Signal (cid:2038)ce Is Considered A
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`IPR2018-01249
`U.S. Patent 7,693,002
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`Clock Signal, The Reference Still Fails To Disclose The
`Claimed “Clock Outputs” ................................................................... 20 
`  Asano And Itoh Do Not Render Obvious Claims 1-17, 20-28, And 31-
`36 (Ground 2) ............................................................................................... 21 
`A. 
`Petitioner’s Proposed Combination Is Based On Impermissible
`Hindsight ............................................................................................ 21 
`The Petition’s Motivation To Combine Argument Is Inadequate ..... 23 
`B. 
`Conclusion .................................................................................................... 26 
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`E. 
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`-iii-
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`IPR2018-01249
`U.S. Patent 7,693,002
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`
`
`Introduction
`Petitioner’s reply introduces unpersuasive and belated arguments and
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`evidence that cannot salvage the petition. Sato does not meet the “clock signal”
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`limitation of the claims, as properly construed, and Petitioner failed to present an
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`adequate motivation to combine Asano and Itoh. The Board should confirm the
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`patentability of claims 1-28 and 31-37.
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` Claim Construction – “Clock Signal”
`A.
`Petitioner’s Criticism Of Dr. Pedram’s Testimony Is Misplaced
`In his expert declaration supporting Qualcomm’s response, Dr. Pedram
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`
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`provided extensive testimony showing that the term “clock signal” should be
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`interpreted as “a periodic signal used for synchronization.” Ex. 2001 at 53-70. The
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`reply argues that “Dr. Pedram’s opinion on the BRI of the term ‘clock signal’ …
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`should be accorded little weight” because he has not provided testimony on the full
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`scope of the claims. Paper 15 at 2-3.
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`
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`Petitioner’s criticism is misplaced. The reply cites no legal authority for the
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`proposition that an expert must consider and testify as to the full scope of claims in
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`order to opine on the meaning of certain claim terms. In preparing his expert
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`declaration, Dr. Pedram considered and testified as to a number of discrete issues:
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`(i) the meaning of the term “clock signal,” and (ii) whether Petitioner’s
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`unpatentability grounds render obvious the challenged claims. See generally
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`1
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`IPR2018-01249
`U.S. Patent 7,693,002
`Ex. 2001. None of these issues required consideration of the “exact scope of the
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`claims.”1
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`B. Qualcomm’s Construction Is Not Inconsistent With The
`Conditional Clock Outputs Of The ’002 Patent
`The reply argues that because the challenged claims require a first logic and/or
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`conditional clock generator that applies a clock signal to a selected one of multiple
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`clock outputs, Qualcomm’s “interpretation of the term ‘clock signal’ is too narrow
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`to even encompass the clock signals carried by ‘clock outputs’ of the ’002 patent
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`claims.” Paper 15 at 3-4.
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`Petitioner’s argument is based on the unfounded assumption that in
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`the ’002 patent, all of the clock outputs of the conditional clock generator
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`are always carrying a clock signal. But they are not. In fact, the specification
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`repeatedly makes clear that “[t]he conditional clock generator 110 receives a clock
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`signal via the clock input 118 and selectively applies the clock signal to a selected
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`one of the clock outputs 124, 126, 128 and 130” (Ex. 1001 at 3:28-31), and that
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`1 The reply also criticizes Dr. Pedram as lacking understanding of the law of
`obviousness, citing a statement in his declaration that is allegedly contrary to the
`Supreme Court’s decision in KSR. Paper 15 at 27-28. Qualcomm disputes this
`criticism. As Dr. Pedram made clear at deposition, his understanding of obviousness
`is not limited to the legal standards recited in his declaration. See Ex. 1019 at 36:6-
`15. Thus, even assuming that the declaration contains a misstatement regarding the
`law of obviousness, this does not show that Dr. Pedram lacks a sufficient
`understanding of the law.
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`2
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`IPR2018-01249
`U.S. Patent 7,693,002
`“[s]ince only one of the four clock outputs 124, 126, 128 and 130 may be active at a
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`time,” the non-selected clock outputs are held at a fixed voltage level (id. at 3:52-
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`62). Dr. Horst confirmed this at deposition. Ex. 2006 at 94:23-24, 98:23-25. Thus,
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`in the ’002 patent, the selected clock output carries the clock signal, but the fixed
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`voltage level on the non-selected clock outputs is not a clock signal.
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`The POSA would thus understand that in the ’002 patent, all of the clock
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`outputs are not carrying a clock signal at all times. Accordingly, the fact that
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`Qualcomm’s construction of “clock signal” does not encompass the fixed voltage
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`levels of the non-selected clock outputs is consistent with the intrinsic evidence.
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`C. The Reply Does Not Rebut Qualcomm’s Showing That Its
`Construction Is Supported By The Intrinsic Evidence
`The response showed that the intrinsic evidence supports Qualcomm’s
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`proposed construction of “clock signal.” Paper 11 at 11-15. In fact, the invention
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`of the ’002 patent is specifically intended to address problems that arise from the use
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`of a periodic clock signal. Such a clock signal periodically switches between logic-
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`level high and low states, thus resulting in high power consumption, and because the
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`periodic clock signal is distributed to many different components of the memory
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`system to synchronize them, a heavy load is placed on the clock signal. See Ex. 1001
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`at 1:11-25. The invention of the ’002 patent is intended to address the problems of
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`3
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`IPR2018-01249
`U.S. Patent 7,693,002
`power consumption and loading that result from the use of a periodic, synchronizing
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`clock signal. See id.
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`The reply does not rebut any of Qualcomm’s showings. Paper 15 at 5-6.
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`Instead, Petitioner argues that the ’002 patent does not include explicit description
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`of certain aspects of computer memory systems, and that therefore, no conclusion
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`can be drawn from the patent’s complete lack of any suggestion of an asynchronous
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`system. Id. Petitioner’s argument misses the point. Patents need not disclose what
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`is well known in the art. Lindemann Maschinenfabrik GMBH v. Am. Hoist and
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`Derrick Co., 730 F.2d 1452, 1463 (Fed. Cir. 1984). Thus, the ’002 patent’s alleged
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`lack of description of conventional components like “clock drivers” and “column
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`address decoders” (Paper 15 at 5-6) is of no consequence.
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`But Petitioner’s assertion that the claims should read on asynchronous
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`memory systems when none are described in the patent, and the patent consistently
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`describes features and functionality found only in synchronous systems, is not
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`credible. If the inventors intended the claims to read on asynchronous memory
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`systems that lacked a periodic clock signal—even though a primary motivation of
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`the invention is to reduce the heavy load and large power consumption of the clock
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`signal of a synchronous system—the specification would include some description
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`or suggestion of asynchronous systems. It does not. The patent provides no basis
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`for interpreting the claims as broadly as Petitioner proposes.
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`4
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`IPR2018-01249
`U.S. Patent 7,693,002
`D. Extrinsic Evidence Shows That Petitioner’s Construction Of
`“Clock Signal” Is Overly Broad
`Qualcomm showed in its response that unbiased and reliable extrinsic
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`evidence supports its construction of “clock signal” as “a periodic signal used for
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`synchronization.” Paper 11 at 11-12. Specifically, the response cited the IEEE
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`Dictionary’s definition of the term “clock signal” as “[a] periodic signal used for
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`synchronizing events.” Ex. 2002 at 9.
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`Petitioner does not dispute that the IEEE Dictionary’s definition of “clock
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`signal” is nearly identical to Qualcomm’s proposed construction of the same term.
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`Paper 15 at 6-7. Instead, Petitioner cites the IEEE Dictionary’s definition of “clock”
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`and argues that this definition shows that the claimed “clock signal” need not be
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`periodic. Id. (citing Ex. 1014 at 4). As an initial matter, the claim term at issue is
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`“clock signal”—not “clock”—and Petitioner provides no explanation as to why the
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`IEEE Dictionary’s definition of “clock” is allegedly more relevant than the
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`dictionary’s definition of “clock signal.” See Paper 15 at 6-7. It is not. The IEEE
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`Dictionary has seven entries for the term clock, as Dr. Horst acknowledged at
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`deposition (Ex. 2006 at 71:21-72:3), but only one entry for the term “clock signal,”
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`thus demonstrating that the term “clock” is broader than the term “clock signal” and
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`not its equivalent. See Ex. 1014 at 4.
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`5
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`IPR2018-01249
`U.S. Patent 7,693,002
`In any event, Petitioner’s cited definition of “clock” from the IEEE Dictionary
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`is completely silent as to whether the signal needs to be periodic. Ex. 1014 at 4. But
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`when read in conjunction with the dictionary’s definition of “clock signal”—“[a]
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`periodic signal used for synchronizing events”—it is clear that the signal is, in fact,
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`periodic. Id. at 5 (emphasis added).
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`Petitioner’s argument based on the Modern Dictionary of Electronics
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`(Paper 15 at 7) fails for similar reasons. The reply cites the Modern Dictionary’s
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`definitions of “clock”—not “clock signal”—but the cited definitions provide no
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`indication as to whether a clock signal is periodic or not. Dr. Horst conceded this at
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`deposition. Ex. 2006 at 79:8-12.
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`
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`When read in conjunction with other portions of the Modern Dictionary of
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`Electronics, however, it is clear that the signal is periodic. For example, the
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`dictionary defines “clock frequency” as follows: “In digital computers, the master
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`frequency of periodic pulses that are used to schedule the operation of the computer.”
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`Ex. 1015 at 4. This definition references the “digital computer” system mentioned
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`in the definition of “clock” (id. at 3-4) and shows that synchronization in such a
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`system is performed using a periodic signal.
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`6
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`IPR2018-01249
`U.S. Patent 7,693,002
`Itoh Does Not Show That The Claimed “Clock Signal”
`Encompasses Non-Periodic Signals
`Qualcomm showed in its response that the POSA would not have viewed
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`E.
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`timing signals in asynchronous systems as clock signals. Paper 11 at 12-14.
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`Qualcomm showed, among other things, that Itoh’s row address strobe (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and
`column address strobe (cid:1829)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) are asynchronous memory “timing signals” or “control
`strobe (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) and column address strobe (cid:1829)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) as “control signal[s],” rather than “clock
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`signals” (Ex. 2001 at ¶¶59-62), and that Itoh never refers to these signals as being
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`“clock signals” (id.). In fact, page 361 of Itoh explicitly refers to the row address
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`signals,” as claimed. Ex. 2003 at 361.
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`In an attempt to rebut this showing, Petitioner cherry picks excerpts from a
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`completely different portion of Itoh—pages 142 and 149, more than 200 pages
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`before Qualcomm’s cited portions at page 361—mentioning an “(cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) clock buffer”
`and “a clock ΦB generated by the (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) buffer.” Paper 15 at 7-8. But Petitioner has
`shows (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) to be a non-periodic “control signal”—in contrast to the periodic clock
`signal CLK—and includes no description or illustration of an “(cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) clock buffer” or
`described “(cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) clock buffer” and “clock ΦB” are somehow relevant to the later-
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`not established the relevance of the earlier portion of Itoh at pages 142 and 149 to
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`the later portion at page 361 cited by Qualcomm. See id. The later portion of Itoh
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`“a clock ΦB.” Ex. 1007 at 142, 149. Thus, there is no indication that the earlier-
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`7
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`

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`described (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) signal, much less any indication that the non-periodic (cid:1844)(cid:1827)(cid:1845)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364)(cid:3364) signal
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`IPR2018-01249
`U.S. Patent 7,693,002
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`should be considered a clock signal.
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`The reply also argues that in the synchronous system of Itoh Figure 6.15, the
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`non-periodic address strobe signal RS1 is used in activating a wordline, and that this
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`disproves Qualcomm’s contention that a periodic clock signal synchronizes all
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`memory operations in synchronous systems. See Paper 15 at 8-9. But Qualcomm
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`does not dispute that timing signals other than the periodic clock signal may be used
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`to time operations in synchronous systems. See, e.g., Ex. 2001 at ¶62. In
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`synchronous systems, all events and all timing signals—such as the RS1 signal in
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`Figure 6.15 of Itoh—are synchronized to the single, periodic clock signal, whereas
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`no such single synchronizing signal exists in asynchronous systems. Id. at ¶¶60-62.
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`Figure 6.15 of Itoh clearly shows that both RS1 an CS1 are triggered by the clock
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`signal’s rising edge and are thus synchronized by the periodic clock signal. Ex. 2003
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`at 19.
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`Petitioner also argues that in the synchronous system of Itoh Figure 6.15, the
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`CLK clock signal “is not necessarily passed to an address decoder.” Paper 15 at 9-
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`10. But even if true, this proves nothing. Qualcomm never argued that the system
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`of Itoh Figure 6.15 is the same as the memory system of the ’002 patent. Ex. 2001
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`at ¶¶61-69. Petitioner’s argument that the two systems are not identical is a red
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`herring and does not rebut Qualcomm’s showing.
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`8
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`IPR2018-01249
`U.S. Patent 7,693,002
`F.
`Petitioner’s New References Do Not Support Its Construction
`In a last-ditch effort, Petitioner cites new references that allegedly “refer to
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`non-periodic signals as clock signals.” Paper 15 at 10. But none of these references
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`supports the overly broad construction of “clock signal” advanced in the reply.
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`Petitioner cites U.S. Patent No. 4,922,461 to Hayakawa (Ex. 1016) and argues
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`that this reference refers to a clock signal ((cid:2038)S) that “is only ‘effective in level for a
`argument of the reply does not show that the signal (cid:2038)S of Hayakawa is non-periodic.
`indicate whether the signal (cid:2038)S is periodic or not. Moreover, other portions of
`Hayakawa indicate that signal (cid:2038)S transitions between logic-level low and high states
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`fixed period of time.’” Paper 15 at 10 (citing Ex. 1016 at 3:50-57). But the cursory
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`The phrase “effective in level for a fixed period of time” is ambiguous and does not
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`at regular, periodic intervals. Ex. 1016 at 6:3-22, 6:65-7:3.
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`The reply also cites two papers published by Qualcomm’s expert Dr. Pedram
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`(Exs. 1017, 1018) as allegedly disclosing non-periodic clock signals. Paper 15 at 10.
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`But Petitioner’s citation to these papers merely evidences its misunderstanding of a
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`gated clock signal in relation to the claimed “clock signal.” As Dr. Pedram testified
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`at deposition, a “gated clock signal” is different than the claimed “clock signal” and
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`can be turned on and off to propagate the clock signal or not. Ex. 1019 at 31:7-11.
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`Whenever the clock signal is being propagated, it is a periodic signal for the reasons
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`9
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`IPR2018-01249
`U.S. Patent 7,693,002
`explained in Qualcomm’s response. Paper 11 at 11-15. Petitioner’s cursory
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`argument (Paper 15 at 10) does not disprove this.
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`G. Dr. Alpert’s Previous Testimony On The Meaning Of “Clock” Is
`Relevant To The Construction Of “Clock Signal”
`Qualcomm’s response showed that Apple’s ITC expert, Dr. Alpert, previously
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`told the Board that the term “clock” should be interpreted as “a periodic signal used
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`for synchronization.” Paper 11 at 14-15 (citing Ex. 2004 at 3-4). The reply argues
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`that Dr. Alpert’s previous testimony was “on behalf of a different party (not Apple),
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`in a different IPR, and in reference to a different patent” (Paper 15 at 10-11), and is
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`therefore irrelevant.
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`But Petitioner is wrong. As Qualcomm showed, Dr. Alpert testified that the
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`“definition [‘a periodic signal used for synchronization’] is consistent with the
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`broadest reasonable interpretation of the term [‘clock’].” Ex. 2004 at 3-4. In so
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`testifying, Dr. Alpert relied on the very same IEEE Dictionary definition that
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`Qualcomm now cites. See id. Moreover, Dr. Alpert did not qualify his opinion on
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`the meaning of “clock” or indicate that it was specific to that previous proceeding or
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`the patent involved therein. See Ex. 2004 at 3-4. The fact that Dr. Alpert was
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`testifying on behalf of a different party in the previous proceeding is of no
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`consequence.
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`10
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`IPR2018-01249
`U.S. Patent 7,693,002
`Petitioner’s Proposed Construction Is Wrong For The Reasons
`Stated In Qualcomm’s Patent Owner Response
`The reply argues that the term “clock signal” should be construed as “a signal
`
`H.
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`used for synchronization.” Paper 15 at 11. This construction is overly broad because
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`it encompasses non-periodic timing and control signals. The POSA would not
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`consider any of these signals to be clock signals for the reasons stated in
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`Qualcomm’s response. Paper 11 at 11-15. The Board should apply the proper
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`construction of clock signal proposed by Qualcomm, i.e., “a periodic signal used for
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`synchronization,” for the reasons stated above and in Qualcomm’s response.
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` Sato Does Not Render Obvious Claims 1-28 And 31-37 (Ground 1)
`A. The Petition Failed To Address All Of The Graham Factors
`Qualcomm’s response showed that the petition failed to establish a prima
`
`facie case of obviousness over Sato because it did not identify any differences
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`between the reference and the claims. Paper 11 at 28-30.
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`Sato’s selection control signal (cid:2038)ce allegedly “represents or renders obvious a clock
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`In its reply (Paper 15 at 12-13), Petitioner cites the petition’s statement that
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`signal” (Paper 2 at 14), and argues that this is a sufficient identification of a
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`difference between the claims and Sato. But this statement only highlights the
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`gamesmanship employed by Petitioner. Specifically, this statement and others (id.
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`at 14-17) show that Petitioner knew when its petition was filed that the key dispute
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`for Sato would be whether it discloses a clock signal. Despite this, Petitioner failed
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`
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`11
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`IPR2018-01249
`U.S. Patent 7,693,002
`to provide any construction for the term until its reply. And rather than explain any
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`differences between Sato’s selection control signal (cid:2038)ce and the claimed clock signal,
`that the signal (cid:2038)ce is a clock signal. See, e.g., Paper 2 at 10 (“Sato selectively applies
`a clock signal ((cid:2038)ce) to wordline drivers….”).
`If Petitioner believed that Sato’s selection control signal (cid:2038)ce is a clock signal,
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`Petitioner instead presented Sato as if it was anticipatory, asserting multiple times
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`then the petition should have presented Sato as an anticipation ground. It did not.
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`Instead, the petition hedged on the meaning of clock signal and further hedged on
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`whether Sato allegedly anticipates the claims or renders them obvious. This is
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`contrary to “the expedited nature of IPRs,” which “bring[s] with it an obligation for
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`petitioners to make their case in their petition to institute.” Intelligent Bio-Systems,
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`Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359, 1369 (Fed. Cir. 2016).
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`B.
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`Sato Does Not Disclose The Claimed “Clock Signal” Because Its
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`Selection Control Signal (cid:2038)ce Is Not Periodic
`Sato’s signal (cid:2038)ce does not teach or suggest the claimed clock signal because
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`it is not periodic. Paper 11 at 30-33. In its reply, Petitioner points to the IEEE
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`Dictionary’s definition of “clock signal” indicating that this term is synonymous
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`with “clock pulse” (Ex. 1014 at 5), and argues that the terms “clock signal” and
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`“timing signal” should therefore have the same meaning. Paper 15 at 13. But the
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`dictionary nowhere equates the term “clock signal” with either of the specific terms
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`12
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`IPR2018-01249
`U.S. Patent 7,693,002
`recited in Sato, i.e., “timing signal” and “selection control signal.” See Ex. 1014 at
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`4-5. The cited definition of “clock signal” instead only refers to the different term
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`“clock pulse” (id. at 5), and Qualcomm does not dispute that a periodic clock signal
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`may be understood as including a plurality of regularly spaced, uniform clock pulses.
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`This is not proof, however, that the terms “clock signal” and “timing signal” are
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`interchangeable. Moreover, the IEEE Dictionary definition of “clock pulse” merely
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`states “See: clock signal.” Ex. 2002 at 9.
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`The reply also disputes Dr. Pedram’s testimony (Ex. 2001 at ¶109) that the
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`symbol (cid:2038) is used in the art to denote a phase signal, not a clock signal. Paper 15
`at 14. Petitioner cherry picks references that use the symbol (cid:2038) to refer to a clock
`signal, but the existence of one or more isolated references that use the symbol (cid:2038) in
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`this non-conventional manner does not rebut Dr. Pedram’s testimony of how this
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`symbol is most commonly used in the art. Dr. Pedram has over 30 years of
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`experience in the field of computers and memory systems, and his testimony on the
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`common usage of the symbol (cid:2038) is informed by this extensive experience. See
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`Ex. 2001 at ¶¶4-19.
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`
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`Petitioner tries to minimize the gulf between Sato and the ’002 patent, stating
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`that “[a]ny disagreement is merely over the timing of pulses in Sato’s timing signal.”
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`Paper 15 at 15. But as Qualcomm explained (Paper 11 at 33-35), the asynchronous
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`memory system of Sato—which uses multiple, non-periodic timing signals—is
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`13
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`IPR2018-01249
`U.S. Patent 7,693,002
`fundamentally different than the synchronous memory system of the ’002 patent,
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`which uses the single, periodic clock signal. Id. at 12-15 (explaining that
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`asynchronous memory systems are event-driven and must include control circuitry
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`for receiving the asynchronous inputs and generating appropriately timed sequences
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`of internal timing signals, whereas in synchronous memory systems, a single,
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`periodic, synchronizing clock is used to time all memory operations). Accordingly,
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`Sato’s failure to disclose one of the distinguishing factors between synchronous and
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`asynchronous systems, i.e., a periodic clock signal, is not a minor difference, as
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`Petitioner suggests.
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`Moreover, Sato’s failure to disclose the periodic clock signal is not the only
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`difference between Sato and the ’002 patent. See, e.g., Paper 11 at 22-23 (explaining
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`difference between parallel arrangement of ’002 patent and serial operation of Sato,
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`where the parallel arrangement reduces a timing delay in providing the clock signal
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`to a particular wordline driver). For example, Sato fails to achieve reduced loading
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`on a clock signal, in contrast to the design of the ’002 patent. The Background
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`section of the ’002 patent describes that one of the problems of conventional memory
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`systems was the heavy load placed on the clock signal. Ex. 1001 at 1:11-25. To
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`address this issue and others of the prior art, the ’002 patent describes an improved
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`wordline driver system having separate first and second logics:
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`Id. at Fig. 1 (annotations added).
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`The ’002 patent describes that the first logic decodes a first portion of the
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`memory address and applies a clock signal to a selected clock output. Id. at 3:26-
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`31. The second logic, by contrast, decodes a second portion of the memory address
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`and selectively activates a particular wordline driver, operating independently of the
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`clock signal. Id. at 3:36-45. Accordingly, in the ’002 patent, the first portion of the
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`memory address is clocked, while the second portion is not, and there is a decoupling
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`of the clocking functionality of the circuit device from its decoding functionality.
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`This design provides the benefit of reduced loading on the clock signal, thus
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`addressing the problem described in the Background section of the patent. Ex. 1001
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`at 1:11-25.
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`In Sato, by contrast, both of the circuits that Petitioner identifies as the “first
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`logic” and “second logic” are controlled by the alleged clock signal (cid:2038)ce, and the
`“first logic”) receives and processes the selection control signal (cid:2038)ce in generating
`the selection control signal (cid:2038)ce. Ex. 1005 at 5:66-6:21. Petitioner’s declarant Dr.
`first and second logics of Sato operate based on the alleged clock signal (cid:2038)ce, and
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`alleged second logic of Sato does not activate a particular wordline driver
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`independently of the clock signal. Specifically, in Sato, the PDCR (i.e., the alleged
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`its output. Paper 11 at 16-23. Further, Sato makes clear that the operation of the
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`NAND gate circuits NAG0-NAGk (i.e., the alleged “second logic”) is controlled by
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`Horst confirmed this at deposition. Ex. 2005 at 34:10-16. Thus, both the alleged
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`this is in contrast to the design of the ’002 patent.
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`C.
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`Sato Does Not Render Obvious The Periodic “Clock Signal”
`Required By The Claims
`Perhaps recognizing that Sato includes no disclosure or suggestion of a
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`periodic clock signal, Petitioner advances the backup argument that Sato somehow
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`renders this limitation obvious. Paper 15 at 16-18. Petitioner specifically argues
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`that “a POSITA would have understood that Sato’s address decoder would function
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`fundamentally the same regardless of whether the timing signal was periodic or not.”
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`Id. at 16.
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`Petitioner fails to provide any evidence or analysis to show that Sato would
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`work with a periodic clock signal. See Paper 15 at 16. Petitioner cites the
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`supplemental declaration of Dr. Horst, but the declaration parrots the reply without
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`providing any reasoning or explanation. See Ex. 1013 at ¶35. And Dr. Horst
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`conceded at deposition that he performed no simulations or tests to determine
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`whether Sato would actually work with a periodic signal. Ex. 2006 at 87:2-4.
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`In any event, there are many reasons why the POSA would not have been
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`motivated to modify Sato as proposed. As Qualcomm explained in its response
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`(Paper 11 at 38-39), synchronous systems that use a periodic clock signal are
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`fundamentally different than the asynchronous system of Sato, such that using a
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`periodic clock signal in Sato would require significant modifications that Petitioner
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`has not explained. In a synchronous system, each function is timed with the clock
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`signal’s rising or falling edge. Id. Accordingly, to ensure the system’s proper
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`functioning, each function needs to finish its operation within a clock period with
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`some margin. If Sato’s selection control signal (cid:2038)ce is replaced with a periodic clock
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`signal, the circuit will not necessarily be fast enough to handle the clock signal.
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`For instance, Sato’s circuit includes NAND gates NAG0-NAGk that operate
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`in two states—an evaluation state and a precharge state. Ex. 2001 at ¶77; Ex. 2006
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`at 90:16-22. When the selection control signal (cid:2038)ce is high, the NAND gates are in
`the evaluation state, and the signal (cid:2038)ce discharges the output of one selected NAND
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`gate to a low level. Ex. 2001 at ¶112; Ex. 2006 at 91:3-13. Discharging the output
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`of the selected NAND gate takes an amount of time that is dictated by characteristics
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`of the three NMOS transistors Qg2, Qg3, and Qg4 of the NAND gate (Ex. 2006
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`at 91:14-21):
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`Ex. 1005 at Fig. 3 (annotations added). In replacing Sato’s selection control
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`signal (cid:2038)ce with a periodic clock signal, if the clock signal transitions from high to
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`low too quickly, the output of the selected NAND gate cannot discharge completely,
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`Ex. 2006 at 88:3-5.
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`thus causing the circuit to malfunction. Dr. Horst acknowledged this at deposition.
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`Accordingly, if Sato’s selection control signal (cid:2038)ce is replaced with a periodic
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`clock signal, in many instances the circuit will not work unless it is specifically
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`redesigned to operate at the frequency of the clock signal.
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`D.
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`Sato Does Not Meet The “Clock Signal” Limitation Even Under
`Petitioner’s Proposed Construction
`Petitioner proposed for the first time in its reply that the term “clock signal”
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`should be construed as “a signal used for synchronization.” Paper 15 at 11. This
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`construction is erroneous, but even if the Board accepts Petitioner’s construction,
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`Sato still fails to meet this limitation because the selection control signal (cid:2038)ce is not
`In Sato, the selection control signal (cid:2038)ce is provided to the predecoder PDCR
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`used for synchronization.
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`(i.e., the alleged “first logic”) and the NAND gate circuits (i.e., the alleged “second
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`logic”) in such a way that the predecoder gates the outputs of the NAND gate circuits
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`in a serial fashion. Specifically, outputs of the NAND gate circuits are not applied
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`to the wordline drivers until selected by outputs of the predecoder PDCR, which are
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`received by the capacitance cut MOSFETs (e.g., Q19, Q20, etc.). Ex. 1005 at 9:68-
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`10:4. The alleged first and second logics of Sato are not synchronized—
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`i.e., operating at the same time—because the predecoder PDCR is controlling the
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`output of the NAND gate circuits. In other words, th