Umted States Patent
`
`[19]
`
`[11] Patent Number:
`
`4,951,259
`
`
`Sato et a1.
`[45] Date of Patent:
`Aug. 21, 1990
`
`[54] SEMCONDUCIOR MEMORY DEVICE
`DRIVEII” EISRST AI 1: SECOND WORD LINE
`
`[75]
`
`Inventors: Yoichi Sato, Iruma; Satoshi
`Shinagawa, Ohme, both of Japan
`
`4,763,304
`8/1988 Uesugi ............................ 365/230 X
`Primary Examiner—Stuart N. Hecker
`Assistant Examiner—Alyssa H. Bowler
`Attorney. Agent, or Firm—Antonelli, Terry, StOUt &
`Kraus
`
`[73] Assignees: Hitachi, Ltd.; Hitachi VLSI
`glazeenng Corp., bOth 0f Tokyo,
`p
`[21] Appl. No.: 156,742
`[22] Filed:
`Feb. 18, 1988
`.
`_
`_
`_
`.
`FOTEIEII Application Priority Data
`[30]
`Feb. 13, 1987 [JP]
`Japan .................................. 62-33201
`
`Int. Cl.5 .......................... GllC 7/00; GllC 8/00
`[51]
`_
`.
`[52] US. Cl. .......................... 365/230.06, 365/ 189.03,
`365/204
`[58] Field of Search ............... 365/189 206 230 204
`365/23006, 189.03; 307/463
`References Cited
`
`[56]
`
`U.S. PATENT DOCUMENTS
`
`4,620,299 10/1986 Remington .......................... 365/230
`4,685,088 8/ 1987
`Iannucci ...................... 365/230
`4,706,222 11/1987 Kwiatkowski et a1.
`...... 365/230
`4,719,603
`1/1988 Shinagawa ............... 365/230
`
`
`
`[57]
`ABSTRACT
`A semiconductor memory device is provided which
`includes a plurality of word line drivers and logic de-
`coding circuitry coupled to the inputs of the word line
`drivers. In large memory arrays, the word line driver
`Cll‘CllltS can place large capacmve loads on the output of
`the logic decoding circuit because the word line driver
`transistors must be relatively large- This large load on
`the logic decoding circuitry adversely effects the oper»
`atin
`.
`.
`g speed of the memory. Accordingly, to reduce this
`load, a switchin arrangement is
`rovided between the
`g.
`P
`“‘1’“ 0f the 10g“: de°°ding Circuitry and the word line
`drivers. This switching arrangement can be controlled
`to respectively connect the output of the logic decoding
`circuit to the word line drivers based on control output
`signals of a pre-decoder. Reset MOSFETs can also be
`provided to prevent the inputs of the word line drivers
`from floating.
`
`19 Claims, 4 Drawing Sheets
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`US. Patent
`
`Aug. 21, 1990
`
`Sheet 1 014
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`4,951,259
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`FIG.
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`US. Patent
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`Aug. 21, 1990
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`Sheet 2 of4
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`4,951,259
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`FIG. 2
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`US. Patent
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`Aug. 21, 1990
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`Sheet 3 of4
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`4,951,259
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`US. Patent
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`Aug. 21, 1990
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`Sheet 4 of4
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`4,951,259
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`FROM XADB
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`1
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`4,951,259
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`'
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`SEMICONDUCTOR MEMORY DEVICE WITH
`FIRST AND SECOND WORD LINE DRIVERS
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to semiconductor memory
`devices and to a technique which will be effective when
`applied, for example, to CMOS (Complementary MOS)
`static RAMs (Random Access Memories).
`CMOS static RAMs including clocked static decod-
`ers are known in the art. A method of improving chip
`layout efficiency has been proposed by disposing a pre-
`decoder PDCR shown in FIG. 5 in an X address de-
`coder XDRC of such a CMOS static RAM.
`Japanese Pat. Laid-Open No. 74890/1981, for exam-
`ple, describes the address decoder of such a static
`RAM. This publication is hereby incorporated by refer-
`ence.
`
`In FIG. 5, the X address decoder XDCR of the
`CMOS static RAM includes one pre-decoder PDCR
`and a plurality of NAND gates for decoding repre-
`sented by a NAND gate circuit NAG 0. Here, the pre-
`decoder PDCR receives lower 2-bit complementary
`internal address signals 3x0 and 3x1 (where an internal
`address signal such as ax0 having the same phase as an
`external addres_s_signal AXO, and an internal address
`signal such as axO having an opposite phase to the phase
`of the external address signal AXO are together ex-
`pressed as complementary intemal address signal axO),
`for example, and generates selection signals ¢x0~¢x3.
`As represented typically by the NAND gate circuit
`NAG 0 in FIG. 5, each NAND gate circuit consists of
`a plurality of N-channel MOSFETs ng~Qg3 which are
`connected in series to receive complementary internal
`address signals ax2~axi combined with one another in
`such a manner as to correspond to the gates of these
`transistors, and a P-channel MOSFET Q31 and an N-
`channel MOSFET Q34 disposed between these MOS-
`FETs Q32, Q3 and a power source voltage Vcc and
`ground potential of the circuit, respectively.
`. As represented by word lines W0~W3, each word
`line of a memory array M-ARY is connected to a word
`line drive circuit corresponding thereto. These word
`line drive circuits each consist of a P-channel MOSFET
`Q41 and an N-channel MOSFET de connected in a
`CMOS inverter circuit arrangement. Four word line
`drive circuits are connected to each decoding NAND
`gate circuit of the X address decoder XDCR. Each
`word line drive circuit has the function of a part of the
`X address decoder XDCR when the corresponding
`selection signal ¢x0~¢x3 is Supplied from the pre-
`decoder PDCR described above to the source of the
`P-channel MOSFET le constituting that word line
`drive circuit.
`
`SUMMARY OF THE INVENTION
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`However, the inventors of the present invention have
`clarified as a result of their studies that the following
`problem develops in the static X address decoder of the
`kind described above when the memory capacity of 60
`CMOS static RAMS is increased. The parasitic capaci-
`tance connected to each word line increases with the
`increase in the memory capacity of the CMOS static
`RAM, and the rise of the voltage level of the word line
`which is brought into the selection state is delayed. If 65
`the sizes of MOSFETS Q11 and Q42 are increased to
`increase the driving capacity of the word line drive
`circuit in order to cope with the problem described
`
`2
`above, the drain capacitance as well as gate capacitance
`of these MOSFETS become great and loads on the
`pre-decoder PDCR and on the decoding NAND gate
`circuit increase, too. The influence of the increase of the
`loads becomes particularly remarkable in the decoding
`NAND gate circuit in which a plurality of MOSFETs
`are connected in series, and this is one of the factors that
`prevent a higher operation speed of static RAMs.
`It is therefore an object of the present invention to
`provide a semiconductor memory device such as a
`CMOS static RAM which speeds up the selection oper-
`ation of the X address decoder and the operation speed
`of memory access.
`The above and other objects and novel features of the
`present invention will become more apparent from the
`following description when taken in conjunction with
`the accompanying drawings.
`Among the inventions disclosed herein, the following
`will illustrate a typical example.
`A capacitance cut MOSFET is provided for receiv-
`ing a corresponding output signal of a pre-decoder, for
`example, at its gate. This capacitance(cut MOSFET is
`disposed between a decoding logic gate circuit of an X
`address decoder and each word line drive circuit. It
`should be noted that the term “capacitance cut MOS~
`FET” means a MOSFET provided to reduce the capac-
`itive load of a circuit which it is coupled to the output
`of (e.g., in this case, for cutting the capacitive load of
`the decoding logic gate and the pre-decoder). In addi-
`tion, a reset MOSFET is provided which is connected
`at its source, for example, to the power source voltage
`of the circuit and receives at its gate a selection control
`signal. This reset MOSFET is disposed at the input
`terminal of each word line drive circuit.
`According to the means described above, since the
`capacitance cut MOSFET is disposed in such a manner
`as to correspond to each word line drive circuit, driva-
`bility of the word line drive circuit can be increased
`without increasing loads on the output signals of the
`pre-decoder and on the decoding logic gate circuit, that
`is, without exerting any undesirable influences on the
`selection operation of the X address decoder. Accord-
`ingly, it becomes possible to increase the memory ca-
`pacity of a semiconductor memory device such as a
`CMOS static RAM and to attain its higher operation
`speed.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG; 1 is a circuit diagram showing an X address
`decoder of a static RAM in accordance with the first
`embodiment of the present invention;
`FIG. 2 is a circuit diagram showing the X address
`decoder of the static RAM in accordance with the sec-
`ond embodiment of the present invention;
`FIG. 3 a circuit diagram showing the X address de-
`coder of the static RAM in accordance with the third
`embodiment of the present invention;
`FIG. 4 is a block circuit diagram showing one em-
`bodiment of the static RAM in accordance with the
`present invention, and
`FIG. 5 is a circuit-diagram showing an example of an
`X address decoder of a conventional static RAM.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Embodiment 1
`
`6
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`20
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`3
`FIG. 4 shows a block circuit diagram of a CMOS
`static RAM in accordance with the first embodiment of
`the present invention. Each circuit element of the draw~
`ing is formed on one semiconductor substrate such as
`single crystal silicon by known fabrication technique of 5
`CMOS integrated circuits, though not particularly limi—
`tative. In the drawings to follow, MOSFETs repre-
`sented by an arrow at their channel (back gate) are of a
`P-channel type while MOSFETs not having the arrow
`are of an N-channel type.
`In FIG. 4, a memory array M-ARY consists of m+1
`worg_lines W0~Wm, n+1 complementary data lines
`D0-D0~Dn-fi1 and (m+1)><(n+1) memory cells dis-
`posed at the points of intersection of these word lines
`and complementary data lines.
`’
`Though not particularly limitative, each memory cell _
`consists fundamentally of two sets of CMOS inverter
`circuits consisting in turn of a P-channel MOSFET Q21
`and an N-channel MOSFET Q1 and a P-channel MOS-
`FET Q22 and an N—channel MOSFET Q2. The input
`and output terminals of these CMOS inverter circuits
`are cross-connected with each other in the latch form
`and constitute a flip-flop as a memory device of this
`CMOS static RAM.
`The drains of MOSFETs Q21 and Q1 and the drains
`of MOSFETs Q22 and Q2 that are connected in com-
`mon are used as the input and output nodes of this flip-
`flop and further connected to the corresponding com-
`plementary data lines D0D0 through N-channel trans- 30
`fer gate MOSFETs Q3 and Q4, respectively. The gates
`of these transfer gate MOSFETs Q3 and Q4 are con-
`nected in common to the corresponding word line W0.
`The other memory cells MC have the same circuit
`construction as described above and are connected 35
`likewise to the corresponding data and word lines,
`thereby forming a memory cell matrix and a memory
`array M-ARY. In other words, the input/output nodes
`of the memory cells MC disposed on the same row are
`connectedto the _c_orresponding complementary data 40
`lines D0-D0~DnDn through the corresponding trans-
`fer gate MOSFETs, and the gates of transfer gate MOS-
`FETs of the memory cells MC disposed on the same
`column are connected in common to the corresponding
`word .lines W0~Wm, respectively.
`As shown typically in FIG. 4, N-channel type load
`MOSFET pairs Q5Q6~Q7-Q8 are_disposedbetween
`the complementary data lines DO-D0~Dn~Dn and the
`power source voltage Vcc of the circuit.
`The word lines W0~Wm are connected to the X 50
`address decoder XDCR. Complementary internal ad-
`dress signals_ax0~axi (an internal address signal such as
`ax0 having the same phase as an external address signal
`AXO, and an internal address signal axO having the
`opposite phase to the phase of an external address signal 55
`AXO will be hereinafter expressed together as the com-
`plementary internal address signal g0) from an X ad-
`dress buffer ADB are supplied to this X address de-
`coder XDCR. A timing signal cbce (a selection control
`signal) is supplied, too, from a later-discussed timing 60
`control circuit TC to the X address decoder XDCR.
`This timing signal «#2 is generated in accordance with
`a chip enable signal CE supplied as a control signal from
`outside and is kept at a high level under‘the selection
`state of this CMOS static RAM. As will be described 65
`later, the X addressdecoder XDCR is selectively actu-
`ated by the timing control signal oce, decodes the com-
`plementary internal address signals gx0~gxi and sets
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`one of the word lines designated by the X address sig-
`nals AXO~AXi to the high level selection state.
`The definite circuit construction and operation of the
`X address decoder will be described later in further
`detail.
`The X address buffer XADB receives the X address
`signals AXO~AXi supplied through external terminals
`AXO~AXi and generates the complementary internal
`address signals 3x0~_a_xi on the basis of these signals
`AXO~Axi and supplies them to the X address decoder
`XDCR.
`the complementary data lines
`On the other hand,
`D0-Dfi~Dn-fii of the memory array M-ARY are con-
`nected sel_e_c_:tively to the complementary common data
`lines CD-CD through the corresponding switch MOS-
`FET pairs Q9-Q10~Q11oQ12 of the column switch
`SW, respectively. The gates of these switch MOSFET
`pairs Q9-Q10~Q11-Q12 are connected in common and
`the corresponding data line selection signals Y0~Yn
`are supplied“ thereto from the Y address decoder
`YDCR.
`Y address decoder YDCR generates data line selec-
`tion signals Y0 ~Yn for selecting one set of complemen-
`tary data lines and for connectingt_hem to the comple-
`mentary common data lines CD-CD by decoding the
`complementary internal address signals gy0~gyj sup-
`plied from the Y address buffer YADB. This Y address
`decoder YDCR is operated selectively in accordance
`with the timing signal dace supplied from the timing
`control circuit TC in the same way as the X address
`decoder XDCR.
`_
`The complementary common data lines CD~CD are
`connected to the input terminals of a sense amplifier SA
`and to the output terminals of a write amplifier WA.
`The output terminals of the sense amplifier SA are con-
`nected to the input terminals of a data output buffer
`DOB while the input terminals of the write amplifier
`WA are connected to the output terminals of a data
`input buffer DIB.
`The sense amplifier SA is operated selectively in
`accordance with the timing signal 4>sa supplied from the
`timing control circuit TC and amplifies the read signal
`outputted from the selected memory cell MC through
`the complementary common data lines CD-CD. The
`output signal of the sense amplifier SA is supplied to the
`data output buffer DOB.
`The data output buffer DOB is operated selectively in
`accordance with the timing signal dzoe supplied from
`the timing control circuit TC in the read mode of
`CMOS static RAM. The data output buffer DOB fur-
`ther amplifies the read signal of the memory cell output-
`ted from the sense amplifier SA and delivers it to exter-
`nal devices through the input/output terminals DIO.
`The output of the data output buffer DOB is in a high
`impedance state under the non-selection state of CMOS
`static RAM in which the timing signal shoe is at the low
`level and in the write mode.
`On the other hand,
`the data input buffer DOB
`supplies write data supplied from an external device
`through the input/output terminals DIO to a write
`amplifier WA as a complementary write signal in the
`write mode of CMOS static RAM.
`In the write mode of CMOS static RAM, the write
`amplifier is operated selectively in accordance with the
`timing signal ¢we supplied from the timing control
`circuit TC. The write amplifier WA supplies a write
`current, which relies on the complementary write sig-
`nals supplied from the data input buffer DIB, to the
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`4,951,259
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`selected memory cell MC_through the complementary
`common data lines CD-CD. The output of the write
`amplifier WA is in a high impedance state under the
`non-selection state of CMOS static RAM where the
`timing signal ¢we is at the low level, and in its read
`mode.
`The timing control circuit TC generates various tim-
`ing sign_al_s described above on the b_a__sis of a chip enable
`signal CE, a write enable signal WE and an output
`enable signal OE supplied as control signals from out-
`side, and supplies each timing signal to each circuit in
`the manner described above.
`FIG. 1 shows a circuit diagram of one example of the
`X address decoder XDCR of the CMOS static RAM
`shownin FIG. 4.
`In FIG. 1, the X address decoder XDCR of the
`CMOS static RAM includes the pre-decoder PDCR
`which receives the lower 2-bit complementary internal
`address signals 3x0 and 3x1 and k+1 decoding NAND
`gate circuits NAGO~NAGk to which the complemen-
`tary internal address signals ax2~axi other than the
`lower two bits in respective combinations are supplied,
`though the circuit configuration is not particularly limi-
`tative.
`
`The pre-decoder PDCR decodes the lower 2-bit
`complementary internal address signals 3x0 and _axl
`supplied thereto from the X address buffer XADB and
`generates selection signals ¢x0~d>x3. These selection
`signals ¢x0~¢x3 are formed selectively in accordance
`with the complementary internal address signals axO
`and a_x1. In other words, the selection signal <;bx0 is set to
`the high logic level when both the inversed internal
`address signals and) and air—1 are at the high logic level.
`Similarly, the selection signals 43x1, ¢x2 and ¢x3 are set
`to the high logic level when both the non-inversed
`internal address signal ax0 and the inversed internal
`address signal iii are at the high logic legl, when both
`the inversed internal address signal
`in!) and non-
`inversed internal address signal axl are at the high logic
`level and when both the non-inversed internal address
`signals ax0 and axl are at the high logic level, respec-
`tively,
`On the other hand, each of the decoding NAND gate
`circuits NAGO~NAGk consists of a P-channel MOS-
`FET le, N-channel MOSFETs Qg2, Qg3 and N-
`channel MOSFET Qg4 disposed in series between the
`power source voltage Vcc of the circuit and the ground
`potential. The gates of MOSFETs le and Qg4 are
`connected in common and the timing signal (bee (selec-
`tion control signal) described above is supplied to them.
`The complementary internal address signals gx2~311i in
`the corresponding combinations are applied to the gates
`of MOSFETs Q2g~Qg3.In o__ther words, the inversed
`internal address signals ax2~ax1 are all applied to the
`gates of MOSFETs Qg2~ Qg3 of the NAND gate cir-
`cuit NAG 0 and the non-inversed internal address sig-
`nals ax2~axi are all supplied to the gates of MOSFETs
`Qg2~Qg3 of the NAND gate circuit NAG k. Simi-
`larly, the complementary internal address signals 3x2—
`~gxi which are combined in such a manner as to be the
`binary number corresponding to the number of the
`respective NAND gate circuit using the complemen-
`tary internal address signal 21x2 as the lowermost bit are
`supplied to the gates of MOSFETs Qg2~Qg3 of the
`NAND gate circuits NAG1~NAGk-l.
`Accordingly, the output signal of the NAND_gate
`circuit NAGO, that15, the inversed selection signal SD, is
`ordinarily at the high logic level under the non-selec-
`
`.
`6
`tion state of CMOS static RAM, and is set to the low
`logic levelin synchronism with the timing sig__nal ¢_c_e
`when all the inversed internal address signals ax2~axi
`are at the high logic level. In other words, the inversed
`selection signal S5 is at the low logic level when the
`CMOS static RAM is under the selection state and any
`one of the word lines W0 through W3 is designated by
`the X address signal AXO-AXi. Similarly, the output
`signal of the NAND gate circuit NAGk, that is, the
`inversed selection signal Sk, is at the low logic levelin
`synchronism with the timing signal ¢ce when all the
`nominversed internal address signals ax2~axi are at the
`high logic level. In other words, the inversed selection
`signals ST: is at the low logic level when CMOS static
`RAM is under the selection state and any one of the
`word lines Wm-3~Wm is designated by the X address
`signal AXO~AXi. The output signals of the NAND
`gate circuits NAG1~_NAGk-1,
`that is,
`the inversed
`selection signals S1~Sk-1, which are not shown in the
`drawing, are generated by the same logic as described
`above.
`(m+l) word line drive circuits WDO~WDm are
`disposed in the X address decoder XDCR of this
`CMOS static RAM in such a manner as to correspond
`to the word lines W0~Wm of the memory array
`M-ARY. As represented typically by the word line
`drive circuits WDO, WD3, WDm-3 and WDm shown in
`FIG. 1, these word line drive circuits WDO~WDm
`each comprise a CMOS inverter circuit which consists
`of a P—channel MOSFET le and an N-channel MOS-
`FET Qd2. In order to provide a CMOS static RAM
`with a relatively large memory capacity, a relatively
`large memory capacitance consisting primarily of the
`gate capacitance of the transfer gate MOSFET of the
`memory cell is connected to each word line W0~Wm
`of the memory array M-ARY. For this reason, MOS-
`FETs le and Qd2 have a relatively large conductance
`and each word line drive circuit WDO~de is de-
`signed to have relatively 1a___rge d__rivability.
`The selection signals SO~ Sk generated by the
`NAND gate circuits NAGO~NAGk are supplied to
`the corresponding four sets of word line drive circuits
`WDO~WD3 or WDm—3~WDm through the corre-
`sponding capacitance cut MOSFETs Q13‘~ Q14 or
`Q15~Q16, respectively. Among the four capacitance
`cut MOSFETs of each set, the selection signal (#110 is
`supplied in common from the pie-decoder PDCR to the
`gate of the first MOSFET represented by MOSFETs
`Q13 and Q15, and the selection signal (#113 is supplied in
`common to the gate of the fourth MOSFET repre-
`sented by MOSFETs Q14 and Q16. Similarly, the selec-
`tion signals d>xl and (bx2 are supplied in common from
`the pre-decoder PDCR to the gates of the second and
`third MOSFETs among the four capacitance cut MOS-
`FETs of each set,
`resp_ective__ly. Accordingly, the in-
`versed selection signal SO~Sk of the low logic levelis
`transmitted to only the word line drive circuit corre- ,
`sponding to one word line that is designated by the X
`address signal Ax0~Axi.
`These capacitance cut MOSFETs Q13~Q16 are
`disposed between the output terminals of the decoding
`NAND gate circuits NAGO~NAGk and the input
`terminals of the word line drive circuits WDO~WDm;
`hence the level of the input terminal of each word line
`drive circuit under the non-selection state is in the float-
`ing state. To prevent this, a P-channel reset MOSFET
`Q23~Q24 or Q25~Q26 is disposed between the input
`terminal of each word line drive circuit and the power
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`source voltage Vcc of the circuit. The timing signal ¢ce
`described above is supplied in common to the gates of
`these
`reset MOSFETs. These
`reset MOSFETs
`Q23~Q24 or Q25~Q26 are turned 0N together under
`the non-selection state of the CMOS static RAM where
`the timing signal cbce is at the low logic level, and set
`the level of the input terminals of the corresponding
`word line drive circuits WDO~WDm to the high logic
`level. Accordingly, the output terminal of each word
`line drive circuit, that is, the level of the word line
`W0~Wm, is fixed at the low level nonoselection state.
`When the CMOS static RAM is brought into the selec-
`tion state and the timing signal time rises to the high
`logic
`level,
`the reset MOSFETS Q23~Q24 or
`Q25~Q26 are turned OFF. At this time, the inversed
`selection signal of the low logic level is supplied to the
`word line drive circuit corresponding to the word line
`which is designated by the X address signal AXO~AXi.
`Therefore, the output terminal of this word line drive
`circuit, that is, the designated word line, is under the
`high level selection state. On the other hand, the input
`terminals of the word line drive circuits which are not
`under the selection state are in the floating state because
`both the corresponding reset MOSFET and capaci-
`tance cut MOSFET are OFF. However, since the time
`in which CMOS static RAM is under the selection state
`is short, the corresponding word line keeps the non-
`selection state due to the high level charge built up in
`the gate capacitance of MOSFETs le and Qd2 of
`each word line drive circuit.
`As described above,
`in the X address decoder of
`CMOS static RAM of this embodiment, capacitance cut
`MOSFETs for receiving the selection signals <i>0~¢i>x3 '
`of the pre-decoder PDCR are disposed between the
`decoding NAND gate circuits and the four sets of word
`line drive circuits corresponding thereto. Moreover,
`reset MOSFETs for receiving the timing signal 4>ce
`(selection control signal) are disposed between the input
`terminal of each word line drive circuit and the power
`source voltage Vcc of the circuit. Accordingly, the load
`to the output signal of the pre-decoder PDCR, that is,
`the load to the selection signal ¢x0~4>x3, is only the
`capacitance cut MOSFET having a relatively small
`conductance, while the load to the output signal of each
`decoding NAND gate cir__cuit,__that is, the load to the
`inversed selection signal SO~Sk, is only one word line
`drive circuit connected through a corresponding capac-
`itance cut MOSFET. In other words, the loads to the
`output signals of the predecoder PDCR and decoding
`NAND gate circuit are not much affected, even though
`a relatively large parasitic capacitance is connected to
`each word line of the memory array M-ARY and the
`side of MOSFETs le and Qd2 constituting the word
`line drive circuit is relatively large due to the large
`memory capacity of CMOS static RAM. Therefore, the
`selection operation of the X address decoder XDCR is
`sped up and memory access of the CMOS static RAM
`is sped up, too.
`Embodiment 2
`FIG. 2 shows the circuit diagram of the X address
`decoder XDCR of a CMOS static RAM in accordance
`with the second embodiment of the present invention.
`The drawing illustrates partially the NAND gate circuit
`NAGD, the word line drive circuits WDO~Wd3 and
`associated circuits of the X address decoder XDCR.
`Therefore, refer to the circuits described in the first
`embodiment for the detail of the circuits which are not
`shown. Furthermore, among the circuits shown in the
`
`8
`drawing, the construction and operation of the same
`circuit portions as those of the first embodiment will not
`be explained.
`the X address decoder XDCR of the
`In FIG. 2,
`CMOS static RAM of this embodiment includes one
`pre-decoder PDCR and k+1 decoding NAND gate
`circuits NAGO~NAGk in the same way as in the first
`embodiment described already. The word line drive
`circuits WDO~WDm are disposed in such a manner as
`to correspond to the word lines W0~Wm of the mem-
`ory array M-ARY.
`In the X address decoder XDCR of this embodiment,
`N-channel capacitance cut MOSFETs Q17~Q18 for
`receiving the corresponding selection signals ¢x0~¢x3
`at their gates from the pre-decoder PDCR are disposed
`between the decoding NAND gate circuit NAGO and
`the corresponding four sets of word line drive circuits
`WDO~Wd3. These selection signals ¢x0~¢x3 are
`generated in accordance with the same logic condition
`as that of the first embodiment.
`P-channel reset MOSFETs Q27 ~ Q28 are juxtaposed
`with the capacitance cut MOSFETs Q17 ~ Q18, respec-
`tively. The gates of these reset MOSFETS‘Q27~Q28
`are connected in common and receive the afore—men-
`tioned timing signal (tee from the timing control circuit
`TC.
`
`The pre-decoder PDCR, the decoding NAND gate
`NAGO, the word line drive circuits WDO~WD3 and
`the capacitance cut MOSFETs Q17~Q18 perform the
`same selection operation as that of the first embodiment
`and bring one word line designated by the X address
`signal AXO~Axi to the high level selection state.
`The reset MOSFETs Q27~Q28 are turned ON to-
`gether when the CMOS static RAM is under the non-
`selection state and the timing signal (,bce is at the low
`logic level. In this instance, the input terminal of each
`word line drive circuit WDO~WD3 is connected to the
`output terminal of the corresponding NAND gate cir-
`cuit NAGO through the corresponding reset MOSFET
`Q27~Q28. As described already, P-channel MOSFET
`le for receiving the timing signal (bee at its gate is
`disposed between the output terminal of the NAND
`gate circuit NAGO and the power source voltage of the
`circuit. This MOSFET le is turned ON together with
`reset MOSFETs Q27~Q28 when the CMOS static
`RAM is under the non-selection state and the timing
`signal (tee is at the low logic level. Therefore, the input
`terminal of each word line drive circuit is fixed to the
`high logic level by the power source voltage Vcc of the
`circuit which is supplied through this MOSFET le
`and the corresponding reset MOSFET. Since the input
`terminal of each word line drive circuit is at the high
`logic level,
`its output signal,
`that is,
`the word line
`W0~Wm, is fixed to the low level non-selection state.
`On the other hand, when this CMOS static RAM is
`under the selection state and the timing signal dice is at
`the high logic level, all the reset MOSFETs Q27~Q28
`are turned OFF, so that the corresponding selection
`signal ¢x0~¢x3 of the pre-decoder PDCR rises to the
`high logic level and the inversed selection signal the
`corresponding NAND circuit is transmitted to only the
`word line drive circuit whose corresponding capaci-
`tance cut MOSFET is turned ON. When the corre-
`sponding selection signal ¢x0~¢>x3 of the pre-decoder
`PDCR is at the low logic level, reset MOSFETs and
`capacitance cut MOSFETs are turned OFF simulta-
`neously and the level of the input terminal of the corre-
`sponding word line drive circuit is in the floating state.
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`However, in the same way as in the first embodiment,
`since the time in which the CMOS static RAM is under
`the selection state is short, the corresponding word line
`keeps the low level non-selection state due to the high
`level charge which is built up in the gate capacitance of
`MOSFETs le and Qd2 of each word line drive cir-
`cult.
`
`As described above, capacitance cut MOSFETs for
`receiving the selection signals ¢x0~¢x3 of the pre-
`decoder PDCR are disposed between the decoding
`NAND gate circuits and the corresponding four sets of
`word line drive circuits in the X address decoder
`XDCR of CMOS static RAM of this embodiment.
`Reset MOSFETS for receiving the timing signal (pee
`(selection control signal) at their gates are disposed for
`these capacitance cut MOSFETs, respectively. Ac-
`cordingly, in the same way as in the first embodiment,
`the load to the output signal of the pre-decoder PDCR,
`that is, the load to the selection signal ¢x0~ ¢x3, is only
`the capacitance cut MOSFET having a relatively small
`conductance and the load to the output signal of each
`decoding NAND gate cir_cuit_,_that is, the load to the
`inversed selection signal SO~Sk, is only one word line
`drive circuit connected through the capacitance cut
`MOSFET. Therefore, even though the CMOS static
`RAM has a large memory capacity, the selection opera-
`tion of the X address decoder XDCR is sped up and the
`memory access of CMOS static RAM is sped up, as
`well.
`Embodiment 3
`FIG. 3 shows the circuit diagram of the X address
`decoder XCDR of the CMOS static RAM in accor-
`dance with the third embodiment of the present inven-
`tion. The drawing shows only the NAND gate circuit
`NAGO, the word line drive circuits WDO and associ-
`ated circuits of the X address decoder XDCR in the
`same way as in the second embodiment. Refer to the
`circuits shown in the first and second embodiments for
`the detail of those circuit portions which are not shown
`in the drawing. Furthermore, the explanation of the
`construction and operation of the same circuit portions
`as those of the first and second embodiments will be
`omitted.
`the X address decoder XDCR of the
`In FIG. 3,
`CMOS static RAM of this embodiment includes one
`pre-decoder PDCR and k+1 decoding NAND gate
`circuits NAGO~NAGk in the same way as in the fore-
`going
`embodiments. Word
`line
`drive
`circuits
`WD~WDm are also disposed in such a manner as to
`correspond to the word lines W0~Wm of the memory
`array M-ARY, respectively.
`In the X address decoder XDCR of this embodiment,
`the afore-mentioned timing signal ¢ce (selection con-
`trol signal) is supplied to the pre-decoder PDCR. Ac-
`cordingly, the CMOS static RAM is brought into the
`selection state and the timing signal qbce is set to the
`high logic level so that the output signal of the pre-
`decoder PDCR, that is, the selection signal d>x0~d>x3,
`is set selectively to the high logic level.
`N-channel capacitance cut MOSFETs Q19~Q20 for
`receiving the corresponding selection signals ¢x0~¢x3
`from the pre—decoder PDCR at their gates are dispose