(12) Unlted States Patent
`(10) Patent No.:
`US 7,693,002 B2
`
`Lin
`(45) Date of Patent:
`Apr. 6, 2010
`
`USOO7693002B2
`
`(54) DYNAMIC WORD LINE DRIVERS AND
`DECODERS FOR MEMORYARRAYS
`
`(75)
`
`Inventor:
`
`Jentsung Lin, Cardifi‘by the Sea, CA
`(US)
`
`(73) Assignee: QUALCOMM Incorporated, San
`Diego, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 3 5
`U.S.C. 15403) by 0 days.
`.
`..
`,
`Appl No . 11/548 132
`
`Filed:
`
`Oct. 10, 2006
`
`Prior Publication Data
`
`US 2008/0084778 A1
`
`Apr. 10, 2008
`
`
`
`Int. Cl.
`(200601)
`G11C 11/00
`(52 US. Cl.
`............................... 365/230.06; 365/233.5
`(58
`Field Of Classification Search ............ 365/230.06,
`365/233
`See application file for complete search history.
`References Cited
`
`(21
`
`(22
`
`(65
`
`(51
`
`(56
`
`
`US. PATENT DOCUMENTS
`
`9/1991 Nakano et al' """"" 365/230'06
`5’051’959 A *
`........ 365/210
`l/l997 Passow et al.
`5,596,539 A *
`
`
`2/1997 Sugio ..........
`365/230.06
`5,602,796 A *
`
`........ 711/167
`5,826,056 A * 10/1998 Noda
`
`100
`
`\
`
`120
`
`6,856,574 B2 *
`7,047,385 131*
`7,092,305 B2
`
`............ 365/233
`2/2005 Iwahashi 6161.
`5/2006 Bhattacharya et 61.
`...... 711/169
`8/2006 Watanabe et al.
`
`.................. 365/201
`8/2001 Kato et a1.
`2001/0015926 A1*
`3/2003 Hatakenaka et a1.
`........ 714/763
`2003/0046632 A1*
`9/2004 Watanabe et a1.
`........... 365/191
`2004/0190352 A1*
`12/2004 Ha
`2004/0246806 A1
`3/2005 Cho
`2005/0052904 A1
`OTHER PUBLICATIONS
`
`- PCT/USO7/080993 - International
`International Search Report
`Search Authority - European Patent Office - May 14, 2008.
`Written Opinion - PCT/USO7/O80993 - International Search Author-
`
`ity - European Patent Office - May 14, 2008.
`* cited by examiner
`
`Primary ExamineriMichael T Tran
`(74) Attorney, Agent, or FirmiNicholas J. Pauley; Peter
`Kamarchik; Sam Talpalatsky
`
`ABSTRACT
`(57)
`In a particular illustrative embodiment, a circuit device that
`includes first logic and second logic is disclosed. The first
`logic receives a clock signal and a first portion ofa memory
`address of a memory array, decodes the first portion of the
`memory address, and selectively applies the clock signal to a
`selected group of wordline .drivers associated with the
`memory array. The second log1c decodes a second portlon of
`the memory address and selectively activates a particular
`wordline driver of the selected group of wordline drivers
`according to the second portion of the memory address.
`
`38 Claims, 5 Drawing Sheets
`
`
`
`,
`
`,
`
`Partially Decoded
`Address (0)
`I
`
`II
`
`'
`
`26
`.
`' K 128
`I
`K—
`. Clk<3:0>
`130
`I
`K—
`.
`'
`I
`I
`I
`
`
`
`,
`
`
`
`(
`
`eco e
`Bl“ la y
`d d
`P 1'
`II D
`Address (15)
`108
`122
`\)
`.1
`,
`,.
`0
`Clk<3.0>
`Conditional clock
`4t 16
`
`
`
`Decoder
`110/— generator
`4
`2 to 4
`
`
`112/ Decoder
`
`1 14
`
`Address<5:2>
`
`1 16
`Address<1:0>
`
`Clock
`
`1 1
`
`8
`
`1
`
`APPLE 1001
`
`[132 {102
`104\
`Group of L0)»
`\ 7 Wordline MDriver
`—>W'-<2>
`WL<3>I
`
`
`
`(
`24
`
`)
`
`WL<0'3>
`'
`I
`I
`:
`'
`I
`I
`I
`.
`'
`I
`I
`I
`
`106\'
`Prohiri Group Of WL<6 >
`F: * Wordline M1;
`,
`WL<60263> WL<6 >
`'
`Driver W362;
`)
`j
`134
`
`MEMORY
`ARRAY
`
`
`
`
`
`APPLE 1001
`
`1
`
`

`

`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 1 0f5
`
`US 7,693,002 B2
`
`100
`
`\V
`
`132
`102
`
`
`Wordline
`
`120
`
`.
`Partially Decoded
`Address (0)
`
`Driver
`(WL<O:3>)
`
`Clk<3:0>
`
`MEMORY
`ARRAY
`
`Address (15) )
`
`
`
`
`
`/-
`
`
`106
`
`Group of
`Wordline
`
`Driver
`(WL<60:63>)
`
`
`Partially Decoded
`
`generator
`
`Conditional clock
`
`“Clk<3:0>”
`
`110
`
`114
`
`Add ress<5:2>
`
`Add ress<1 :0>
`
`Clock
`
`FIG. 1
`
`2
`
`

`

`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 2 0f5
`
`US 7,693,002 B2
`
`132
`
`v/B
`
`102
`
`(200
`
`206
`
`208
`
`FIG. 2
`
`3
`
`

`

`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 3 0f5
`
`US 7,693,002 B2
`
`318
`
`202
`
`VVL<0>
`
`338
`
`204
`
`VVL<1>
`
`358
`
`206
`
`VVL<2>
`
`378
`
`208
`
`VVL<3>
`
`
`
`302
`
`120
`
`Address
`
`CLK<2>
`
`CLK<0>
`
`CLK<3>
`
`CLK<1>
`
`FIG. 3
`
`4
`
`

`

`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 4 0f5
`
`US 7,693,002 B2
`
`FIG.4
`
`384
`
`400
`
`5
`
`

`

`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 5 0f5
`
`US 7,693,002 B2
`
`
`
`RECEIVE AT A PARTIALLY DECODED MEMORY ADDRESS AT A
`
`
`WORDLINE DRIVER OF A MEMORY ARRAY
`
`
`
`\500
`
`
`
`
`
`SELECTIVELY PROVIDE A CLOCK SIGNAL TO A SELECTED
`
`GROUP OF WORDLINE DRIVERS OF A PLURALITY OF
`
`WORDLINE DRIVERS BASED ON A FIRST PORTION OF THE
`
`MEMORY ADDRESS OF THE MEMORY ARRAY, WHERE EACH \
`WORDLINE DRIVER OF THE PLURALITY OF WORDLINE
`DRIVERS IS ASSOCIATED WITH A WORDLINE OF THE MEMORY
`
`ARRAY
`
`
`I
`ACTIVATE A PARTICULAR WORDLINE DRIVER OF THE
`
`SELECTED GROUP OF WORDLINE DRIVERS ACCORDING TO A \
`SECOND PORTION OF THE MEMORY ADDRESS
`
`
`502
`
`504
`
`505
`
`I
`HOLD UNSELECTED WORDLINE DRIVERS OF THE SELECTED
`
`GROUP OF WORDLINE DRIVERS IN AN INACTIVE PRECHARGE \
`STATE
`
`
`FIG. 5
`
`6
`
`

`

`US 7,693,002 B2
`
`1
`DYNAMIC WORD LINE DRIVERS AND
`DECODERS FOR MEMORY ARRAYS
`
`BACKGROUND
`
`I. Field
`
`The present disclosure generally relates to memory arrays,
`and more particularly,
`to dynamic wordline drivers and
`decoders for memory arrays.
`II. Description of RelatedArt
`In general, memory systems with a traditional dynamic/
`static circuit structure may place a heavy load on the clock.
`For example, in a memory structure having a plurality of
`wordline drivers, a single clock may drive multiple drivers
`and multiple address decoders, placing a large electrical load
`on the clock.
`
`Additionally, each wordline driver may have its own
`decoded address input, which may place a large load on the
`decoder and which may utilize a large area of the circuit
`substrate, increasing complexity and power consumption.
`Moreover, when the clock signal is provided to multiple
`wordline drivers, capacitive noise coupling between the
`wordline driver outputs may introduce additional design
`complexities. Hence, there is a need for improved wordline
`drivers.
`
`SUMMARY
`
`In a particular illustrative embodiment, a circuit device that
`includes first logic and second logic is disclosed. The first
`logic receives a clock signal and a first portion of a memory
`address of a memory array, decodes the first portion of the
`memory address, and selectively applies the clock signal to a
`selected group of wordline drivers associated with the
`memory array. The second logic decodes a second portion of
`the memory address and selectively activates a particular
`wordline driver of the selected group of wordline drivers
`according to the second portion of the memory address.
`In another particular embodiment, a method of selecting a
`particular wordline of a memory array is disclosed. The
`method includes selectively providing a clock signal to a
`selected group of wordline drivers of a plurality of wordline
`drivers based on a first portion of a memory address of the
`memory array. Each wordline driver is associated with a
`wordline of the memory array. The method further includes
`activating a particular wordline driver ofthe selected group of
`wordline drivers according to a second portion ofthe memory
`address.
`
`In another particular embodiment, an integrated circuit
`includes a substrate and a plurality of circuit devices. The
`circuit devices are arranged on the substrate to reduce capaci-
`tive coupling noise. The plurality of circuit devices includes a
`first wordline driver having a first pair oftransistors and a first
`wordline output and includes a second wordline driver having
`a second pair oftransistors and a second wordline output. The
`first and second wordline drivers are disposed on the substrate
`in a single row. A first wire trace couples the first pair of
`transistors to the first wordline output. The second wire trace
`couples the second pair of transistors to the second wordline
`output. The first wire trace and the second wire trace are
`substantially parallel. An advantage of this embodiment is
`that the layout provides increased capacitive noise-coupling
`immunity.
`illustrative
`One particular advantage of a particular
`embodiment of the circuit device is that a timing delay from
`a clock to a particular wordline is reduced. Still another par-
`ticular advantage of a particular illustrative embodiment of
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`the circuit device is that the clock driver’ s capacitance loading
`may also be reduced. Another particular advantage of a par-
`ticular illustrative embodiment is that use of multiple condi-
`tional clocks to selectively apply a clock signal reduces power
`consumption. In a particular embodiment, the clock power
`consumption may be reduced to one-fourth of the power
`consumed by a single clock system (e.g. the power consump-
`tion of a clock generator may be reduced by 75%). This
`reduction in power consumption provides an additional
`advantage in that power is conserved for use in other pro-
`cesses and/or to extend an operational life of a power source,
`such as a battery.
`Still another particular advantage of a particular illustrative
`embodiment may be realized by sharing a common address
`signal among multiple wordline decoders, which reduces
`power consumption and conserves layout area. In a particular
`embodiment, four wordline drivers may share a common
`address signal, which reduces transistor gate loading of the
`decoders without decreasing speed.
`Other aspects, advantages, and features of the present dis-
`closure will become apparent after review of the entire appli-
`cation, including the following sections: Brief Description of
`the Drawings, Detailed Description, and the Claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The aspects and the attendant advantages of the embodi-
`ments described herein will become more readily apparent by
`reference to the following detailed description when taken in
`conjunction with the accompanying drawings wherein:
`FIG. 1 is a block diagram of a particular illustrative
`embodiment of a wordline driver system including a plurality
`of groups of wordline drivers associated with a memory
`array;
`FIG. 2 is a circuit diagram of a particular illustrative
`embodiment of a portion of a memory array, such as the
`memory array of FIG. 1;
`FIG. 3 is a circuit diagram of a particular illustrative
`embodiment of a group ofwordline drivers, such as a selected
`group of wordline drivers of the plurality of groups of word-
`line drivers in FIG. 1;
`FIG. 4 is a block diagram of a particular illustrative
`embodiment of a layout on a circuit substrate including a
`group of wordline drivers, such as the group of wordline
`drivers of FIG. 3; and
`FIG. 5 is a flow diagram of a particular illustrative embodi-
`ment of a method of selectively activating a wordline of a
`group of wordline drivers, such as the group of wordline
`drivers of FIG. 4.
`
`DETAILED DESCRIPTION
`
`FIG. 1 is a block diagram of a particular illustrative
`embodiment of a wordline driver system 100 including a set
`of wordline drivers, such as the groups of wordline drivers
`104 and 106 that are associated with a memory array 102. The
`system 100 may include multiple additional sets of wordline
`drivers (not shown). Each set ofwordline drivers may control
`up to sixty—four wordlines (numbered zero to sixty—three)
`using sixty-four corresponding wordline drivers. The set of
`sixty-four wordlines and corresponding wordline drivers may
`be divided into groups ofwordline drivers, such as the groups
`of wordline drivers 104 and 106. In a particular embodiment,
`the group of wordline drivers 104 may drive wordlines, such
`as the wordlines 132 from zero to three (WL<0>, WL<1>,
`WL<2>, and WL<3 >), and the group of wordline drivers 106
`may control wordlines, such as the wordlines 134 from sixty
`
`7
`
`

`

`US 7,693,002 B2
`
`3
`to sixty-three (WL<60>, WL<61>, WL<62>, and WL<63>).
`In this instance, each of the groups of wordline drivers 104
`and 106 control four wordlines, and the set of wordline driv-
`ers may include sixteen groups. For clarity, only the two
`illustrative groups of wordline drivers 104 and 106 are shown
`and other groups associated with wordlines of the memory
`array 102 (such as wordline drivers that control the wordlines
`from four through fifty-nine) are omitted.
`The system 100 may also include a four-to-sixteen bit
`memory address decoder 108, a conditional clock generator
`110, a two-to-four bit memory address decoder 112, address
`inputs 114 and 116, and a clock input 118. The system 100
`may also include partially decoded address lines 120 and 122,
`conditional clock outputs 124, 126, 128 and 130, and a group
`ofwordline driver outputs 132 and 134. The conditional clock
`outputs 124, 126, 128, and 130 are also inputs to the groups of
`wordline drivers 104 and 106.
`
`In a particular embodiment, a six-bit memory address
`specifying one of sixty-four wordlines in the memory array
`102 is received. The two-to-four bit memory address decoder
`112 may decode a first portion of the six-bit memory address
`(such as bits zero and one) via the address input 116, and the
`four-to-sixteen bit memory address decoder 108 may decode
`the remainder (i.e. a second portion) of the six-bit memory
`address (such as bits two to five) via the address input 114.
`The two-to-four bit decoder 112 may decode the first portion
`of the memory address and may provide the decoded portion
`to the conditional clock generator 110. The conditional clock
`generator 110 receives a clock signal via the clock input 118
`and selectively applies the clock signal to a selected one ofthe
`clock outputs 124, 126, 128 and 130. In general, each clock
`output 124, 126, 128 and 130 is coupled to each ofthe groups
`of wordline drivers 104 and 106 of the particular group of
`wordline drivers. In a particular embodiment, the conditional
`clock generator 110 may derive the clock outputs 124, 126,
`128 and 130 from a single clock.
`The four-to-sixteen bit memory address decoder 108
`decodes the remainder of the six-bit memory address (e.g.
`bits two to five) and applies a partial address input to the
`wordlines that are related to the decoded memory address.
`For example, the decoded four bits of the partially decoded
`address may be applied to the partially decoded address line
`(0) 120 to enable the group of wordline drivers 104 to enable
`one of the four wordlines (WL<0:3>) 132 to access data
`stored in the memory array 102.
`In general, each group of wordline drivers, such as the
`group of wordline drivers 104 may share a common partially
`decoded address input, such as the partially decoded address
`line (0) 120 for the group of wordline drivers 104, reducing
`layout area usage and layout complexity. Additionally, the
`common address input reduces input gate capacitance load-
`ing without introducing timing delays. In general, the clock
`outputs 124, 126, 128, and 130 determine whether a device is
`in a dynamic evaluation state (e. g., an active evaluation state
`where a clock signal is applied) or in a static precharge state
`(e. g., a fixed voltage level, such a voltage high signal, is
`applied). Since only one of the four clock outputs 124, 126,
`128 and 130 may be active at a time, only one of the four
`wordline drivers ofthe group ofwordline drivers 104 is in the
`dynamic evaluation state (e.g. a clock signal is present), while
`the other three remain in a static precharge state (such as a
`logic high state). If the four-to-sixteen memory address
`decoder 108 decodes a portion (e.g. bits two to five) of the
`memory address to determine a set of wordlines from zero to
`three (WL<0>, WL<1>, WL<2> and WL<3> in FIG. 1), the
`four-to-sixteen bit memory address decoder 108 applies a
`signal to the address line 120. The dynamic evaluation state of
`
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`a clock output, such as the clock 124, activates a particular
`wordline of the group of wordline drivers 104, such as word-
`line Zero (WL<0>) of the memory array 102. In general, the
`decoded output of the two-to-four decoder 112 with clock
`generator 110 and the decoded output of the four-to-sixteen
`bit memory address decoder 108 may be utilized via a logical
`AND operation to selectively activate a wordline driver of the
`group of wordline drivers 104, for example.
`FIG. 2 is a circuit diagram of a particular illustrative
`embodiment of a portion 200 of a memory array, such as a
`portion ofthe memory array 102 ofFIG. 1. The portion 200 of
`the memory array 102 includes wordlines 202, 204, 206, and
`208 and bit lines 210 and 212. The portion 200 ofthe memory
`array 102 further includes transistors 214 and 216 and cross-
`coupled inverters 218 and 220 associated with the wordline
`202. Additionally, the portion 200 of the memory array 102
`may include transistors 222 and 224 and cross-coupled
`inverters 226 and 228 associated with the wordline 204. The
`
`portion 200 of the memory array 102 may further include
`transistors 230 and 232 and cross-coupled inverters 234 and
`236 associated with the wordline 206. The portion 200 of the
`memory array 102 also includes transistors 238 and 240 and
`cross-coupled inverters 242 and 244 associated with the
`wordline 208. In a particular embodiment, the wordlines 202,
`204, 206 and 208 may correspond to the wordlines 132 of the
`group wordline drivers 104 of FIG. 1.
`In operation, when a particular wordline, such as the word-
`line 202 is charged, the other wordlines 204, 206 and 208 are
`held at a logic low level. The charged wordline 202 activates
`the transistors 214 and 216, which apply a differential voltage
`to the bit lines 210 and 212. The differential voltage is related
`to a bit stored by the cross-coupled inverters 242 and 244,
`which operates as a data latch to store a bit value. A sense
`amplifier or a differential amplifier (not shown) may be
`coupled to the bit lines 210 and 212 to detect a differential
`voltage and to output a value related to a value ofthe stored bit
`associated with the wordline 202.
`
`FIG. 3 is a circuit diagram of a particular illustrative
`embodiment of a group ofwordline drivers, such as the group
`of wordline drivers 104 in FIG. 1. The group of wordline
`drivers 104 includes an address input 120, clock outputs 124,
`126, 128 and 130, an inverter 302, a shared address line 304,
`and wordline drivers 306, 308, 310 and 312.
`The wordline driver 306 includes a first transistor (Mp0)
`314, a second transistor (M10) 316, and an output driver 318,
`including a transistor 320 and an inverter C(WLO) 322 that
`are coupled to the first and second transistors 314 and 316 via
`a data line (ddh0) 324. The transistor 320 holds the data from
`device leakage. The inverter 322 is also coupled to the word-
`line (WL<0>) 202. The first transistor 314 includes a first
`terminal 326 coupled to a power terminal, a control terminal
`328 coupled to the clock 130, and a second terminal coupled
`to the data line (ddh0) 324. The second transistor 316 includes
`a first terminal coupled to the data line (ddh0) 324, a control
`terminal 330 coupled to the clock 130, and a second terminal
`332 coupled to the shared address line 304.
`The wordline driver 308 includes a first transistor (Mp1)
`334, a second transistor (Mnl) 336, and an output driver 338,
`including a transistor 340 to hold the data from device leakage
`and including an inverter (XWLl) 342 that are coupled to the
`first and second transistors 334 and 336 via a data line (ddh1)
`344. The inverter 342 is also coupled to the wordline
`(WL<1>) 204. The first transistor 334 includes a first terminal
`346 coupled to a power terminal, a control terminal 348
`coupled to the clock 128, and a second terminal coupled to the
`data line (ddh1) 344. The second transistor 336 includes a first
`terminal coupled to the data line (ddhl) 344, a control termi-
`
`8
`
`

`

`US 7,693,002 B2
`
`5
`nal 350 coupled to the clock 128, and a second terminal 352
`coupled to the shared address line 304.
`The wordline driver 310 includes a first transistor (Mp2)
`354, a second transistor (Mn2) 356, and an output driver 358,
`including a transistor 360 to hold the data from device leakage
`and including an inverter (XWL2) 362 that are coupled to the
`first and second transistors 354 and 356 via a data line (ddh2)
`364. The inverter 362 is also coupled to the wordline
`(WL<2>) 206. The first transistor 354 includes a first terminal
`366 coupled to a power terminal, a control terminal 368
`coupled to the clock 126, and a second terminal coupled to the
`data line (ddh2) 364. The second transistor 356 includes a first
`terminal coupled to the data line 364, a control terminal 370
`coupled to the clock 126, and a second terminal 372 coupled
`to the shared address line 304.
`
`The wordline driver 312 includes a first transistor (Mp3)
`374, a second transistor (Mn3) 376, and an output driver 378,
`including a transistor 380 to hold the data from device leakage
`and including an inverter (XWL3) 382 that are coupled to the
`first and second transistors 374 and 376 via a data line (ddh3)
`384. The inverter 382 is also coupled to the wordline
`(WL<3>) 208. The first transistor 374 includes a first terminal
`386 coupled to a power terminal, a control terminal 388
`coupled to the clock 124, and a second terminal coupled to the
`data line (ddh3) 384. The second transistor 376 includes a first
`terminal coupled to the data line 384, a control terminal 390
`coupled to the clock 124, and a second terminal 392 coupled
`to the shared address line 304.
`
`In a particular embodiment, an address is received via the
`address input 120 and inverted by the inverter 302 to provide
`a shared address input 304. As previously disclosed, a condi-
`tional clock generator, such as the conditional clock generator
`110 ofFIG. 1, applies a clock signal to a selected clock output,
`such as the clock output 130. The clock signal applied to the
`clock output 130 selectively activates the wordline driver 306
`to access data of a memory array (such as the memory array
`102 in FIG. 1) via the selected wordline 202. By applying the
`clock signal only to the selected clock output 130, power
`consumption is reduced, since the clock only drives a single
`line of a group of wordline drivers, as opposed to driving all
`of the wordline drivers. In a particular embodiment, since
`only one of the four clock outputs 124, 126, 128 and 130 is
`active at any given time, the power consumed by the clock
`may be reduced by 75% over a single clock system.
`By sharing a common address 304 among multiple word-
`line drivers (decoders) 306, 308, 310, and 312, power con-
`sumption of the overall wordline driver circuitry may be
`reduced. Additionally, the layout area of the wordline drivers
`and layout complexity of the circuit design may be reduced.
`Further, the shared address input reduces transistor gate load-
`ing (e.g. control terminals 328, 330, 348, 350, 368, 370, 388,
`and 390) ofthe wordline drivers (decoders) 306, 308, 310 and
`312 without decreasing the performance of the circuit.
`In a particular illustrative embodiment, a conditional clock
`generator, such as the conditional clock generator 110 in FIG.
`1, applies the clock signal to a selected clock output, such as
`the clock output 126. The other clocks 124, 128 and 130 may
`be held at a ground voltage level. The transistors 3 14, 334, and
`374 are p—channel transistors, which are activated by a logic
`low signal. Thus, when the clocks 124, 128 and 130 are at a
`logic low level, the p-channel transistors 314, 334 and 374 are
`active, and the data lines 324, 344 and 384 are at a logic high
`level, placing a logic low voltage on the wordlines 202, 204
`and 208, due to the inverters 322, 362 and 382.
`The clock 126 deactivates the p-channel transistor (Mp2)
`354 and activates the n-channel transistor (Mn2) 356. The
`address 120 is inverted by the inverter 302 and applied to the
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`address line 304, which is coupled to the source ofthe n-chan-
`nel transistor 356. The inverted address appears on the data
`line (ddh2) 364 and is inverted again by the inverter (XWL2)
`362, coupling the address 120 to the wordline (WL<2>) 206.
`The clock 126 activates the desired wordline 206, while caus-
`ing the other wordlines 202, 204 and 208 to be held at a logic
`low level. Thus, only the desired wordline 206 is active at any
`given time. The conditional clock generator, such as the con-
`ditional clock generator 110 in FIG. 1, applies the clock signal
`to only one ofthe four clocks 124, 126, 128 and 130, reducing
`power consumption by 75%.
`In general, other conditional clock generator implementa-
`tions may be used. For example, in a particular embodiment,
`a three-bit portion of the address 120 may be decoded and
`may be applied by the conditional clock generator to selec-
`tively apply a clock signal to one of eight lines, reducing
`power consumption by approximately 87.5%. Thus, the par-
`ticular arrangement may allow for further reductions in power
`consumption.
`FIG. 4 is a block diagram of a particular illustrative
`embodiment of a circuit layout 400 of a circuit substrate
`including a group of wordline drivers, such as wordline driv-
`ers 306, 308, 310 and 312 of FIG. 3. In general, the elements
`of the wordline drivers 306, 308, 310 and 312 are depicted as
`rectangular regions on the substrate. It should be understood
`that transistors and other circuit components may be formed
`within such regions and may be sized to match the memory
`cell’s height, such as a height between wordlines 202 and 208
`in FIG. 2. For the purpose of the discussion, the regions are
`identified by the particular circuit components of FIG. 3 that
`may be formed within the particular region.
`The circuit layout 400 includes the first transistor (Mp0)
`314, the second transistor (Mn0) 316, and the output driver
`C(WLO) 318 of the wordline driver 306 in FIG. 3. The circuit
`layout 400 also includes the first transistor (Mp1) 334, the
`second transistor (Mn1) 336, and the output driver (XWLI)
`338 of the wordline driver 308 in FIG. 3. The circuit layout
`400 may also include the first transistor (Mp2) 354, the sec-
`ond transistor (Mn2) 356, and the output driver C(WL2) 358
`of the wordline driver 310 in FIG. 3. Additionally, the circuit
`layout 400 may include the first transistor (Mp3) 374, the
`second transistor (Mn3) 376, and the output driver (XWL3)
`378 of the wordline driver 312 in FIG. 3.
`
`In general, a first row 402 includes the transistor (Mn0)
`316, the transistor (Mn1) 336, the transistor (Mp0) 314, the
`transistor (Mp1) 334, the output driver (XWLO) 318, and the
`output driver (XWLl) 338. A second row 404 includes the
`transistor (Mn2) 356, the transistor (Mn3) 376, the transistor
`(Mp2) 354,
`the transistor (Mp3) 374,
`the output driver
`C(WL2) 358, and the output driver (XWL3) 378. The first
`row 402 and the second row 404 are substantially parallel.
`Additionally, the line (ddh0) 324, the line (ddh1) 344, the
`line (ddh2) 364 and the line (ddh3) 384 are substantially
`parallel to one another. The output driver (XWLO) 318 may
`include a first region (N) 406 and a second region (P) 408. The
`output driver (XWLl) 338 may include a first region (P) 410
`and a second region (N) 412. The output driver C(WL2) 358
`may include a first region (N) 414 and a second region (P)
`416. The output driver (XWL3) 378 may include a first region
`(P) 418 and a second region (N) 420. In general, the regions
`408, 410, 416 and 418 may be utilized to form a transistor,
`such as the pull up transistors 320, 340, 360, and 380 in FIG.
`3. The regions 406, 412, 414, and 420 may cooperate with the
`regions 408, 410, 416 and 418 to form the inverters 322, 342,
`362, and 382 of FIG. 3.
`By arranging the layout 400 of the wordline drivers 306,
`308, 310 and 312 on the substrate as shown, capacitive noise-
`
`9
`
`

`

`US 7,693,002 B2
`
`7
`coupling immunity ofthe structure is improved. In particular,
`if the same clock signal is applied to each of the wordline
`drivers, any ofthe wire traces 324, 344, 364, and 384 and the
`corresponding circuit devices may be active. In such an
`instance, there may be undesired cross-coupling between the
`wire traces, such that a signal applied to one trace may expe-
`rience inductive function error and power loss caused by
`capacitive coupling between the wire traces. However, a con-
`ditional clock, such as the conditional clock 110 in FIG. 1,
`activates only one wire trace and one corresponding set of
`structures at any given time. The exclusive nature of the
`application of a signal to the traces ensures that only one of
`the four wordline drivers 306, 308, 310 and 312 are in a
`dynamic evaluation state at any given time, and that the other
`wordline drivers are in a static “precharge” state. The particu-
`lar arrangement places data line (ddh0) 314 and the wordline
`output 202 adjacent to the data line (dth) 334. The data line
`(ddh0) 314 and its associated wordline output 202 are
`inverted with respect to each other. Thus, a voltage applied to
`the data line (ddh0) 314 is inverted at the wordline 202. While
`the data line (ddh1) 334 might ordinarily experience capaci-
`
`8
`(ddh2) 364, and the line (ddh3) 384 are in a static precharge
`state. The line (dth) 344 is closest in proximity to the line
`(ddh0) 324, so the line (ddh0) 324 and wordline (WL<0>)
`202 may be aggressors relative to the line (ddh1) 344. When
`a voltage on the line (ddh0) 324 is decreasing, the wordline
`(WL<0>) 202 is rising. The rising voltage at the wordline 202
`is cross-coupled with the line (dth) 344, helping to offset or
`cancel coupling between the line (ddh1) 344 and the line
`(ddh0). The lines (ddhl, ddh2, and ddh3) 344, 364, and 384
`are statically held by the transistors (Mp1, Mp2, and Mp3)
`334, 354, and 374, respectively. The wordlines (WL<1>,
`WL<2>, and WL<3>) 204, 206, and 208 are statically
`inverted relative to the lines (ddh1, ddh2, and ddh3) 344, 364,
`and 384, respectively. Thus, the layout 400 contributes to the
`robustness of the circuit design, by reducing capacitive noise
`coupling between the wordline drivers 306, 308, 310, and
`312.
`
`5
`
`10
`
`15
`
`20
`
`Table 1 below illustrates a relationship between the data
`lines (ddl10, ddhl, dth, and ddh3) 324, 344, 364, and 384
`that enhances capacitive noise immunity.
`
`Dynamic nodes
`
`Situation
`
`data line (ddh0)
`324
`
`data line (ddh l)
`344
`
`clk<0> 130 = active;
`dynamic
`evaluation
`state
`clk<l> 128 = 0;
`static
`precharged
`state
`
`TABLE 1
`
`Aggressor
`
`not applicable.
`
`Note:
`
`When the data line
`(ddh0) 324 is falling,
`the wordline
`(WL<0>) 202 is
`rising.
`
`The data ine (ddhl) is
`statically held by the clocked
`p-channe transistor (Mp1)
`334. The overlap ofthe
`rising wordline (WL<0>)
`202 assis s the data line
`(ddhl) 344 in resisting the
`capacitive coupling from
`(ddh0) 324 falling.
`The data ine (ddh2) is
`statically held by the clocked
`p-channe transistor (Mp2)
`354.
`The data ine (ddh3) is
`statically held by the clocked
`p-channe transistor (Mp3)
`374.
`
`
`
`data line (ddh2)
`364
`
`data line (ddh3)
`384
`
`clk<2> 126 = 0;
`static
`precharged
`state
`clk<3> 124 = 0;
`static
`precharged
`state
`
`110116.
`
`none.
`
`45
`
`50
`
`tive coupling with the data line (ddh0) 314, resulting in data
`errors and power loss, the opposite voltages of the data line
`(ddh0) 314 and the associated wordline 202 apply opposing
`capacitive influences on the adjacent data line (ddh1) 334,
`canceling capacitive noise coupling between the data lines
`(ddh0 and dth) 314 and 334, for example. The particular
`arrangement generally reduces capacitive noise coupling.
`For example, ifthe clock signal is selectively applied to the
`clock output 130 in FIG. 3, the line (ddh0) 324 is in a dynamic
`evaluation state. The line (wire trace) (dth) 344, the line
`
`In FIG. 4, the data line (ddh0) 324 and the wordline
`(WL<0>) 202 are adjacent to the data line (dth) 344, but are
`not adjacent to the other data lines (ddh2 and ddh3) 364 and
`384. Thus, only the data line (dth) 344 may be influenced by
`capacitive coupling with the data line (ddh0) 324.
`Table 2 below illustrates a relationship between the data
`lines (ddh0, ddh1, ddh2, and ddh3) 324, 344, 364, and 384
`that enhances capacitive noise immunity when more than one
`data line is adjacent to the data line that is in a dynamic
`evaluation state.
`
`TABLE 2
`
`Aggressor
`When the data line
`(ddhl) 344 is falling,
`the wordline
`(WL<1>) 204 is
`rising.
`
`Note:
`
`The data line (ddh0) is
`statically held by the clocked
`p-channel transistor (Mp0)
`314. The overlap ofthe
`rising wordline (WL<1>)
`204 assists the data line
`(ddh0) 324 in resisting the
`
`Dynamic nodes Situation
`
`data line (ddh0) clk<0> 130 = 0;
`324
`static
`precharged
`state
`
`10
`
`10
`
`

`

`US 7,693,002 B2
`
`10
`
`9 T
`
`ABLE 2-continued
`
`Dynamic nodes Situation
`
`Aggressor
`
`Note:
`
`data line (ddh1) clk<1> 128 = active;
`344
`dynaInic
`evaluation
`state
`data line (ddh2) clk<2> 126 = 0;
`3 64
`static
`precharged
`state
`
`Not applicable.
`
`When the data line
`(dth) 344 is falling,
`the wordline
`(WL<1>) 204 is
`rising.
`
`data line (ddh3) clk<3> 124 = 0;
`3 84
`static
`precharged
`state
`
`none.
`
`capacitive coupling from
`(ddh0) 344 falling.
`
`The data line (ddh2) is
`statically held by the clocked
`p-channel transistor (Mp2)
`354. The overlap ofthe
`rising wordline (WL<1>)
`204 assists the data line
`(ddh2) 364 in resisting the
`capacitive coupling from
`(ddh1) 344 falling.
`The data line (ddh3) is
`statically held by the clocked
`p-channel transistor (Mp3)
`374.
`
`In general, the data lines (ddhl and ddh3) 344 and