UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-01249
`Patent 7,693,002
`______________________
`
`DECLARATION OF DR. MASSOUD PEDRAM
`
`I, Massoud Pedram, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Qualcomm Incorporated
`
`(“Qualcomm” or “Patent Owner”) in the matter of the Inter Partes Review of U.S.
`
`Patent No. 7,693,002 (“the ’002 patent”).
`
`2.
`
`I am being compensated for my work in this matter at my standard
`
`hourly rate of $900 for consulting services. My compensation in no way depends
`
`on the outcome of this proceeding.
`
`3.
`
`In preparing this Declaration, I considered the following materials:
`
`a. The ’002 patent (Ex. 1001) and its file history (Ex. 1002);
`
`QUALCOMM EXHIBIT 2001
`Apple v. Qualcomm
`IPR2018-01249
`Page 1
`
`
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Apple Inc.
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-01249
`Patent 7,693,002
`______________________
`
`DECLARATION OF DR. MASSOUD PEDRAM
`
`I, Massoud Pedram, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Qualcomm Incorporated
`
`(“Qualcomm” or “Patent Owner”) in the matter of the Inter Partes Review of U.S.
`
`Patent No. 7,693,002 (“the ’002 patent”).
`
`2.
`
`I am being compensated for my work in this matter at my standard
`
`hourly rate of $900 for consulting services. My compensation in no way depends
`
`on the outcome of this proceeding.
`
`3.
`
`In preparing this Declaration, I considered the following materials:
`
`a. The ’002 patent (Ex. 1001) and its file history (Ex. 1002);
`
`QUALCOMM EXHIBIT 2001
`Apple v. Qualcomm
`IPR2018-01249
`Page 1
`
`
`
`b. Petition for Inter Partes Review of U.S. Patent No. 7,693,002,
`IPR2018-01249 (Paper 2);
`c. The Declaration of Dr. Robert W. Horst (Ex. 1003);
`d. U.S. Patent No. 4,951,259 to Sato (Ex. 1005) (“Sato”);
`e. U.S. Patent Pub. No. 2006/0098520 to Asano (Ex. 1006)
`(“Asano”);
`f. Kiyoo Itoh, VLSI Memory Chip Design, Springer 2001
`(Ex. 1007) (“Itoh”);
`g. U.S. Patent No. 5,602,796 to Sugio (Ex. 1012);
`h. U.S. Patent No. 5,291,076 to Bridges (Ex. 1008);
`i. Decision - Institution of Inter Partes Review (Paper 6);
`j.
`IEEE Dictionary (Ex. 2002);
`k. Additional portions of Itoh (Ex. 2003) not included in
`Petitioner’s Ex. 1007; and
`l. Any other materials referenced herein.
`
`I.
`
`Professional Background
`4.
`I am a Professor of Electrical Engineering and Charles Lee Powell
`
`Chair in Electrical Engineering and Computer Science in the Viterbi School of
`
`Engineering at the University of Southern California (USC). From 2013 until early
`
`2017 I held the Stephen and Etta Varra Professorship in the Viterbi School of
`
`Engineering at USC.
`
`5.
`
`I am an expert on electronic design automation (EDA), Very Large
`
`Scale Integration (VLSI) design
`
`including digital
`
`integrated circuits and
`
`semiconductor memory, energy efficient design, hybrid electrical energy storage
`
`Page 2
`
`
`
`systems (HEESS), and power/thermal modeling and management in integrated
`
`circuits and systems including multiple-supply-voltage designs and power
`
`collapsing techniques and voltage regulation. I also have expertise in building,
`
`validating, and delivering voltage regulation and conversion and management
`
`circuits and, more generally, nano-electronic circuits and system-on-chip designs
`
`targeting applications ranging from high performance computing to low-power
`
`embedded computing.
`
`6.
`
`I earned my B.S. in Electrical Engineering from the California
`
`Institute of Technology in 1986. I earned my M.S. in Electrical Engineering and
`
`Computer Sciences from the University of California at Berkeley in 1989. During
`
`my Masters and Doctoral degree programs, I was a Graduate Student Researcher in
`
`the Department of Electrical Engineering and Computer Sciences at the University
`
`of California at Berkeley from 1986-1991. Concurrently I held a part-time
`
`Research Position, at the Xerox Palo Alto Research Center (“Xerox PARC”) from
`
`1987-1989. I then earned my Ph.D. in Electrical Engineering and Computer
`
`Sciences from the University of California at Berkeley in 1991.
`
`7.
`
`After receiving my doctorate, I was an Assistant Professor in the
`
`Department of Electrical Engineering at USC from 1991-1996. I was then an
`
`Associate Professor in the Department of Electrical Engineering at USC from
`
`1996-2000. After that I have been a Professor of Electrical Engineering and
`
`Page 3
`
`
`
`Computer Science in the Viterbi School of Engineering at the University of
`
`Southern California (USC).
`
`8.
`
`I am a named inventor on ten U.S. patents and a U.S. patent
`
`application. These patents relate to topics ranging from novel address bus encoding
`
`techniques to charge recycling based multi-threshold CMOS design, and from low
`
`leakage SRAMs to dynamic backlight scaling for power minimization. The
`
`recently-filed patent application focuses on design and implementation of a
`
`superconductive Field Programmable Gate Array (FPGA) fabric.
`
`9.
`
`I have (co-) published four books and more than 650 archival and
`
`conference papers and book chapters. My research ranges from computer-aided
`
`design techniques and tools targeting VLSI circuit and system design to FPGA
`
`fabric design and FPGA synthesis, from low power electronics and battery-
`
`powered embedded system design to power distribution, conversion and regulation.
`
`For this research, my students and I have received ten conference and journal Best
`
`Paper awards.
`
`10.
`
`In addition to my work at Xerox PARC, I have been a member of
`
`multiple technical and scientific advisory boards for high-tech companies,
`
`including EPIC Design, Magma Design Automation, and Atrenta Inc., all of which
`
`went on to have successful initial public offerings (IPOs) or were acquired.
`
`Page 4
`
`
`
`11.
`
`I have served as the (lead) principal investigator on many US
`
`government (including the National Science Foundation, the Defense Advanced
`
`Research Projects Agency, U.S. Department of Defense, and the Intelligence
`
`Advanced Research Projects Activity) and private industry (including the
`
`Semiconductor Research Corporation) research projects, for some of which I have
`
`been the lead investigator of a team comprised of tens of faculty, students, and
`
`industry collaborators.
`
`12.
`
`I was a recipient of the 1996 Presidential Early Career Award for
`
`Scientists and Engineers, and in 2000 I was selected as a Fellow of the IEEE and in
`
`2008 named as an ACM Distinguished Scientist.
`
`13.
`
`I received the 2015 IEEE Circuits and Systems Society Charles A.
`
`Desoer Technical Achievement Award for my contributions to modeling and
`
`design of lower power VLSI circuits and systems, and energy efficient computing.
`
`14.
`
`I was recognized as the Third Most Cited Author at the 50th
`
`anniversary of the Design Automation Conference, Austin, TX, in June 2013. I
`
`received a Top Three Author Award at the 20th Anniversary Asia and South
`
`Pacific Design Automation Conference, Chiba/Tokyo, Japan, in January 2015, and
`
`was named as the Second Most Prolific and Second Most Cited Author at the 20th
`
`Anniversary International Symposium on Low Power Electronics and Design,
`
`Rome, Italy, in July 2015.
`
`Page 5
`
`
`
`15.
`
`I received the USC Viterbi School of Engineering Senior Research
`
`Award in 2017.
`
`16.
`
`Since July 2012, I have been the Executive Committee Chair of the
`
`IEEE/ACM International Symposium on Low Power Electronics and Design, a
`
`technical conference which I co-founded in 1996.
`
`17.
`
`I was the Editor-in-Chief of the ACM Transactions on Design
`
`Automation of Electronic Systems from June 2008-May 2014. I was also the
`
`Inaugural Editor-in-Chief of the IEEE Journal on Emerging and Selected Topics in
`
`Circuits and Systems from January 2010-December 2013.
`
`18.
`
`I served as the VP of Publications and Chair of the Distinguished
`
`Lecturer Program of the IEEE Circuits and Systems Society in 2005-2006 and
`
`2003-2004, respectively. I served as a member of the Board of Governors, IEEE
`
`Circuits and Systems Society in 2000-2003. I served as the Technical Program
`
`Chair of the International Symposium on Low Power Electronics and Design,
`
`Monterey, CA, in August 1996 and the International Symposium on Physical
`
`Design, Del Mar, CA, in April 2002. I also served as the General Chair of the
`
`International Symposium on Low Power Electronics and Design, Monterey, CA, in
`
`August 1997, the International Symposium on Physical Design, Monterey, CA, in
`
`April 2003, and the International Symposium on Quality of Electronic Design, San
`
`Jose, CA, in April 2007.
`
`Page 6
`
`
`
`19. My curriculum vitae is attached to this declaration as Appendix A.
`
`II. Relevant Legal Standards
`20.
`I have been asked to provide my opinion as to whether claims 1-28
`
`and 31-37 of the ’002 patent would have been obvious to a person of ordinary skill
`
`in the art (“POSA”) at the time of the invention, in view of the alleged prior art.
`
`21.
`
`I am an engineer by training and profession. The opinions I am
`
`expressing in this Declaration involve the application of my engineering
`
`knowledge and experience to the evaluation of certain alleged prior art with respect
`
`to the ’002 patent. Aside from my experience in litigation support, my knowledge
`
`of patent law is no different than that of any lay person. Therefore, I have
`
`requested the attorneys from Jones Day, who represent Qualcomm, to provide me
`
`with guidance as to the applicable patent law in this matter. The paragraphs below
`
`express my understanding of how I must apply current principles related to
`
`patentability.
`
`22.
`
`It is my understanding that in determining whether a patent claim is
`
`obvious in view of the alleged prior art, the Patent Office must construe the claim
`
`by giving the claim its broadest reasonable interpretation consistent with the
`
`specification as it would have been understood by one of ordinary skill in the art.
`
`For the purposes of this review, I have construed each claim term in accordance
`
`Page 7
`
`
`
`with its plain and ordinary meaning under the required broadest reasonable
`
`interpretation.
`
`23.
`
`It
`
`is my understanding
`
`that a claim
`
`is unpatentable under
`
`35 U.S.C. § 103 if the claimed subject matter as a whole would have been obvious
`
`to a POSA at the time of the invention. I also understand that an obviousness
`
`analysis takes into account the scope and content of the prior art, the differences
`
`between the claimed subject matter and the prior art, and the level of ordinary skill
`
`in the art at the time of the invention.
`
`24.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art if it falls within
`
`the field of the inventor’s endeavor. In addition, a reference is prior art if it is
`
`reasonably pertinent to the particular problem with which the inventor was
`
`involved. A reference is reasonably pertinent if it logically would have
`
`commended itself to an inventor’s attention in considering his problem. If a
`
`reference relates to the same problem as the claimed invention, that supports use of
`
`the reference as prior art in an obviousness analysis.
`
`25. To assess the differences between prior art and the claimed subject
`
`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
`
`be considered as a whole. This “as a whole” assessment requires showing that one
`
`of ordinary skill in the art at the time of invention, confronted by the same
`
`Page 8
`
`
`
`problems as the inventor and with no knowledge of the claimed invention, would
`
`have selected the elements from the prior art and combined them in the claimed
`
`manner.
`
`26.
`
`It is my further understanding that the Supreme Court has recognized
`
`several rationales for combining references or modifying a reference to show
`
`obviousness of claimed subject matter. Some of these rationales include:
`
`combining prior art elements according to known methods to yield predictable
`
`results; simple substitution of one known element for another to obtain predictable
`
`results; a predictable use of prior art elements according to their established
`
`functions; applying a known technique to a known device (method or product)
`
`ready for improvement to yield predictable results; choosing from a finite number
`
`of identified, predictable solutions, with a reasonable expectation of success; and
`
`some teaching, suggestion, or motivation in the prior art that would have led one of
`
`ordinary skill to modify the prior art reference or to combine prior art reference
`
`teachings to arrive at the claimed invention.
`
`III. THE ’002 PATENT
`A. Technology Background and Overview of the ’002 Patent
`27. The ’002 patent generally relates to circuits and methods for accessing
`
`memory arrays in integrated circuits. The title of the patent is “Dynamic Word
`
`Line Drivers and Decoders for Memory Arrays.”
`
`Page 9
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`
`
`28. Random Access Memory (RAM) is generally organized into rows and
`
`columns, as shown in the following image:
`
`29. Cells are read from or written to by activating a wordline driver,
`
`which selects the appropriate row, and then using bitlines to either read from or
`
`write to a particular column. The cell that is in the row selected by the wordline
`
`driver and in the column selected by the bitline is the cell that is read from or
`
`
`
`written to.
`
`30. A cell in a memory array is addressed using a memory address, which
`
`can be split into a row address and a column address. Worldlines are selected by
`
`decoding the row address, and bitlines are selected by decoding the column address.
`
`Because the ’002 patent discloses structures and methods for activating wordlines
`
`Page 10
`
`
`
`of a memory array, the relevant memory address for purposes of the ’002 is the
`
`row address.
`
`31.
`
`SRAM (static random access memory) is used on processor chips to
`
`implement caches and scratchpad memory. SRAM, which is organized as a two-
`
`dimensional array of memory cells comprising row and columns, stores bits in a
`
`cross-coupled inverter pair configuration with two access transistors within an
`
`integrated circuit. Dynamic random-access memory (DRAM) is a type of storage
`
`that is widely used as the main memory for a computer system. DRAM, which is
`
`also organized as a two-dimensional memory array, stores each bit of data in a
`
`separate capacitor with a single access transistor within a DRAM chip. SRAM
`
`cells are bigger than DRAM cells (which explains the much higher density of
`
`DRAM storage) but have much lower access latency (mainly because they are on-
`
`chip.) Both SRAM and DRAM requires row and column address decoders to
`
`translate addresses to a desired group of bits (one word of 32 or 64 bits of data in
`
`case of caches, one block of 4 to 8 words in case of main memory) within the
`
`memory array. DRAM cells require periodic refresh to avoid data loss to leakage.
`
`SRAM cells do not require refresh since data is stored in a cross-coupled pair of
`
`inverters. Both SRAM and DRAM are examples of volatile memory, meaning that
`
`data is lost once power is removed.
`
`Page 11
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`
`
`32. One method of activating a particular wordline driver of a memory
`
`array that the ’002 patent discloses was in the prior art was to decode the entire
`
`row address at once and use the decoded signal, along with a clock signal, to
`
`activate a particular wordline driver. For example, the following simplified figure
`
`shows how a three-bit address can be decoded in a 3-to-8 bit decoder to activate a
`
`particular wordline driver when that decoded signal is combined with the output of
`
`a clock driver:
`
`
`
`Page 12
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`
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`33. Some disadvantages of using such a decoding scheme to activate
`
`wordline drivers include high power consumption and reduced access speed. Each
`
`wordline driver has an input capacitance that the clock driver must drive. Because
`
`most of the wordline drivers are not used, this scheme results in wasted power. In
`
`addition, because the clock driver needs to drive a relatively large capacitive load,
`
`the SRAM access time will be increased. Moreover, a full decoder would need to
`
`be larger to decode a desired number of address bits. For example, a full row
`
`address decoder for 6 bits will have to do a 6-to-64 bit decoding to generate 64
`
`decoded row line addresses, whereas a split row address decoder with 3-bit pre-
`
`decoding will have to do a 3-to-8 bit decoding to generate decoded addresses for
`
`eight groups of row addresses followed by eight other 3-to-8 bit decoders to pick
`
`the desired row address within a selected group. The logic realization cost of the
`
`latter design is much less than that of the former. The larger the decoder necessary
`
`to decode the row address, the more power it consumes, the more time it takes to
`
`decode the address, and the more area is needed to implement the decoder in
`
`silicon.
`
`34. The ’002 patent discloses improved structures and methods of
`
`activating a wordline driver that save power and increase the maximum speed of
`
`the circuit by providing a clock signal to only a selected group of wordline drivers,
`
`rather than all wordline drivers and address decoders. The patent discloses splitting
`
`Page 13
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`
`
`the address into two portions. Each address portion is decoded separately. A first
`
`logic decodes the first portion of the memory address, and a second logic decodes
`
`the second portion of the memory address. The first logic also receives a clock
`
`signal and applies the clock signal to selected clock output of a plurality of clock
`
`outputs. Each of the clock outputs is associated with a group of the wordline
`
`drivers. Only one of the clock outputs is selected at any time, which means only
`
`one group of wordline drivers is selected. The second logic decodes the second
`
`portion of the memory address and selectively activates a particular wordline
`
`driver according to the second portion of the memory address.
`
`35. An advantage of the patented circuit device of the ’002 patent is that a
`
`timing delay from the clock to the activation of a particular wordline is reduced.
`
`The first and second logics operate independently of each other and apply their
`
`respective outputs directly to wordline drivers in parallel, thus reducing a timing
`
`delay in providing the clock signal to a particular wordline driver. Still another
`
`advantage is that capacitive loading on the clock driver is reduced, thereby
`
`lowering power dissipation of the clock driver. Another advantage is that use of a
`
`conditional clock to apply a clock signal to a selected group of wordline drivers
`
`reduces power consumption of an address decoder of a memory device.
`
`Page 14
`
`
`
`B.
`36.
`
`Prosecution History of the ’002 Patent
`I have reviewed the prosecution history of the ’002 patent. See
`
`Ex. 1002. The following is a summary of key events.
`
`37. The initial application (Application No. 11/548,132) was filed on
`
`October 10, 2006. Ex. 1002 at 257-91.
`
`38.
`
`In a November 19, 2007 Office Action (Ex. 1002 at 226-35), claims 2,
`
`3, 5, 6, 10, 13, 14, 19-21, 23 and 24 were objected to as being dependent upon a
`
`rejected base claim, but the examiner indicated that they would be allowable if
`
`rewritten in independent form including all of the limitations of the base claim and
`
`any intervening claims. The examiner rejected (i) claims 1, 4, 7-9, 11, 12, 15, and
`
`16 under § 102(b) as allegedly being anticipated by Iwahashi (U.S. Patent
`
`6,856,574), (ii) claims 17 and 18 under § 102(b) as allegedly being anticipated by
`
`Sugio (U.S. Patent 5,602,796), and (iii) claims 22 and 25 under § 102(b) as
`
`allegedly being anticipated by Kato (U.S. Patent Application 2001/0015926).
`
`39. Applicant filed an amendment on February 19, 2008. Ex. 1002
`
`at 193-212. The only amendments to the rejected claims were minor and made to
`
`overcome an objection and fix a typo. Applicant added thirteen new claims, with
`
`the new claims including previously objected to claims rewritten in independent
`
`form. Applicant argued that the cited references did not anticipate any of the
`
`claims.
`
`Page 15
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`
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`40. On April 28, 2008, the examiner issued a restriction requirement
`
`(Ex. 1002 at 181-85), asserting that certain claims were directed to addressing
`
`(Species I, claims 1-16, 22-25, 28-35, 39 and 40), while others were directed to
`
`particular wordline drivers (Species II, claims 17-21, 26, 27 and 36-38). On
`
`May 20, 2008, in response to the restriction requirement, the Applicant elected
`
`Species I. Ex. 1002 at 179-80.
`
`41.
`
`In a July 30, 2008 non-final rejection (Ex. 1002 at 160-66), the
`
`examiner rejected claims 22-25, 39, and 40 under § 102(b) as allegedly being
`
`anticipated by Iwahashi. The examiner allowed all other pending claims and noted
`
`that the prior art did not disclose a second logic to decode a second portion of the
`
`memory address to selectively activate a particular wordline driver.
`
`42. Applicant filed an amendment on December 6, 2008. Ex. 1002
`
`at 141-55. In this amendment, claims 22 and 39 were amended to recite limitations
`
`directed to the second logic. Applicant also added eight new claims. Seven of the
`
`new claims depended from claims noted to be allowable by the Office. New
`
`claim 48 was independent.
`
`43.
`
`In a January 28, 2008 final rejection, the examiner found that all
`
`pending claims were allowable, except for independent claim 48. Ex. 1002 at 120-
`
`26. Applicant subsequently canceled this claim in an amendment filed March 19,
`
`2009. Id. at 106-16.
`
`Page 16
`
`
`
`44. On April 2, 2009, the Office issued a notice of allowance. Ex. 1002
`
`at 85-88. On June 4, 2009, Applicant filed a request for continued examination
`
`(RCE) with an information disclosure statement listing Watanabe (U.S. Patent
`
`7,092,305). Id. at 64-83.
`
`45.
`
`In a non-final rejection dated June 17, 2009, the examiner rejected
`
`claims 7-10, 11-16, 22, 25, and 46 under § 102(b) as allegedly being anticipated by
`
`Watanabe. Ex. 1002 at 40-46. The examiner stated that claims 1-6, 28-35, 39, and
`
`40 were allowable over the prior art and noted that the prior art did not disclose
`
`“second logic to decode a second portion of the memory address, the second logic
`
`to selectively activate a particular wordline driver of the selected group of wordline
`
`drivers according to the second portion of the memory address,” among other
`
`limitations. Applicant subsequently filed an amendment on September 15, 2009 to
`
`amend rejected claims 7, 11, and 22 to include this allowable subject matter and
`
`thus overcome the rejections. Id. at 25-38.
`
`46. The Office
`
`issued
`
`a
`
`second
`
`notice
`
`of
`
`allowance
`
`on
`
`November 11, 2009. Ex. 1002 at 15-18. A March 10, 2010 Issue Notification
`
`states that the patent has a PTA of 0 days. Id. at 9-10.
`
`47. A Certificate of Correction issued July 5, 2011 corrects typographical
`
`errors. Ex. 1002 at 1-4.
`
`Page 17
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`
`
`C. Level of Skill in the Art
`48.
`I understand that Petitioner has proposed that a person of ordinary
`
`skill in the art relevant to the ’002 patent would have had at least an undergraduate
`
`degree in electrical engineering, or a related field, and three years of experience in
`
`the design of memory systems and circuits. Petition at 2. Petitioner has also
`
`proposed that a person of ordinary skill with less than the amount of experience
`
`noted above would have had a correspondingly greater amount of educational
`
`training such as a graduate degree in a related field. Id.
`
`49.
`
`I further understand that for purposes of its Institution Decision (“the
`
`Decision”), the USPTO’s Patent Trial and Appeal Board (“the Board”) accepted
`
`the assessment of the POSA offered by Petitioner, with the exception of the
`
`language “at least.” Institution Decision at 6.
`
`50.
`
`I do not dispute Petitioner’s proposed level of ordinary skill in the art
`
`as modified by the Board.
`
`51.
`
`It is my understanding that when interpreting the claims of
`
`the ’002 patent, I must do so based on the perspective of one of ordinary skill in
`
`the art at the relevant priority date. I understand that the ’002 patent has a priority
`
`date as of its filing date, October 10, 2006, and so I have interpreted the claims of
`
`the ’002 patent based on the perspective of the POSA as of that date.
`
`Page 18
`
`
`
`D. Claim Construction
`52.
`It is my understanding that in determining whether a patent claim is
`
`obvious in view of the prior art, the Patent Office must construe the claim by
`
`giving the claim its broadest reasonable interpretation consistent with the
`
`specification. For the purposes of this review, I have construed each claim term in
`
`accordance with its plain and ordinary meaning under the required broadest
`
`reasonable interpretation, as a person having ordinary skill in the art would
`
`understand. In my opinion, the claim term “clock signal” is in need of construction,
`
`and I provide my interpretation of this term below. I also address Petitioner’s
`
`proposed constructions below.
`
`“clock signal”
`
`53. The term “clock signal,” as recited in each of the independent claims
`
`of the ’002 patent, should be interpreted to mean “a periodic signal used for
`
`synchronization.” This interpretation is consistent with the plain and ordinary
`
`meaning of the term as understood by the POSA. The POSA’s understanding of
`
`the term is reflected, for example, by the IEEE Dictionary, which defines the term
`
`“clock signal” as “[a] periodic signal used for synchronizing events.” Ex. 2002
`
`at 9. The IEEE Dictionary is a reliable, unbiased authority, and in my opinion, it
`
`sets forth the definition of clock signal that would be understood by the POSA as
`
`of the filing date of the ’002 patent.
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`Page 19
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`
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`54. Support for this interpretation is also found in the ’002 patent itself.
`
`Specifically, the POSA would understand that the ’002 patent describes a
`
`synchronous memory system that uses a periodic clock signal. It does not describe
`
`an asynchronous memory system that uses multiple, non-periodic timing signals.
`
`The POSA would understand that the non-periodic timing signals of an
`
`asynchronous memory system are different than the periodic clock signal of a
`
`synchronous memory system. This is explained in detail below.
`
`55. Conventional SRAM and DRAM (RAM for short) are controlled
`
`asynchronously. Therefore, the memory latency and data toggle rate can be some
`
`fractional number of CPU clock cycles. More importantly, what makes the RAM
`
`asynchronous is that externally provided command inputs control latches and I/O
`
`buffers/drivers internal to RAM, and those external command inputs can arrive at
`
`the RAM’s pins at any time. Since asynchronous RAM does not operate based on
`
`any kind of periodic system clock that it shares with the CPU, the timings of the
`
`control signals, addresses, and data have to be consciously taken into account. In
`
`such asynchronous systems, where pulses or strobe signals are used to activate
`
`certain portions of the circuitry, the timing and duration of such signals must be
`
`explicitly specified. Furthermore, in such systems, the characteristics of the
`
`circuitry generating these timing signals must be clearly specified.
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`Page 20
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`
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`56. Asynchronous static RAMs (SRAMs) respond to asynchronous
`
`changes at the device’s address pins by generating multiple internal timing signals
`
`that are used to orchestrate the operation of the SRAM’s internal circuitry during a
`
`read or a write operation. Essentially, this means that there exists some control
`
`logic circuitry in the asynchronous SRAM that can asynchronously accept
`
`externally asserted control signals, read row and column addresses, and then
`
`generate appropriately timed sequences of internal timing signals (in the form of
`
`pulses or strobe signals) to direct the movement of data onto, within, and off of the
`
`SRAM. The external interface to the control logic on the asynchronous SRAM
`
`consists of essentially two signals: the active-low chip-select (CS#)1 and the active-
`
`low write enable (WE#). Various timing constraints among the external control
`
`signals and address/data signals must be satisfied in order to ensure correct
`
`operation.2 The duration and precise timing of internal timing signals is also key to
`
`
`1 In this declaration, the # symbol after a signal name means the
`complemented (active-low) form of the signal. For example, CS# (which is the
`same as CS_bar) indicates that the chip is selected when the value of the chip
`select signal CS is low.
`2 Typical timing specs for asynchronous SRAMs include many complicated
`requirements on and/or among external input/output signals. Examples include
`requirements on maximum access times from address and CS# low to data valid,
`maximum output disable times after CS# high, minimum write pulse width,
`minimum address setup time with respect to WE# low, minimum address hold time
`with respect to WE# high, minimum CS# setup time with respect to WE# high,
`minimum data setup and hold times with respect to WE# high, minimum output
`data valid after address change, and so on.
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`Page 21
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`
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`the correct operation of the device. Guaranteeing that the controller can
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`successfully orchestrate various activities within the asynchronous SRAM under
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`subtle process-voltage-temperature (PVT) variations is an intricate task, which
`
`becomes ever more daunting as the access latencies are shortened and supply
`
`voltages are reduced. Asynchronous SRAMs thus run into limitations at the high
`
`end of the performance range.
`
`57. Asynchronous dynamic RAM (DRAM) devices likewise contain
`
`control logic circuitry to direct the movement of data onto, within, and off of the
`
`DRAM device. The control logic accepts externally asserted control (command)
`
`signals and then orchestrates precisely timed sequences of internal control signals
`
`to direct the movement of data. The external interface to the control logic
`
`comprises active low Row Address Strobe (RAS#), active low Column Address
`
`Strobe (CAS#), and active low Write Enable (WE#).
`
`58.
`
`In an asynchronous DRAM device, the logic control circuitry and an
`
`external memory controller directly control the movement of data. Moreover, the
`
`external interface is an asynchronous interface. The direct control of the internal
`
`circuitry of the DRAM device by the external memory controller means that the
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`DRAM device cannot be well pipelined, and new commands to the DRAM device
`
`cannot typically be initiated until the previous command completes the movement
`
`of data. The movement of data is measured and reported by DRAM manufacturers
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`Page 22
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`
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`in terms of nanoseconds. The asynchronous nature of the interface means that each
`
`time a new DRAM device is introduced, a new and different memory controller
`
`has to be developed. This fact also gives rise to a complex set of timing constraints
`
`that must be satisfied by the DRAM device.3
`
`59. The following diagram illustrates aspects of asynchronous memory
`
`systems:
`
`
`3 Typical timing specs for asynchronous DRAMs include many complicated
`requirements on and/or among external input/output signals. Examples include
`requirements on maximum data access times from RAS# low and CAS# low,
`maximum output disable time from CAS# high, minimum RAS# high (precharge)
`and low (access) durations, minimum CAS# high (precharge) and low (access)
`durations, minimum write pulse duration, minimum row address setup and hold
`times with respect to RAS# low, minimum column address setup and hold times
`with respect to CAS# low, minimum and maximum delays from RAS# low to
`CAS# low and from RAS# low to WE# low, minimum Read command setup time,
`minimum Write command hold times from RAS# and CAS#, minimum data hold
`times after RAS#, CAS#, and WE#, and so on.
`
`Page 23
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`
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`
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`Ex. 2003 (Itoh) at 18. In the asynchronous operation of the DRAM chip depicted
`
`above, periodic clock signals are not used. Rather, the system is event-driven
`
`based on multiple, non-periodic timing signals RAS#, CAS#, and WE#. The
`
`timing signals RAS#, CAS#, and WE# are pulses or strobes without a periodic
`
`component. Internal activities of the DRAM chip (e.g. activation of a selected
`
`wordline (for example, W1) and appearance of data on I/O bus following the
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`sensing of the data stored in a selected memory cell (D1…D4)) are initiated by
`
`asynchronous transitions on RAS# and CAS#. The delay between values appearing
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`Page 24
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`
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`on the I/O bus and the output signals D0 are not synchronized with any transitions
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`on CAS# or RAS#. Indeed, this delay can only be reported in units of nanoseconds,
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`rather than in multiples of a system clock cycle. Finally, the RAS# and CAS#
`
`timing signals are not referred to as clock signals, as seen above.
`
`60. The POSA would understand that asynchronous systems do not use a
`
`periodic clock signal – rather, they use multiple, non-periodic timing signals, such
`
`as the RAS# and CAS# strobe signals shown above. As explained below,
`
`synchronous systems, by contrast, use a periodic clock signal, with all events being
`
`synchronized to the periodic signal.
`
`61. An alternative to asynchronous memory
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